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util_cpack: interface updates

main
Rejeesh Kutty 2016-05-16 12:17:45 -04:00
parent 6bc05fc844
commit e05204a86d
1 changed files with 73 additions and 43 deletions
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116
library/util_cpack/util_cpack_hw.tcl
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@ -39,67 +39,97 @@ set_parameter_property NUM_OF_CHANNELS HDL_PARAMETER true
# defaults
ad_alt_intf clock adc_clk input 1
ad_alt_intf reset adc_rst input 1 if_adc_clk
ad_alt_intf signal adc_valid output 1 valid
ad_alt_intf signal adc_sync output 1 sync
ad_alt_intf reset adc_rst input 1 if_adc_clk
ad_alt_intf signal adc_valid output 1 valid
ad_alt_intf signal adc_sync output 1 sync
ad_alt_intf signal adc_data output NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH data
add_interface fifo_ch_0 conduit end
#set_interface_property fifo_ch_0 associatedClock if_adc_clk
add_interface_port fifo_ch_0 adc_enable_0 enable Input 1
add_interface_port fifo_ch_0 adc_valid_0 valid Input 1
add_interface_port fifo_ch_0 adc_data_0 data Input CHANNEL_DATA_WIDTH
add_interface adc_ch_0 conduit end
add_interface_port adc_ch_0 adc_enable_0 enable Input 1
add_interface_port adc_ch_0 adc_valid_0 valid Input 1
add_interface_port adc_ch_0 adc_data_0 data Input CHANNEL_DATA_WIDTH
set_interface_property adc_ch_0 associatedClock if_adc_clk
set_interface_property adc_ch_0 associatedReset if_adc_rst
proc p_util_cpack {} {
if {[get_parameter_value NUM_OF_CHANNELS] > 1} {
add_interface fifo_ch_1 conduit end
#set_interface_property fifo_ch_1 associatedClock if_adc_clk
add_interface_port fifo_ch_1 adc_enable_1 enable Input 1
add_interface_port fifo_ch_1 adc_valid_1 valid Input 1
add_interface_port fifo_ch_1 adc_data_1 data Input CHANNEL_DATA_WIDTH
add_interface adc_ch_1 conduit end
add_interface_port adc_ch_1 adc_enable_1 enable Input 1
add_interface_port adc_ch_1 adc_valid_1 valid Input 1
add_interface_port adc_ch_1 adc_data_1 data Input CHANNEL_DATA_WIDTH
set_interface_property adc_ch_1 associatedClock if_adc_clk
set_interface_property adc_ch_1 associatedReset if_adc_rst
}
if {[get_parameter_value NUM_OF_CHANNELS] > 2} {
add_interface fifo_ch_2 conduit end
#set_interface_property fifo_ch_2 associatedClock if_adc_clk
add_interface_port fifo_ch_2 adc_enable_2 enable Input 1
add_interface_port fifo_ch_2 adc_valid_2 valid Input 1
add_interface_port fifo_ch_2 adc_data_2 data Input CHANNEL_DATA_WIDTH
add_interface adc_ch_2 conduit end
add_interface_port adc_ch_2 adc_enable_2 enable Input 1
add_interface_port adc_ch_2 adc_valid_2 valid Input 1
add_interface_port adc_ch_2 adc_data_2 data Input CHANNEL_DATA_WIDTH
set_interface_property adc_ch_2 associatedClock if_adc_clk
set_interface_property adc_ch_2 associatedReset if_adc_rst
}
if {[get_parameter_value NUM_OF_CHANNELS] > 3} {
add_interface fifo_ch_3 conduit end
#set_interface_property fifo_ch_3 associatedClock if_adc_clk
add_interface_port fifo_ch_3 adc_enable_3 enable Input 1
add_interface_port fifo_ch_3 adc_valid_3 valid Input 1
add_interface_port fifo_ch_3 adc_data_3 data Input CHANNEL_DATA_WIDTH
add_interface adc_ch_3 conduit end
add_interface_port adc_ch_3 adc_enable_3 enable Input 1
add_interface_port adc_ch_3 adc_valid_3 valid Input 1
add_interface_port adc_ch_3 adc_data_3 data Input CHANNEL_DATA_WIDTH
set_interface_property adc_ch_3 associatedClock if_adc_clk
set_interface_property adc_ch_3 associatedReset if_adc_rst
}
if {[get_parameter_value NUM_OF_CHANNELS] > 4} {
add_interface fifo_ch_4 conduit end
#set_interface_property fifo_ch_4 associatedClock if_adc_clk
add_interface_port fifo_ch_4 adc_enable_4 enable Input 1
add_interface_port fifo_ch_4 adc_valid_4 valid Input 1
add_interface_port fifo_ch_4 adc_data_4 data Input CHANNEL_DATA_WIDTH
add_interface adc_ch_4 conduit end
add_interface_port adc_ch_4 adc_enable_4 enable Input 1
add_interface_port adc_ch_4 adc_valid_4 valid Input 1
add_interface_port adc_ch_4 adc_data_4 data Input CHANNEL_DATA_WIDTH
set_interface_property adc_ch_4 associatedClock if_adc_clk
set_interface_property adc_ch_4 associatedReset if_adc_rst
}
if {[get_parameter_value NUM_OF_CHANNELS] > 5} {
add_interface fifo_ch_5 conduit end
#set_interface_property fifo_ch_5 associatedClock if_adc_clk
add_interface_port fifo_ch_5 adc_enable_5 enable Input 1
add_interface_port fifo_ch_5 adc_valid_5 valid Input 1
add_interface_port fifo_ch_5 adc_data_5 data Input CHANNEL_DATA_WIDTH
add_interface adc_ch_5 conduit end
add_interface_port adc_ch_5 adc_enable_5 enable Input 1
add_interface_port adc_ch_5 adc_valid_5 valid Input 1
add_interface_port adc_ch_5 adc_data_5 data Input CHANNEL_DATA_WIDTH
set_interface_property adc_ch_5 associatedClock if_adc_clk
set_interface_property adc_ch_5 associatedReset if_adc_rst
}
if {[get_parameter_value NUM_OF_CHANNELS] > 6} {
add_interface fifo_ch_6 conduit end
#set_interface_property fifo_ch_6 associatedClock if_adc_clk
add_interface_port fifo_ch_6 adc_enable_6 enable Input 1
add_interface_port fifo_ch_6 adc_valid_6 valid Input 1
add_interface_port fifo_ch_6 adc_data_6 data Input CHANNEL_DATA_WIDTH
add_interface adc_ch_6 conduit end
add_interface_port adc_ch_6 adc_enable_6 enable Input 1
add_interface_port adc_ch_6 adc_valid_6 valid Input 1
add_interface_port adc_ch_6 adc_data_6 data Input CHANNEL_DATA_WIDTH
set_interface_property adc_ch_6 associatedClock if_adc_clk
set_interface_property adc_ch_6 associatedReset if_adc_rst
}
if {[get_parameter_value NUM_OF_CHANNELS] > 7} {
add_interface fifo_ch_7 conduit end
#set_interface_property fifo_ch_7 associatedClock if_adc_clk
add_interface_port fifo_ch_7 adc_enable_7 enable Input 1
add_interface_port fifo_ch_7 adc_valid_7 valid Input 1
add_interface_port fifo_ch_7 adc_data_7 data Input CHANNEL_DATA_WIDTH
add_interface adc_ch_7 conduit end
add_interface_port adc_ch_7 adc_enable_7 enable Input 1
add_interface_port adc_ch_7 adc_valid_7 valid Input 1
add_interface_port adc_ch_7 adc_data_7 data Input CHANNEL_DATA_WIDTH
set_interface_property adc_ch_7 associatedClock if_adc_clk
set_interface_property adc_ch_7 associatedReset if_adc_rst
}
}