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daq3/a10gx: Add external falsh support

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Istvan Csomortani 2017-10-06 08:45:33 +01:00
parent be4e02aed9
commit df70a6605c
2 changed files with 41 additions and 1 deletions
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11
projects/daq3/a10gx/system_constr.sdc
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@ -9,3 +9,14 @@ set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_je
set_false_path -from [get_clocks *outclk0*] -through [get_nets *altera_jesd204*] -to [get_clocks {sys_clk_100mhz}]
set_false_path -to [get_registers *altera_jesd204_rx_csr_inst|phy_csr_rx_pcfifo_full_latched*]
# flash interface
set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_addr[*]} ]
set_input_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_data[*]} ]
set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_data[*]} ]
set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_cen[*]} ]
set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_oen} ]
set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_resetn} ]
set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_wen} ]
set_false_path -from * -to [get_ports {flash_resetn}]

31
projects/daq3/a10gx/system_top.v
View File

@ -77,6 +77,17 @@ module system_top (
input [ 10:0] gpio_bd_i,
output [ 15:0] gpio_bd_o,
// flash
output flash_oen,
output [ 1:0] flash_cen,
output [ 27:0] flash_addr,
inout [ 31:0] flash_data,
output flash_wen,
output flash_advn,
output flash_clk,
output flash_resetn,
// lane interface
input rx_ref_clk,
@ -119,6 +130,7 @@ module system_top (
wire spi_miso_s;
wire spi_mosi_s;
wire [ 7:0] spi_csn_s;
wire [ 23:0] flash_addr_raw;
// daq3
@ -163,6 +175,18 @@ module system_top (
assign gpio_bd_o = gpio_o[15:0];
// User code space at offset 0x0930_0000 per Altera's Board Update Portal
// reference design used to program flash
assign flash_addr = flash_addr_raw + 28'h9300000;
// Common Flash interface assignments
assign flash_resetn = 1'b1; // user_resetn; flash ready after FPGA is configured, reset during configuration
assign flash_advn = 1'b0;
assign flash_clk = 1'b0;
assign flash_cen[1] = flash_cen[0]; // select both flash devices for double-wide 32 bit data width
system_bd i_system_bd (
.sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
.sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
@ -212,7 +236,12 @@ module system_top (
.tx_sync_export (tx_sync),
.tx_sysref_export (tx_sysref),
.sys_clk_clk (sys_clk),
.sys_rst_reset_n (sys_resetn));
.sys_rst_reset_n (sys_resetn),
.sys_flash_tcm_address_out (flash_addr_raw),
.sys_flash_tcm_read_n_out (flash_oen),
.sys_flash_tcm_write_n_out (flash_wen),
.sys_flash_tcm_data_out (flash_data),
.sys_flash_tcm_chipselect_n_out (flash_cen[0]));
endmodule