avl_dacfifo: Update IP to qsys flow

library/altera/avl_dacfifo/avl_dacfifo.v

@@ -38,7 +38,9 @@
 module avl_dacfifo #(
 
   parameter   DAC_DATA_WIDTH = 64,
+  parameter   DAC_MEM_ADDRESS_WIDTH = 8,
   parameter   DMA_DATA_WIDTH = 64,
+  parameter   DMA_MEM_ADDRESS_WIDTH = 8,
   parameter   AVL_DATA_WIDTH = 512,
   parameter   AVL_ADDRESS_WIDTH = 25,
   parameter   AVL_BASE_ADDRESS = 32'h00000000,
@@ -121,7 +123,7 @@ module avl_dacfifo #(
     .AVL_DATA_WIDTH (AVL_DATA_WIDTH),
     .DMA_DATA_WIDTH (DMA_DATA_WIDTH),
     .AVL_DDR_BASE_ADDRESS (AVL_BASE_ADDRESS),
-    .DMA_MEM_ADDRESS_WIDTH(8)
+    .DMA_MEM_ADDRESS_WIDTH(DMA_MEM_ADDRESS_WIDTH)
   ) i_wr (
     .dma_clk (dma_clk),
     .dma_data (dma_data),
@@ -148,7 +150,7 @@ module avl_dacfifo #(
     .DAC_DATA_WIDTH(DAC_DATA_WIDTH),
     .AVL_DDR_BASE_ADDRESS(AVL_BASE_ADDRESS),
     .AVL_DDR_ADDRESS_LIMIT(AVL_ADDRESS_LIMIT),
-    .DAC_MEM_ADDRESS_WIDTH(8)
+    .DAC_MEM_ADDRESS_WIDTH(DAC_MEM_ADDRESS_WIDTH)
   ) i_rd (
     .dac_clk(dac_clk),
     .dac_reset(dac_rst),

library/altera/avl_dacfifo/avl_dacfifo_hw.tcl

@@ -4,8 +4,8 @@ source ../../scripts/adi_env.tcl
 source ../../scripts/adi_ip_alt.tcl
 
 ad_ip_create avl_dacfifo {Avalon DDR DAC Fifo}
+set_module_property ELABORATION_CALLBACK p_avl_dacfifo
 ad_ip_files avl_dacfifo [list\
-  $ad_hdl_dir/library/altera/common/ad_mem_asym.v \
   $ad_hdl_dir/library/common/util_dacfifo_bypass.v \
   $ad_hdl_dir/library/common/util_delay.v \
   $ad_hdl_dir/library/common/ad_b2g.v \
@@ -19,8 +19,11 @@ ad_ip_files avl_dacfifo [list\
 
 # parameters
 
+ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
 ad_ip_parameter DAC_DATA_WIDTH INTEGER 64
+ad_ip_parameter DAC_MEM_ADDRESS_WIDTH INTEGER 8
 ad_ip_parameter DMA_DATA_WIDTH INTEGER 64
+ad_ip_parameter DMA_MEM_ADDRESS_WIDTH INTEGER 8
 ad_ip_parameter AVL_DATA_WIDTH INTEGER 512
 ad_ip_parameter AVL_ADDRESS_WIDTH INTEGER 25
 ad_ip_parameter AVL_BASE_ADDRESS INTEGER 0
@@ -67,3 +70,36 @@ set_interface_property amm_ddr associatedClock avl_clock
 set_interface_property amm_ddr associatedReset avl_reset
 set_interface_property amm_ddr addressUnits WORDS
 
+# elaborate
+
+proc p_avl_dacfifo {} {
+
+  # read parameters
+
+  set m_device_family [get_parameter_value "DEVICE_FAMILY"]
+  set m_dma_data_width [get_parameter_value "DMA_DATA_WIDTH"]
+  set m_dma_mem_addr_width [get_parameter_value "DMA_MEM_ADDRESS_WIDTH"]
+  set m_avl_data_width [get_parameter_value "AVL_DATA_WIDTH"]
+  set m_avl_addr_width [get_parameter_value "AVL_ADDRESS_WIDTH"]
+  set m_dac_data_width [get_parameter_value "DAC_DATA_WIDTH"]
+  set m_dac_mem_addr_width [get_parameter_value "DAC_MEM_ADDRESS_WIDTH"]
+
+  # altera memory for WRITE side
+
+  add_hdl_instance alt_mem_asym_wr alt_mem_asym
+  set_instance_parameter_value alt_mem_asym_wr DEVICE_FAMILY $m_device_family
+  set_instance_parameter_value alt_mem_asym_wr A_ADDRESS_WIDTH $m_dma_mem_addr_width
+  set_instance_parameter_value alt_mem_asym_wr A_DATA_WIDTH $m_dma_data_width
+  set_instance_parameter_value alt_mem_asym_wr B_DATA_WIDTH $m_avl_data_width
+
+  # altera memory for READ side
+
+  add_hdl_instance alt_mem_asym_rd alt_mem_asym
+  set_instance_parameter_value alt_mem_asym_rd DEVICE_FAMILY $m_device_family
+  set_instance_parameter_value alt_mem_asym_rd A_ADDRESS_WIDTH 0
+  set_instance_parameter_value alt_mem_asym_rd A_DATA_WIDTH $m_avl_data_width
+  set_instance_parameter_value alt_mem_asym_rd B_ADDRESS_WIDTH $m_dac_mem_addr_width
+  set_instance_parameter_value alt_mem_asym_rd B_DATA_WIDTH $m_dac_data_width
+
+}
+

library/altera/avl_dacfifo/avl_dacfifo_rd.v

@@ -140,19 +140,14 @@ module avl_dacfifo_rd #(
   // interface
   // ==========================================================================
 
-  ad_mem_asym #(
+  alt_mem_asym_rd i_mem_asym (
-    .A_ADDRESS_WIDTH (AVL_MEM_ADDRESS_WIDTH),
+    .mem_i_wrclock (avl_clk),
-    .A_DATA_WIDTH (AVL_DATA_WIDTH),
+    .mem_i_wren (avl_mem_wr_enable),
-    .B_ADDRESS_WIDTH (DAC_MEM_ADDRESS_WIDTH),
+    .mem_i_wraddress (avl_mem_wr_address),
-    .B_DATA_WIDTH (DAC_DATA_WIDTH))
+    .mem_i_datain (avl_mem_data),
-  i_mem_asym (
+    .mem_i_rdclock (dac_clk),
-    .clka (avl_clk),
+    .mem_i_rdaddress (dac_mem_rd_address),
-    .wea (avl_mem_wr_enable),
+    .mem_o_dataout (dac_mem_data_s));
-    .addra (avl_mem_wr_address),
-    .dina (avl_mem_data),
-    .clkb (dac_clk),
-    .addrb (dac_mem_rd_address),
-    .doutb (dac_mem_data_s));
 
   // ==========================================================================
   // Avalon Memory Mapped interface access
@@ -230,7 +225,7 @@ module avl_dacfifo_rd #(
     .dout (avl_mem_wr_address_b2g_s));
 
   // ==========================================================================
-  // control the FIFO to prevent overflow, underfloq is monitored
+  // control the FIFO to prevent overflow, underflow is monitored
   // ==========================================================================
 
   assign avl_mem_rd_address_s = (MEM_RATIO ==  1) ? avl_mem_rd_address :

library/altera/avl_dacfifo/avl_dacfifo_wr.v

@@ -135,19 +135,14 @@ module avl_dacfifo_wr #(
   // An asymmetric memory to transfer data from DMAC interface to AXI Memory Map
   // interface
 
-  ad_mem_asym #(
+  alt_mem_asym_wr i_mem_asym (
-    .A_ADDRESS_WIDTH (DMA_MEM_ADDRESS_WIDTH),
+    .mem_i_wrclock (dma_clk),
-    .A_DATA_WIDTH (DMA_DATA_WIDTH),
+    .mem_i_wren (dma_mem_wea_s),
-    .B_ADDRESS_WIDTH (AVL_MEM_ADDRESS_WIDTH),
+    .mem_i_wraddress (dma_mem_wr_address),
-    .B_DATA_WIDTH (AVL_DATA_WIDTH))
+    .mem_i_datain (dma_data),
-  i_mem_asym (
+    .mem_i_rdclock (avl_clk),
-    .clka (dma_clk),
+    .mem_i_rdaddress (avl_mem_rd_address),
-    .wea (dma_mem_wea_s),
+    .mem_o_dataout (avl_mem_rdata_s));
-    .addra (dma_mem_wr_address),
-    .dina (dma_data),
-    .clkb (avl_clk),
-    .addrb (avl_mem_rd_address),
-    .doutb (avl_mem_rdata_s));
 
   // the fifo reset is the dma_xfer_req