From de53a6190266e00b3517ffab514332df63f55257 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 4 Nov 2015 13:31:50 +0200 Subject: [PATCH] util_adcfifo: Put a limit on the read/write address from memory so there is no overflow Added altera component --- library/util_adcfifo/util_adcfifo.v | 41 ++++++++------- library/util_adcfifo/util_adcfifo_hw.tcl | 66 ++++++++++++++++++++++++ 2 files changed, 88 insertions(+), 19 deletions(-) create mode 100755 library/util_adcfifo/util_adcfifo_hw.tcl diff --git a/library/util_adcfifo/util_adcfifo.v b/library/util_adcfifo/util_adcfifo.v index 210f38ea2..f1a2db291 100644 --- a/library/util_adcfifo/util_adcfifo.v +++ b/library/util_adcfifo/util_adcfifo.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,16 +21,16 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -66,10 +66,10 @@ module util_adcfifo ( parameter DMA_ADDRESS_WIDTH = 10; localparam DMA_MEM_RATIO = ADC_DATA_WIDTH/DMA_DATA_WIDTH; - localparam ADC_ADDRESS_WIDTH = (DMA_MEM_RATIO == 2) ? (DMA_ADDRESS_WIDTH - 1) : + localparam ADC_ADDRESS_WIDTH = (DMA_MEM_RATIO == 1) ? (DMA_ADDRESS_WIDTH) : (DMA_MEM_RATIO == 2) ? (DMA_ADDRESS_WIDTH - 1) : ((DMA_MEM_RATIO == 4) ? (DMA_ADDRESS_WIDTH - 2) : (DMA_ADDRESS_WIDTH - 3)); localparam ADC_ADDR_LIMIT = (2**ADC_ADDRESS_WIDTH)-1; - + // adc interface input adc_rst; @@ -94,21 +94,21 @@ module util_adcfifo ( reg adc_xfer_enable = 'd0; reg adc_wr_int = 'd0; reg [ADC_DATA_WIDTH-1:0] adc_wdata_int = 'd0; - reg [ADC_ADDRESS_WIDTH-1:0] adc_waddr_int = 'd0; + reg [ADC_ADDRESS_WIDTH-1:0] adc_waddr_int = 'd0; reg adc_waddr_rel_t = 'd0; - reg [ADC_ADDRESS_WIDTH-1:0] adc_waddr_rel = 'd0; + reg [ADC_ADDRESS_WIDTH-1:0] adc_waddr_rel = 'd0; reg dma_rst = 'd0; reg [ 2:0] dma_waddr_rel_t_m = 'd0; - reg [ADC_ADDRESS_WIDTH-1:0] dma_waddr_rel = 'd0; + reg [ADC_ADDRESS_WIDTH-1:0] dma_waddr_rel = 'd0; reg dma_rd = 'd0; reg dma_rd_d = 'd0; reg [DMA_DATA_WIDTH-1:0] dma_rdata_d = 'd0; - reg [DMA_ADDRESS_WIDTH-1:0] dma_raddr = 'd0; + reg [DMA_ADDRESS_WIDTH-1:0] dma_raddr = 'd0; // internal signals wire dma_waddr_rel_t_s; - wire [DMA_ADDRESS_WIDTH-1:0] dma_waddr_rel_s; + wire [DMA_ADDRESS_WIDTH-1:0] dma_waddr_rel_s; wire dma_wready_s; wire dma_rd_s; wire [DMA_DATA_WIDTH-1:0] dma_rdata_s; @@ -127,13 +127,14 @@ module util_adcfifo ( adc_xfer_init <= adc_xfer_req_m[1] & ~adc_xfer_req_m[2]; if (adc_xfer_init == 1'b1) begin adc_xfer_enable <= 1'b1; - end else if ((adc_waddr_int >= ADC_ADDR_LIMIT) || + end else if ((adc_waddr_int >= ADC_ADDR_LIMIT - 1) || (adc_xfer_req_m[2] == 1'b0)) begin adc_xfer_enable <= 1'b0; end end end + always @(posedge adc_clk or posedge adc_rst) begin if (adc_rst == 1'b1) begin adc_wr_int <= 'd0; @@ -159,7 +160,7 @@ module util_adcfifo ( adc_waddr_rel_t <= 'd0; adc_waddr_rel <= 'd0; end else begin - if ((adc_wr_int == 1'b1) && (adc_waddr_int[2:0] == 3'd7)) begin + if ((adc_wr_int == 1'b1) && (adc_waddr_int[2:0] == 3'h7)) begin adc_waddr_rel_t <= ~adc_waddr_rel_t; adc_waddr_rel <= adc_waddr_int; end @@ -170,7 +171,7 @@ module util_adcfifo ( assign dma_xfer_status = 4'd0; assign dma_waddr_rel_t_s = dma_waddr_rel_t_m[2] ^ dma_waddr_rel_t_m[1]; - assign dma_waddr_rel_s = (DMA_MEM_RATIO == 2) ? {dma_waddr_rel, 1'd0} : + assign dma_waddr_rel_s = (DMA_MEM_RATIO == 1) ? dma_waddr_rel : (DMA_MEM_RATIO == 2) ? {dma_waddr_rel, 1'd0} : ((DMA_MEM_RATIO == 4) ? {dma_waddr_rel, 2'd0} : {dma_waddr_rel, 3'd0}); always @(posedge dma_clk) begin @@ -186,9 +187,9 @@ module util_adcfifo ( end end end - + assign dma_wready_s = (DMA_READY_ENABLE == 0) ? 1'b1 : dma_wready; - assign dma_rd_s = (dma_raddr >= dma_waddr_rel_s) ? 1'b0 : dma_wready_s; + assign dma_rd_s = (dma_raddr < ADC_ADDR_LIMIT) ? ((dma_raddr >= dma_waddr_rel_s) ? 1'b0 : dma_wready_s) : dma_wready_s ; always @(posedge dma_clk) begin if (dma_xfer_req == 1'b0) begin @@ -201,7 +202,9 @@ module util_adcfifo ( dma_rd_d <= dma_rd; dma_rdata_d <= dma_rdata_s; if (dma_rd_s == 1'b1) begin - dma_raddr <= dma_raddr + 1'b1; + if (dma_raddr < ADC_ADDR_LIMIT) begin + dma_raddr <= dma_raddr + 1'b1; + end end end end @@ -222,7 +225,7 @@ module util_adcfifo ( .addrb (dma_raddr), .doutb (dma_rdata_s)); - ad_axis_inf_rx #(.DATA_WIDTH(DMA_DATA_WIDTH)) i_axis_inf ( + ad_axis_inf_rx #(.DATA_WIDTH(DMA_DATA_WIDTH)) i_axis_inf ( .clk (dma_clk), .rst (dma_rst), .valid (dma_rd_d), diff --git a/library/util_adcfifo/util_adcfifo_hw.tcl b/library/util_adcfifo/util_adcfifo_hw.tcl new file mode 100755 index 000000000..d3c8417cd --- /dev/null +++ b/library/util_adcfifo/util_adcfifo_hw.tcl @@ -0,0 +1,66 @@ + + +package require -exact qsys 15.0 +source ../scripts/adi_env.tcl +source ../scripts/adi_ip_alt.tcl + + +set_module_property NAME util_adcfifo +set_module_property DESCRIPTION "ADC FIFO utility" +set_module_property VERSION 1.0 +set_module_property GROUP "Analog Devices" +set_module_property DISPLAY_NAME util_adcfifo + +# files + +add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" +set_fileset_property quartus_synth TOP_LEVEL util_adcfifo + +add_fileset_file ad_axis_inf_rx.v VERILOG PATH ../common/ad_axis_inf_rx.v +add_fileset_file ad_mem_asym.v VERILOG PATH ../common/ad_mem_asym.v +add_fileset_file util_adcfifo.v VERILOG PATH util_adcfifo.v TOP_LEVEL_FILE +add_fileset_file util_adcfifo_constr.sdc SDC PATH util_adcfifo_constr.sdc + +# parameters + +add_parameter ADC_DATA_WIDTH INTEGER 0 +set_parameter_property ADC_DATA_WIDTH DEFAULT_VALUE 256 +set_parameter_property ADC_DATA_WIDTH DISPLAY_NAME ADC_DATA_WIDTH +set_parameter_property ADC_DATA_WIDTH TYPE INTEGER +set_parameter_property ADC_DATA_WIDTH UNITS None +set_parameter_property ADC_DATA_WIDTH HDL_PARAMETER true + +add_parameter DMA_DATA_WIDTH INTEGER 0 +set_parameter_property DMA_DATA_WIDTH DEFAULT_VALUE 64 +set_parameter_property DMA_DATA_WIDTH DISPLAY_NAME DMA_DATA_WIDTH +set_parameter_property DMA_DATA_WIDTH TYPE INTEGER +set_parameter_property DMA_DATA_WIDTH UNITS None +set_parameter_property DMA_DATA_WIDTH HDL_PARAMETER true + +add_parameter DMA_READY_ENABLE INTEGER 0 +set_parameter_property DMA_READY_ENABLE DEFAULT_VALUE 1 +set_parameter_property DMA_READY_ENABLE DISPLAY_NAME DMA_READY_ENABLE +set_parameter_property DMA_READY_ENABLE TYPE INTEGER +set_parameter_property DMA_READY_ENABLE UNITS None +set_parameter_property DMA_READY_ENABLE HDL_PARAMETER true + +add_parameter DMA_ADDRESS_WIDTH INTEGER 0 +set_parameter_property DMA_ADDRESS_WIDTH DEFAULT_VALUE 10 +set_parameter_property DMA_ADDRESS_WIDTH DISPLAY_NAME DMA_ADDRESS_WIDTH +set_parameter_property DMA_ADDRESS_WIDTH TYPE INTEGER +set_parameter_property DMA_ADDRESS_WIDTH UNITS None +set_parameter_property DMA_ADDRESS_WIDTH HDL_PARAMETER true + +# defaults + +ad_alt_intf clock adc_clk input 1 adc_clk +ad_alt_intf reset adc_rst input 1 if_adc_clk +ad_alt_intf signal adc_wr input 1 adc_valid +ad_alt_intf signal adc_wdata input ADC_DATA_WIDTH adc_data +ad_alt_intf signal adc_wovf output 1 adc_dovf + +ad_alt_intf clock dma_clk input 1 clk +ad_alt_intf signal dma_wr output 1 valid +ad_alt_intf signal dma_wdata output DMA_DATA_WIDTH data +ad_alt_intf signal dma_wready input 1 ready +ad_alt_intf signal dma_xfer_req input 1 xfer_req