axi_mc_speed: Updated for motor control revision 2
Adrian Costina
parent
d5fa0071bd
commit
de12184038
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@ -39,14 +39,12 @@
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module axi_mc_speed
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#(
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parameter C_S_AXI_MIN_SIZE = 32'hffff,
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parameter MOTOR_CONTROL_REVISION = 2
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parameter C_S_AXI_MIN_SIZE = 32'hffff
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)
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//----------- Ports Declarations -----------------------------------------------
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(
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// physical interface
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input [2:0] position_i,
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input [2:0] bemf_i,
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output [2:0] position_o,
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output [31:0] speed_o,
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output new_speed_o,
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@ -54,16 +52,7 @@ module axi_mc_speed
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input ref_clk,
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// dma interface
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output adc_clk_o,
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output adc_dwr_o,
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output [31:0] adc_ddata_o,
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input adc_dovf_i,
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input adc_dunf_i,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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@ -82,19 +71,11 @@ module axi_mc_speed
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output s_axi_rvalid,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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input s_axi_rready,
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// debug signals
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output adc_mon_valid,
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output [31:0] adc_mon_data);
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input s_axi_rready);
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//------------------------------------------------------------------------------
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//----------- Registers Declarations -------------------------------------------
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//------------------------------------------------------------------------------
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reg adc_valid = 'd0;
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reg [31:0] adc_data = 'd0;
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reg [31:0] up_rdata = 'd0;
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reg up_wack = 'd0;
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reg up_rack = 'd0;
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@ -103,14 +84,11 @@ reg up_rack = 'd0;
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//----------- Wires Declarations -----------------------------------------------
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//------------------------------------------------------------------------------
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// internal clocks & resets
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wire adc_rst;
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wire up_rstn;
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wire up_clk;
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// internal signals
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wire adc_start_s;
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wire [31:0] speed_data_s;
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wire adc_enable_s;
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wire adc_status_s;
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@ -123,7 +101,6 @@ wire [31:0] up_adc_common_rdata_s;
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wire up_adc_common_wack_s;
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wire up_adc_common_rack_s;
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wire [31:0] pid_s;
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wire [ 2:0] position_s;
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wire [ 2:0] bemf_s;
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wire [ 2:0] bemf_delayed_s;
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@ -134,34 +111,15 @@ wire [ 2:0] bemf_multiplex_s;
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//----------- Assign/Always Blocks ---------------------------------------------
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//------------------------------------------------------------------------------
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign adc_clk_o = ref_clk;
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assign adc_dwr_o = adc_valid;
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assign adc_ddata_o = adc_data;
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// monitor signals
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assign adc_mon_valid = new_speed_s;
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assign adc_mon_data = { 20'h0, bemf_multiplex_s, bemf_s, bemf_delayed_s, position_s };
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assign bemf_multiplex_s =(MOTOR_CONTROL_REVISION == 2) ? position_i : bemf_i;
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assign bemf_s = position_s ;
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assign position_o =(hall_bemf_i == 2'b01) ? bemf_delayed_s : position_s;
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assign new_speed_o = new_speed_s;
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assign speed_o = speed_data_s;
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// adc channels - dma interface
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always @(posedge ref_clk)
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begin
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adc_data <= speed_data_s;
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adc_valid <= new_speed_s;
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end
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// processor read interface
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always @(negedge up_rstn or posedge up_clk)
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begin
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if(up_rstn == 0)
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@ -178,7 +136,6 @@ begin
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end
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// HALL sensors debouncers
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debouncer
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#( .DEBOUNCER_LEN(400))
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position_0(
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@ -203,31 +160,6 @@ position_2(
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.sig_i(position_i[2]),
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.sig_o(position_s[2]));
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// BEMF debouncer
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debouncer
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#( .DEBOUNCER_LEN(400))
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bemf_0(
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.clk_i(ref_clk),
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.rst_i(adc_rst),
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.sig_i(bemf_multiplex_s[0]),
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.sig_o(bemf_s[0]));
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debouncer
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#( .DEBOUNCER_LEN(400))
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bemf_1(
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.clk_i(ref_clk),
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.rst_i(adc_rst),
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.sig_i(bemf_multiplex_s[1]),
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.sig_o(bemf_s[1]));
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debouncer
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#( .DEBOUNCER_LEN(400))
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bemf_2(
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.clk_i(ref_clk),
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.rst_i(adc_rst),
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.sig_i(bemf_multiplex_s[2]),
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.sig_o(bemf_s[2]));
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delay_30_degrees delay_30_degrees_i1(
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.clk_i(ref_clk),
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.rst_i(adc_rst),
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@ -247,8 +179,7 @@ speed_detector_inst(
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.current_speed_o(),
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.speed_o(speed_data_s));
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// common processor control
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// common processor control
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up_adc_common i_up_adc_common(
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.mmcm_rst(),
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.adc_clk(ref_clk),
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@ -257,9 +188,15 @@ up_adc_common i_up_adc_common(
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.adc_ddr_edgesel(),
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.adc_pin_mode(),
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.adc_status(1'b1),
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.adc_status_ovf(adc_dovf_i),
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.adc_status_unf(adc_dunf_i),
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.adc_sync_status(1'b1),
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.adc_status_ovf(),
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.adc_status_unf(),
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.adc_clk_ratio(32'd1),
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.adc_start_code(),
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.adc_sync(),
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.up_status_pn_err(1'b0),
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.up_status_pn_oos(1'b0),
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.up_status_or(1'b0),
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.delay_clk(1'b0),
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.delay_rst(),
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.delay_sel(),
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@ -279,8 +216,8 @@ up_adc_common i_up_adc_common(
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.drp_ready(1'b0),
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.drp_locked(1'b0),
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.up_usr_chanmax(),
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.adc_usr_chanmax(8'd0),
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.up_adc_gpio_in(),
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.adc_usr_chanmax(8'd2),
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.up_adc_gpio_in(32'h0),
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.up_adc_gpio_out(),
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.up_rstn(up_rstn),
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.up_clk(up_clk),
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@ -294,7 +231,6 @@ up_adc_common i_up_adc_common(
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.up_rack (up_adc_common_rack_s));
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// up bus interface
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up_axi i_up_axi(
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.up_rstn(up_rstn),
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.up_clk(up_clk),
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@ -325,6 +261,5 @@ up_axi i_up_axi(
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.up_rack (up_rack));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@ -77,6 +77,7 @@ reg [DEBOUNCER_LEN-1:0] shift_reg;
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//------------------------------------------------------------------------------
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//----------- Assign/Always Blocks ---------------------------------------------
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//------------------------------------------------------------------------------
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always @(posedge clk_i)
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begin
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if(rst_i == 1)
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@ -83,12 +83,12 @@ localparam IDLE = 6'b100000;
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//------------------------------------------------------------------------------
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//----------- Registers Declarations -------------------------------------------
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//------------------------------------------------------------------------------
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reg [5:0] state; // current state
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reg [5:0] next_state; // next state
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reg [2:0] position_old; // saves the latest position
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reg [31:0] speed_count; // counts the current speed of rotation
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reg [31:0] speed_divider; // divides the speed of rotation by 2, correspoding to 30 degrees
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reg [31:0] delay_count; // Applied the delay to the input signal
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reg [5:0] state = RESET; // current state
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reg [5:0] next_state = RESET; // next state
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reg [2:0] position_old = 3'h0; // saves the latest position
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reg [31:0] speed_count = 32'h0; // counts the current speed of rotation
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reg [31:0] speed_divider = 32'h0; // divides the speed of rotation by 2, correspoding to 30 degrees
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reg [31:0] delay_count = 32'h0; // Applied the delay to the input signal
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//------------------------------------------------------------------------------
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//----------- Assign/Always Blocks ---------------------------------------------
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@ -77,9 +77,7 @@ module speed_detector
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//------------------------------------------------------------------------------
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//----------- Local Parameters -------------------------------------------------
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//------------------------------------------------------------------------------
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localparam AW = LOG_2_AW - 1;
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localparam MAX_SPEED_CNT = 32'h10000;
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//State machine
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@ -94,7 +92,6 @@ localparam IDLE = 8'b10000000;
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//------------------------------------------------------------------------------
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//----------- Registers Declarations -------------------------------------------
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//------------------------------------------------------------------------------
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reg [ 2:0] position_old;
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reg [63:0] avg_register;
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reg [63:0] avg_register_stable;
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@ -113,7 +110,6 @@ reg [ 7:0] next_state;
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//------------------------------------------------------------------------------
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//----------- Assign/Always Blocks ---------------------------------------------
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//------------------------------------------------------------------------------
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// Count ticks per position
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always @(posedge clk_i)
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begin
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