diff --git a/library/axi_mc_speed/axi_mc_speed.v b/library/axi_mc_speed/axi_mc_speed.v index 1515a7287..c26591fbd 100644 --- a/library/axi_mc_speed/axi_mc_speed.v +++ b/library/axi_mc_speed/axi_mc_speed.v @@ -39,14 +39,12 @@ module axi_mc_speed #( - parameter C_S_AXI_MIN_SIZE = 32'hffff, - parameter MOTOR_CONTROL_REVISION = 2 + parameter C_S_AXI_MIN_SIZE = 32'hffff ) //----------- Ports Declarations ----------------------------------------------- ( // physical interface input [2:0] position_i, - input [2:0] bemf_i, output [2:0] position_o, output [31:0] speed_o, output new_speed_o, @@ -54,16 +52,7 @@ module axi_mc_speed input ref_clk, - // dma interface - - output adc_clk_o, - output adc_dwr_o, - output [31:0] adc_ddata_o, - input adc_dovf_i, - input adc_dunf_i, - // axi interface - input s_axi_aclk, input s_axi_aresetn, input s_axi_awvalid, @@ -82,19 +71,11 @@ module axi_mc_speed output s_axi_rvalid, output [ 1:0] s_axi_rresp, output [31:0] s_axi_rdata, - input s_axi_rready, - -// debug signals - - output adc_mon_valid, - output [31:0] adc_mon_data); + input s_axi_rready); //------------------------------------------------------------------------------ //----------- Registers Declarations ------------------------------------------- //------------------------------------------------------------------------------ - -reg adc_valid = 'd0; -reg [31:0] adc_data = 'd0; reg [31:0] up_rdata = 'd0; reg up_wack = 'd0; reg up_rack = 'd0; @@ -103,14 +84,11 @@ reg up_rack = 'd0; //----------- Wires Declarations ----------------------------------------------- //------------------------------------------------------------------------------ // internal clocks & resets - wire adc_rst; wire up_rstn; wire up_clk; // internal signals - -wire adc_start_s; wire [31:0] speed_data_s; wire adc_enable_s; wire adc_status_s; @@ -123,45 +101,25 @@ wire [31:0] up_adc_common_rdata_s; wire up_adc_common_wack_s; wire up_adc_common_rack_s; wire [31:0] pid_s; - -wire [ 2:0] position_s; -wire [ 2:0] bemf_s; -wire [ 2:0] bemf_delayed_s; -wire new_speed_s; -wire [ 2:0] bemf_multiplex_s; +wire [ 2:0] position_s; +wire [ 2:0] bemf_s; +wire [ 2:0] bemf_delayed_s; +wire new_speed_s; +wire [ 2:0] bemf_multiplex_s; //------------------------------------------------------------------------------ //----------- Assign/Always Blocks --------------------------------------------- //------------------------------------------------------------------------------ // signal name changes - assign up_clk = s_axi_aclk; assign up_rstn = s_axi_aresetn; -assign adc_clk_o = ref_clk; -assign adc_dwr_o = adc_valid; -assign adc_ddata_o = adc_data; - -// monitor signals - -assign adc_mon_valid = new_speed_s; -assign adc_mon_data = { 20'h0, bemf_multiplex_s, bemf_s, bemf_delayed_s, position_s }; - -assign bemf_multiplex_s =(MOTOR_CONTROL_REVISION == 2) ? position_i : bemf_i; +assign bemf_s = position_s ; assign position_o =(hall_bemf_i == 2'b01) ? bemf_delayed_s : position_s; assign new_speed_o = new_speed_s; assign speed_o = speed_data_s; -// adc channels - dma interface - -always @(posedge ref_clk) -begin - adc_data <= speed_data_s; - adc_valid <= new_speed_s; -end - // processor read interface - always @(negedge up_rstn or posedge up_clk) begin if(up_rstn == 0) @@ -178,7 +136,6 @@ begin end // HALL sensors debouncers - debouncer #( .DEBOUNCER_LEN(400)) position_0( @@ -203,31 +160,6 @@ position_2( .sig_i(position_i[2]), .sig_o(position_s[2])); -// BEMF debouncer -debouncer -#( .DEBOUNCER_LEN(400)) -bemf_0( - .clk_i(ref_clk), - .rst_i(adc_rst), - .sig_i(bemf_multiplex_s[0]), - .sig_o(bemf_s[0])); - -debouncer -#( .DEBOUNCER_LEN(400)) -bemf_1( - .clk_i(ref_clk), - .rst_i(adc_rst), - .sig_i(bemf_multiplex_s[1]), - .sig_o(bemf_s[1])); - -debouncer -#( .DEBOUNCER_LEN(400)) -bemf_2( - .clk_i(ref_clk), - .rst_i(adc_rst), - .sig_i(bemf_multiplex_s[2]), - .sig_o(bemf_s[2])); - delay_30_degrees delay_30_degrees_i1( .clk_i(ref_clk), .rst_i(adc_rst), @@ -247,8 +179,7 @@ speed_detector_inst( .current_speed_o(), .speed_o(speed_data_s)); - // common processor control - +// common processor control up_adc_common i_up_adc_common( .mmcm_rst(), .adc_clk(ref_clk), @@ -257,9 +188,15 @@ up_adc_common i_up_adc_common( .adc_ddr_edgesel(), .adc_pin_mode(), .adc_status(1'b1), - .adc_status_ovf(adc_dovf_i), - .adc_status_unf(adc_dunf_i), + .adc_sync_status(1'b1), + .adc_status_ovf(), + .adc_status_unf(), .adc_clk_ratio(32'd1), + .adc_start_code(), + .adc_sync(), + .up_status_pn_err(1'b0), + .up_status_pn_oos(1'b0), + .up_status_or(1'b0), .delay_clk(1'b0), .delay_rst(), .delay_sel(), @@ -279,8 +216,8 @@ up_adc_common i_up_adc_common( .drp_ready(1'b0), .drp_locked(1'b0), .up_usr_chanmax(), - .adc_usr_chanmax(8'd0), - .up_adc_gpio_in(), + .adc_usr_chanmax(8'd2), + .up_adc_gpio_in(32'h0), .up_adc_gpio_out(), .up_rstn(up_rstn), .up_clk(up_clk), @@ -294,7 +231,6 @@ up_adc_common i_up_adc_common( .up_rack (up_adc_common_rack_s)); // up bus interface - up_axi i_up_axi( .up_rstn(up_rstn), .up_clk(up_clk), @@ -325,6 +261,5 @@ up_axi i_up_axi( .up_rack (up_rack)); endmodule - // *************************************************************************** // *************************************************************************** diff --git a/library/axi_mc_speed/axi_mc_speed_ip.tcl b/library/axi_mc_speed/axi_mc_speed_ip.tcl old mode 100755 new mode 100644 diff --git a/library/axi_mc_speed/debouncer.v b/library/axi_mc_speed/debouncer.v index d48869e26..33def31bc 100644 --- a/library/axi_mc_speed/debouncer.v +++ b/library/axi_mc_speed/debouncer.v @@ -77,6 +77,7 @@ reg [DEBOUNCER_LEN-1:0] shift_reg; //------------------------------------------------------------------------------ //----------- Assign/Always Blocks --------------------------------------------- //------------------------------------------------------------------------------ + always @(posedge clk_i) begin if(rst_i == 1) diff --git a/library/axi_mc_speed/delay_30_degrees.v b/library/axi_mc_speed/delay_30_degrees.v index ef6363848..407a66628 100644 --- a/library/axi_mc_speed/delay_30_degrees.v +++ b/library/axi_mc_speed/delay_30_degrees.v @@ -83,12 +83,12 @@ localparam IDLE = 6'b100000; //------------------------------------------------------------------------------ //----------- Registers Declarations ------------------------------------------- //------------------------------------------------------------------------------ -reg [5:0] state; // current state -reg [5:0] next_state; // next state -reg [2:0] position_old; // saves the latest position -reg [31:0] speed_count; // counts the current speed of rotation -reg [31:0] speed_divider; // divides the speed of rotation by 2, correspoding to 30 degrees -reg [31:0] delay_count; // Applied the delay to the input signal +reg [5:0] state = RESET; // current state +reg [5:0] next_state = RESET; // next state +reg [2:0] position_old = 3'h0; // saves the latest position +reg [31:0] speed_count = 32'h0; // counts the current speed of rotation +reg [31:0] speed_divider = 32'h0; // divides the speed of rotation by 2, correspoding to 30 degrees +reg [31:0] delay_count = 32'h0; // Applied the delay to the input signal //------------------------------------------------------------------------------ //----------- Assign/Always Blocks --------------------------------------------- diff --git a/library/axi_mc_speed/speed_detector.v b/library/axi_mc_speed/speed_detector.v index ac09d238c..43962928d 100644 --- a/library/axi_mc_speed/speed_detector.v +++ b/library/axi_mc_speed/speed_detector.v @@ -77,9 +77,7 @@ module speed_detector //------------------------------------------------------------------------------ //----------- Local Parameters ------------------------------------------------- //------------------------------------------------------------------------------ - localparam AW = LOG_2_AW - 1; - localparam MAX_SPEED_CNT = 32'h10000; //State machine @@ -94,14 +92,13 @@ localparam IDLE = 8'b10000000; //------------------------------------------------------------------------------ //----------- Registers Declarations ------------------------------------------- //------------------------------------------------------------------------------ - reg [ 2:0] position_old; reg [63:0] avg_register; reg [63:0] avg_register_stable; reg [31:0] cnt_period; -reg [31:0] decimation; // register used to divide by ten the speed +reg [31:0] decimation; // register used to divide by ten the speed reg [31:0] cnt_period_old; -reg [31:0] fifo [0:((2**LOG_2_AW)-1)]; // 32 bit wide RAM +reg [31:0] fifo [0:((2**LOG_2_AW)-1)]; // 32 bit wide RAM reg [AW:0] write_addr; reg [AW:0] read_addr; @@ -113,7 +110,6 @@ reg [ 7:0] next_state; //------------------------------------------------------------------------------ //----------- Assign/Always Blocks --------------------------------------------- //------------------------------------------------------------------------------ - // Count ticks per position always @(posedge clk_i) begin