From ddd8a14790df3a00ae204ca3a6b728f057a49d82 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Tue, 2 Feb 2021 09:44:10 +0000 Subject: [PATCH] ad9081_fmca_ebz: Remove system reset from Xilinx PHY Reset in device clock domain caused timing failures. Since link reconfiguration is not supported the reset is not required. --- projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl index 6118d385b..90711fddf 100644 --- a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl +++ b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl @@ -380,11 +380,11 @@ ad_connect $sys_dma_resetn axi_mxfe_tx_dma/m_src_axi_aresetn ad_connect $sys_dma_reset mxfe_dac_fifo/dma_rst if {$ADI_PHY_SEL == 0} { -ad_connect tx_device_clk_rstgen/peripheral_reset jesd204_phy_121/tx_sys_reset -ad_connect tx_device_clk_rstgen/peripheral_reset jesd204_phy_126/tx_sys_reset +ad_connect jesd204_phy_121/tx_sys_reset GND +ad_connect jesd204_phy_126/tx_sys_reset GND -ad_connect rx_device_clk_rstgen/peripheral_reset jesd204_phy_121/rx_sys_reset -ad_connect rx_device_clk_rstgen/peripheral_reset jesd204_phy_126/rx_sys_reset +ad_connect jesd204_phy_121/rx_sys_reset GND +ad_connect jesd204_phy_126/rx_sys_reset GND ad_connect axi_mxfe_tx_jesd/tx_axi/device_reset jesd204_phy_121/tx_reset_gt ad_connect axi_mxfe_rx_jesd/rx_axi/device_reset jesd204_phy_121/rx_reset_gt