fmcomms2_udc: Initial check in
FMCOMMS2 with an additional SPI port for the up/down converter boardmain
Istvan Csomortani
parent
6f77af4aff
commit
ddc7c845e9
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@ -0,0 +1,29 @@
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# spi interface
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set spi_udc_clk_i [create_bd_port -dir I spi_udc_clk_i]
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set spi_udc_clk_o [create_bd_port -dir O spi_udc_clk_o]
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set spi_udc_csn_i [create_bd_port -dir I spi_udc_csn_i]
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set spi_udc_csn_tx_o [create_bd_port -dir O spi_udc_csn_tx_o]
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set spi_udc_csn_rx_o [create_bd_port -dir O spi_udc_csn_rx_o]
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set spi_udc_mosi_i [create_bd_port -dir I spi_udc_mosi_i]
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set spi_udc_mosi_o [create_bd_port -dir O spi_udc_mosi_o]
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set spi_udc_miso_i [create_bd_port -dir I spi_udc_miso_i]
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# additions to default configuration
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set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7
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# spi connections
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connect_bd_net -net spi_udc_csn_i [get_bd_ports spi_udc_csn_i] [get_bd_pins sys_ps7/SPI1_SS_I]
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connect_bd_net -net spi_udc_csn_tx_o [get_bd_ports spi_udc_csn_tx_o] [get_bd_pins sys_ps7/SPI1_SS_O]
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connect_bd_net -net spi_udc_csn_rx_o [get_bd_ports spi_udc_csn_rx_o] [get_bd_pins sys_ps7/SPI1_SS1_O]
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connect_bd_net -net spi_udc_clk_i [get_bd_ports spi_udc_clk_i] [get_bd_pins sys_ps7/SPI1_SCLK_I]
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connect_bd_net -net spi_udc_clk_o [get_bd_ports spi_udc_clk_o] [get_bd_pins sys_ps7/SPI1_SCLK_O]
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connect_bd_net -net spi_udc_mosi_i [get_bd_ports spi_udc_mosi_i] [get_bd_pins sys_ps7/SPI1_MOSI_I]
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connect_bd_net -net spi_udc_mosi_o [get_bd_ports spi_udc_mosi_o] [get_bd_pins sys_ps7/SPI1_MOSI_O]
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connect_bd_net -net spi_udc_miso_i [get_bd_ports spi_udc_miso_i] [get_bd_pins sys_ps7/SPI1_MISO_I]
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@ -0,0 +1,5 @@
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source $ad_hdl_dir/projects/common/zc702/zc702_system_bd.tcl
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source $ad_hdl_dir/projects/fmcomms2/common/fmcomms2_bd.tcl
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source ../common/udconv_bd.tcl
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@ -0,0 +1,15 @@
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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set project_name udconv_zc702
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adi_project_create $project_name
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adi_project_files $project_name [list "$ad_hdl_dir/library/common/ad_iobuf.v" \
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"system_top.v" \
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"$ad_hdl_dir/projects/common/zc702/zc702_system_constr.xdc" \
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"$ad_hdl_dir/projects/fmcomms2/zc702/system_constr.xdc"]
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adi_project_run $project_name
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@ -0,0 +1,267 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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DDR_addr,
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DDR_ba,
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DDR_cas_n,
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DDR_ck_n,
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DDR_ck_p,
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DDR_cke,
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DDR_cs_n,
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DDR_dm,
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DDR_dq,
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DDR_dqs_n,
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DDR_dqs_p,
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DDR_odt,
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DDR_ras_n,
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DDR_reset_n,
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DDR_we_n,
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FIXED_IO_ddr_vrn,
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FIXED_IO_ddr_vrp,
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FIXED_IO_mio,
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FIXED_IO_ps_clk,
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FIXED_IO_ps_porb,
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FIXED_IO_ps_srstb,
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gpio_bd,
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hdmi_out_clk,
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hdmi_vsync,
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hdmi_hsync,
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hdmi_data_e,
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hdmi_data,
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spdif,
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iic_scl,
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iic_sda,
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rx_clk_in_p,
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rx_clk_in_n,
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rx_frame_in_p,
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rx_frame_in_n,
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rx_data_in_p,
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rx_data_in_n,
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tx_clk_out_p,
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tx_clk_out_n,
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tx_frame_out_p,
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tx_frame_out_n,
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tx_data_out_p,
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tx_data_out_n,
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gpio_txnrx,
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gpio_enable,
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gpio_resetb,
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gpio_sync,
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gpio_en_agc,
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gpio_ctl,
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gpio_status,
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spi_csn,
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spi_clk,
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spi_mosi,
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spi_miso);
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inout [14:0] DDR_addr;
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inout [ 2:0] DDR_ba;
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inout DDR_cas_n;
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inout DDR_ck_n;
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inout DDR_ck_p;
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inout DDR_cke;
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inout DDR_cs_n;
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inout [ 3:0] DDR_dm;
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inout [31:0] DDR_dq;
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inout [ 3:0] DDR_dqs_n;
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inout [ 3:0] DDR_dqs_p;
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inout DDR_odt;
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inout DDR_ras_n;
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inout DDR_reset_n;
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inout DDR_we_n;
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inout FIXED_IO_ddr_vrn;
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inout FIXED_IO_ddr_vrp;
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inout [53:0] FIXED_IO_mio;
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inout FIXED_IO_ps_clk;
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inout FIXED_IO_ps_porb;
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inout FIXED_IO_ps_srstb;
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inout [15:0] gpio_bd;
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output hdmi_out_clk;
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output hdmi_vsync;
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output hdmi_hsync;
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output hdmi_data_e;
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output [15:0] hdmi_data;
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output spdif;
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inout iic_scl;
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inout iic_sda;
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input rx_clk_in_p;
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input rx_clk_in_n;
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input rx_frame_in_p;
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input rx_frame_in_n;
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input [ 5:0] rx_data_in_p;
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input [ 5:0] rx_data_in_n;
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output tx_clk_out_p;
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output tx_clk_out_n;
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output tx_frame_out_p;
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output tx_frame_out_n;
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output [ 5:0] tx_data_out_p;
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output [ 5:0] tx_data_out_n;
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inout gpio_txnrx;
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inout gpio_enable;
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inout gpio_resetb;
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inout gpio_sync;
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inout gpio_en_agc;
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inout [ 3:0] gpio_ctl;
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inout [ 7:0] gpio_status;
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output spi_csn;
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output spi_clk;
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output spi_mosi;
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input spi_miso;
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// internal signals
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wire [48:0] gpio_i;
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wire [48:0] gpio_o;
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wire [48:0] gpio_t;
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wire spi_udc_csn_tx;
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wire spi_udc_csn_rx;
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wire spi_udc_sclk;
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wire spi_udc_data;
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// instantiations
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ad_iobuf #(.DATA_WIDTH(29)) i_iobuf (
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.dt ({gpio_t[48:32],gpio_t[15:8], gpio_t[3:0]}),
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.di ({gpio_o[48:32],gpio_o[15:8], gpio_o[3:0]}),
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.do ({gpio_i[48:32],gpio_i[15:8], gpio_i[3:0]}),
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.dio({ gpio_txnrx,
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gpio_enable,
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gpio_resetb,
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gpio_sync,
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gpio_en_agc,
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gpio_ctl,
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gpio_status,
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gpio_bd[15:8],
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gpio_bd[3:0]}));
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// udc spi is just output and connected PMOD2_x_LS
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ad_iobuf #(.DATA_WIDTH(4)) i_iobuf_spi (
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.dt ({4'd0}),
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.di ({spi_udc_csn_tx, spi_udc_csn_rx, spi_udc_data, spi_udc_sclk}),
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.do (),
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.dio(gpio_bd[7:4]));
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system_wrapper i_system_wrapper (
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.DDR_addr (DDR_addr),
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.DDR_ba (DDR_ba),
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.DDR_cas_n (DDR_cas_n),
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.DDR_ck_n (DDR_ck_n),
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.DDR_ck_p (DDR_ck_p),
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.DDR_cke (DDR_cke),
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.DDR_cs_n (DDR_cs_n),
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.DDR_dm (DDR_dm),
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.DDR_dq (DDR_dq),
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.DDR_dqs_n (DDR_dqs_n),
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.DDR_dqs_p (DDR_dqs_p),
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.DDR_odt (DDR_odt),
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.DDR_ras_n (DDR_ras_n),
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.DDR_reset_n (DDR_reset_n),
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.DDR_we_n (DDR_we_n),
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.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
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.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
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.FIXED_IO_mio (FIXED_IO_mio),
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.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
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.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
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.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
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.GPIO_I (gpio_i),
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.GPIO_O (gpio_o),
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.GPIO_T (gpio_t),
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.hdmi_data (hdmi_data),
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.hdmi_data_e (hdmi_data_e),
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.hdmi_hsync (hdmi_hsync),
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.hdmi_out_clk (hdmi_out_clk),
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.hdmi_vsync (hdmi_vsync),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.rx_clk_in_n (rx_clk_in_n),
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.rx_clk_in_p (rx_clk_in_p),
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.rx_data_in_n (rx_data_in_n),
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.rx_data_in_p (rx_data_in_p),
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.rx_frame_in_n (rx_frame_in_n),
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.rx_frame_in_p (rx_frame_in_p),
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.spdif (spdif),
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.spi_csn_i (1'b1),
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.spi_csn_o (spi_csn),
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.spi_miso_i (spi_miso),
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.spi_mosi_i (1'b0),
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.spi_mosi_o (spi_mosi),
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.spi_sclk_i (1'b0),
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.spi_sclk_o (spi_clk),
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.tx_clk_out_n (tx_clk_out_n),
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.tx_clk_out_p (tx_clk_out_p),
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.tx_data_out_n (tx_data_out_n),
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.tx_data_out_p (tx_data_out_p),
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.tx_frame_out_n (tx_frame_out_n),
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.tx_frame_out_p (tx_frame_out_p),
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.spi_udc_clk_i (1'b0),
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.spi_udc_clk_o (spi_udc_sclk),
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.spi_udc_csn_i (1'b1),
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.spi_udc_csn_tx_o (spi_udc_csn_tx),
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.spi_udc_csn_rx_o (spi_udc_csn_rx),
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.spi_udc_mosi_i (spi_udc_data),
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.spi_udc_mosi_o (spi_udc_data),
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.spi_udc_miso_i (1'b0));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@ -0,0 +1,5 @@
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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
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source $ad_hdl_dir/projects/fmcomms2/common/fmcomms2_bd.tcl
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source ../common/udconv_bd.tcl
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@ -0,0 +1,8 @@
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# spi pmod J58
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set_property -dict {PACKAGE_PIN AJ21 IOSTANDARD LVCMOS25} [get_ports spi_udc_csn_tx] ; ## PMOD1_0_LS
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set_property -dict {PACKAGE_PIN AK21 IOSTANDARD LVCMOS25} [get_ports spi_udc_csn_rx] ; ## PMOD1_1_LS
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set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS25} [get_ports spi_udc_sclk] ; ## PMOD1_3_LS
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set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS25} [get_ports spi_udc_data] ; ## PMOD1_2_LS
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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set project_name udconv_zc706
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adi_project_create $project_name
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adi_project_files $project_name [list "$ad_hdl_dir/library/common/ad_iobuf.v" \
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"system_top.v" \
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"system_constr.xdc" \
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"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" \
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"$ad_hdl_dir/projects/fmcomms2/zc706/system_constr.xdc"]
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adi_project_run $project_name
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@ -0,0 +1,265 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
// contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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DDR_addr,
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DDR_ba,
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DDR_cas_n,
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DDR_ck_n,
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DDR_ck_p,
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DDR_cke,
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DDR_cs_n,
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DDR_dm,
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DDR_dq,
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DDR_dqs_n,
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DDR_dqs_p,
|
||||
DDR_odt,
|
||||
DDR_ras_n,
|
||||
DDR_reset_n,
|
||||
DDR_we_n,
|
||||
|
||||
FIXED_IO_ddr_vrn,
|
||||
FIXED_IO_ddr_vrp,
|
||||
FIXED_IO_mio,
|
||||
FIXED_IO_ps_clk,
|
||||
FIXED_IO_ps_porb,
|
||||
FIXED_IO_ps_srstb,
|
||||
|
||||
gpio_bd,
|
||||
|
||||
hdmi_out_clk,
|
||||
hdmi_vsync,
|
||||
hdmi_hsync,
|
||||
hdmi_data_e,
|
||||
hdmi_data,
|
||||
|
||||
spdif,
|
||||
|
||||
iic_scl,
|
||||
iic_sda,
|
||||
|
||||
rx_clk_in_p,
|
||||
rx_clk_in_n,
|
||||
rx_frame_in_p,
|
||||
rx_frame_in_n,
|
||||
rx_data_in_p,
|
||||
rx_data_in_n,
|
||||
tx_clk_out_p,
|
||||
tx_clk_out_n,
|
||||
tx_frame_out_p,
|
||||
tx_frame_out_n,
|
||||
tx_data_out_p,
|
||||
tx_data_out_n,
|
||||
|
||||
gpio_txnrx,
|
||||
gpio_enable,
|
||||
gpio_resetb,
|
||||
gpio_sync,
|
||||
gpio_en_agc,
|
||||
gpio_ctl,
|
||||
gpio_status,
|
||||
|
||||
spi_csn,
|
||||
spi_clk,
|
||||
spi_mosi,
|
||||
spi_miso,
|
||||
|
||||
spi_udc_csn_tx,
|
||||
spi_udc_csn_rx,
|
||||
spi_udc_sclk,
|
||||
spi_udc_data);
|
||||
|
||||
inout [14:0] DDR_addr;
|
||||
inout [ 2:0] DDR_ba;
|
||||
inout DDR_cas_n;
|
||||
inout DDR_ck_n;
|
||||
inout DDR_ck_p;
|
||||
inout DDR_cke;
|
||||
inout DDR_cs_n;
|
||||
inout [ 3:0] DDR_dm;
|
||||
inout [31:0] DDR_dq;
|
||||
inout [ 3:0] DDR_dqs_n;
|
||||
inout [ 3:0] DDR_dqs_p;
|
||||
inout DDR_odt;
|
||||
inout DDR_ras_n;
|
||||
inout DDR_reset_n;
|
||||
inout DDR_we_n;
|
||||
|
||||
inout FIXED_IO_ddr_vrn;
|
||||
inout FIXED_IO_ddr_vrp;
|
||||
inout [53:0] FIXED_IO_mio;
|
||||
inout FIXED_IO_ps_clk;
|
||||
inout FIXED_IO_ps_porb;
|
||||
inout FIXED_IO_ps_srstb;
|
||||
|
||||
inout [14:0] gpio_bd;
|
||||
|
||||
output hdmi_out_clk;
|
||||
output hdmi_vsync;
|
||||
output hdmi_hsync;
|
||||
output hdmi_data_e;
|
||||
output [23:0] hdmi_data;
|
||||
|
||||
output spdif;
|
||||
|
||||
inout iic_scl;
|
||||
inout iic_sda;
|
||||
|
||||
input rx_clk_in_p;
|
||||
input rx_clk_in_n;
|
||||
input rx_frame_in_p;
|
||||
input rx_frame_in_n;
|
||||
input [ 5:0] rx_data_in_p;
|
||||
input [ 5:0] rx_data_in_n;
|
||||
output tx_clk_out_p;
|
||||
output tx_clk_out_n;
|
||||
output tx_frame_out_p;
|
||||
output tx_frame_out_n;
|
||||
output [ 5:0] tx_data_out_p;
|
||||
output [ 5:0] tx_data_out_n;
|
||||
|
||||
inout gpio_txnrx;
|
||||
inout gpio_enable;
|
||||
inout gpio_resetb;
|
||||
inout gpio_sync;
|
||||
inout gpio_en_agc;
|
||||
inout [ 3:0] gpio_ctl;
|
||||
inout [ 7:0] gpio_status;
|
||||
|
||||
output spi_csn;
|
||||
output spi_clk;
|
||||
output spi_mosi;
|
||||
input spi_miso;
|
||||
|
||||
output spi_udc_csn_tx;
|
||||
output spi_udc_csn_rx;
|
||||
output spi_udc_sclk;
|
||||
output spi_udc_data;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [48:0] gpio_i;
|
||||
wire [48:0] gpio_o;
|
||||
wire [48:0] gpio_t;
|
||||
|
||||
// instantiations
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(32)) i_iobuf (
|
||||
.dt ({gpio_t[48:32],gpio_t[14:0]}),
|
||||
.di ({gpio_o[48:32],gpio_o[14:0]}),
|
||||
.do ({gpio_i[48:32],gpio_i[14:0]}),
|
||||
.dio({ gpio_txnrx,
|
||||
gpio_enable,
|
||||
gpio_resetb,
|
||||
gpio_sync,
|
||||
gpio_en_agc,
|
||||
gpio_ctl,
|
||||
gpio_status,
|
||||
gpio_bd}));
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.DDR_addr (DDR_addr),
|
||||
.DDR_ba (DDR_ba),
|
||||
.DDR_cas_n (DDR_cas_n),
|
||||
.DDR_ck_n (DDR_ck_n),
|
||||
.DDR_ck_p (DDR_ck_p),
|
||||
.DDR_cke (DDR_cke),
|
||||
.DDR_cs_n (DDR_cs_n),
|
||||
.DDR_dm (DDR_dm),
|
||||
.DDR_dq (DDR_dq),
|
||||
.DDR_dqs_n (DDR_dqs_n),
|
||||
.DDR_dqs_p (DDR_dqs_p),
|
||||
.DDR_odt (DDR_odt),
|
||||
.DDR_ras_n (DDR_ras_n),
|
||||
.DDR_reset_n (DDR_reset_n),
|
||||
.DDR_we_n (DDR_we_n),
|
||||
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
|
||||
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
|
||||
.FIXED_IO_mio (FIXED_IO_mio),
|
||||
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
|
||||
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
|
||||
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
|
||||
.GPIO_I (gpio_i),
|
||||
.GPIO_O (gpio_o),
|
||||
.GPIO_T (gpio_t),
|
||||
.hdmi_data (hdmi_data),
|
||||
.hdmi_data_e (hdmi_data_e),
|
||||
.hdmi_hsync (hdmi_hsync),
|
||||
.hdmi_out_clk (hdmi_out_clk),
|
||||
.hdmi_vsync (hdmi_vsync),
|
||||
.iic_main_scl_io (iic_scl),
|
||||
.iic_main_sda_io (iic_sda),
|
||||
.rx_clk_in_n (rx_clk_in_n),
|
||||
.rx_clk_in_p (rx_clk_in_p),
|
||||
.rx_data_in_n (rx_data_in_n),
|
||||
.rx_data_in_p (rx_data_in_p),
|
||||
.rx_frame_in_n (rx_frame_in_n),
|
||||
.rx_frame_in_p (rx_frame_in_p),
|
||||
.spdif (spdif),
|
||||
.spi_csn_i (1'b1),
|
||||
.spi_csn_o (spi_csn),
|
||||
.spi_miso_i (spi_miso),
|
||||
.spi_mosi_i (1'b0),
|
||||
.spi_mosi_o (spi_mosi),
|
||||
.spi_sclk_i (1'b0),
|
||||
.spi_sclk_o (spi_clk),
|
||||
.tx_clk_out_n (tx_clk_out_n),
|
||||
.tx_clk_out_p (tx_clk_out_p),
|
||||
.tx_data_out_n (tx_data_out_n),
|
||||
.tx_data_out_p (tx_data_out_p),
|
||||
.tx_frame_out_n (tx_frame_out_n),
|
||||
.tx_frame_out_p (tx_frame_out_p),
|
||||
.spi_udc_clk_i (1'b0),
|
||||
.spi_udc_clk_o (spi_udc_sclk),
|
||||
.spi_udc_csn_i (1'b1),
|
||||
.spi_udc_csn_tx_o (spi_udc_csn_tx),
|
||||
.spi_udc_csn_rx_o (spi_udc_csn_rx),
|
||||
.spi_udc_mosi_i (spi_udc_data),
|
||||
.spi_udc_mosi_o (spi_udc_data),
|
||||
.spi_udc_miso_i (1'b0));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
|
||||
source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
|
||||
source $ad_hdl_dir/projects/fmcomms2/common/fmcomms2_bd.tcl
|
||||
source ../common/udconv_bd.tcl
|
||||
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
|
||||
# spi pmod JA1
|
||||
|
||||
set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports spi_udc_csn_tx] ; ## JA1
|
||||
set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS33} [get_ports spi_udc_csn_rx] ; ## JA2
|
||||
set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVCMOS33} [get_ports spi_udc_sclk] ; ## JA4
|
||||
set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS33} [get_ports spi_udc_data] ; ## JA3
|
||||
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_project.tcl
|
||||
|
||||
set project_name udconv_zed
|
||||
|
||||
adi_project_create $project_name
|
||||
|
||||
adi_project_files $project_name [list "$ad_hdl_dir/library/common/ad_iobuf.v" \
|
||||
"system_top.v" \
|
||||
"system_constr.xdc" \
|
||||
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \
|
||||
"$ad_hdl_dir/projects/fmcomms2/zed/system_constr.xdc"]
|
||||
|
||||
adi_project_run $project_name
|
||||
|
||||
|
|
@ -0,0 +1,314 @@
|
|||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2011(c) Analog Devices, Inc.
|
||||
//
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
// contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module system_top (
|
||||
|
||||
DDR_addr,
|
||||
DDR_ba,
|
||||
DDR_cas_n,
|
||||
DDR_ck_n,
|
||||
DDR_ck_p,
|
||||
DDR_cke,
|
||||
DDR_cs_n,
|
||||
DDR_dm,
|
||||
DDR_dq,
|
||||
DDR_dqs_n,
|
||||
DDR_dqs_p,
|
||||
DDR_odt,
|
||||
DDR_ras_n,
|
||||
DDR_reset_n,
|
||||
DDR_we_n,
|
||||
|
||||
FIXED_IO_ddr_vrn,
|
||||
FIXED_IO_ddr_vrp,
|
||||
FIXED_IO_mio,
|
||||
FIXED_IO_ps_clk,
|
||||
FIXED_IO_ps_porb,
|
||||
FIXED_IO_ps_srstb,
|
||||
|
||||
gpio_bd,
|
||||
|
||||
hdmi_out_clk,
|
||||
hdmi_vsync,
|
||||
hdmi_hsync,
|
||||
hdmi_data_e,
|
||||
hdmi_data,
|
||||
|
||||
i2s_mclk,
|
||||
i2s_bclk,
|
||||
i2s_lrclk,
|
||||
i2s_sdata_out,
|
||||
i2s_sdata_in,
|
||||
|
||||
spdif,
|
||||
|
||||
iic_scl,
|
||||
iic_sda,
|
||||
iic_mux_scl,
|
||||
iic_mux_sda,
|
||||
|
||||
otg_vbusoc,
|
||||
|
||||
rx_clk_in_p,
|
||||
rx_clk_in_n,
|
||||
rx_frame_in_p,
|
||||
rx_frame_in_n,
|
||||
rx_data_in_p,
|
||||
rx_data_in_n,
|
||||
tx_clk_out_p,
|
||||
tx_clk_out_n,
|
||||
tx_frame_out_p,
|
||||
tx_frame_out_n,
|
||||
tx_data_out_p,
|
||||
tx_data_out_n,
|
||||
|
||||
gpio_txnrx,
|
||||
gpio_enable,
|
||||
gpio_resetb,
|
||||
gpio_sync,
|
||||
gpio_en_agc,
|
||||
gpio_ctl,
|
||||
gpio_status,
|
||||
|
||||
spi_csn,
|
||||
spi_clk,
|
||||
spi_mosi,
|
||||
spi_miso,
|
||||
|
||||
spi_udc_csn_tx,
|
||||
spi_udc_csn_rx,
|
||||
spi_udc_sclk,
|
||||
spi_udc_data);
|
||||
|
||||
inout [14:0] DDR_addr;
|
||||
inout [ 2:0] DDR_ba;
|
||||
inout DDR_cas_n;
|
||||
inout DDR_ck_n;
|
||||
inout DDR_ck_p;
|
||||
inout DDR_cke;
|
||||
inout DDR_cs_n;
|
||||
inout [ 3:0] DDR_dm;
|
||||
inout [31:0] DDR_dq;
|
||||
inout [ 3:0] DDR_dqs_n;
|
||||
inout [ 3:0] DDR_dqs_p;
|
||||
inout DDR_odt;
|
||||
inout DDR_ras_n;
|
||||
inout DDR_reset_n;
|
||||
inout DDR_we_n;
|
||||
|
||||
inout FIXED_IO_ddr_vrn;
|
||||
inout FIXED_IO_ddr_vrp;
|
||||
inout [53:0] FIXED_IO_mio;
|
||||
inout FIXED_IO_ps_clk;
|
||||
inout FIXED_IO_ps_porb;
|
||||
inout FIXED_IO_ps_srstb;
|
||||
|
||||
inout [31:0] gpio_bd;
|
||||
|
||||
output hdmi_out_clk;
|
||||
output hdmi_vsync;
|
||||
output hdmi_hsync;
|
||||
output hdmi_data_e;
|
||||
output [15:0] hdmi_data;
|
||||
|
||||
output spdif;
|
||||
|
||||
output i2s_mclk;
|
||||
output i2s_bclk;
|
||||
output i2s_lrclk;
|
||||
output i2s_sdata_out;
|
||||
input i2s_sdata_in;
|
||||
|
||||
inout iic_scl;
|
||||
inout iic_sda;
|
||||
inout [ 1:0] iic_mux_scl;
|
||||
inout [ 1:0] iic_mux_sda;
|
||||
|
||||
input otg_vbusoc;
|
||||
|
||||
input rx_clk_in_p;
|
||||
input rx_clk_in_n;
|
||||
input rx_frame_in_p;
|
||||
input rx_frame_in_n;
|
||||
input [ 5:0] rx_data_in_p;
|
||||
input [ 5:0] rx_data_in_n;
|
||||
output tx_clk_out_p;
|
||||
output tx_clk_out_n;
|
||||
output tx_frame_out_p;
|
||||
output tx_frame_out_n;
|
||||
output [ 5:0] tx_data_out_p;
|
||||
output [ 5:0] tx_data_out_n;
|
||||
|
||||
inout gpio_txnrx;
|
||||
inout gpio_enable;
|
||||
inout gpio_resetb;
|
||||
inout gpio_sync;
|
||||
inout gpio_en_agc;
|
||||
inout [ 3:0] gpio_ctl;
|
||||
inout [ 7:0] gpio_status;
|
||||
|
||||
output spi_csn;
|
||||
output spi_clk;
|
||||
output spi_mosi;
|
||||
input spi_miso;
|
||||
|
||||
output spi_udc_csn_tx;
|
||||
output spi_udc_csn_rx;
|
||||
output spi_udc_sclk;
|
||||
output spi_udc_data;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [48:0] gpio_i;
|
||||
wire [48:0] gpio_o;
|
||||
wire [48:0] gpio_t;
|
||||
wire [ 1:0] iic_mux_scl_i_s;
|
||||
wire [ 1:0] iic_mux_scl_o_s;
|
||||
wire iic_mux_scl_t_s;
|
||||
wire [ 1:0] iic_mux_sda_i_s;
|
||||
wire [ 1:0] iic_mux_sda_o_s;
|
||||
wire iic_mux_sda_t_s;
|
||||
|
||||
// instantiations
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(49)) i_iobuf_gpio (
|
||||
.dt ({gpio_t[48:0]}),
|
||||
.di ({gpio_o[48:0]}),
|
||||
.do ({gpio_i[48:0]}),
|
||||
.dio({ gpio_txnrx,
|
||||
gpio_enable,
|
||||
gpio_resetb,
|
||||
gpio_sync,
|
||||
gpio_en_agc,
|
||||
gpio_ctl,
|
||||
gpio_status,
|
||||
gpio_bd}));
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_iic_scl (
|
||||
.dt (iic_mux_scl_t_s),
|
||||
.di (iic_mux_scl_i_s),
|
||||
.do (iic_mux_scl_o_s),
|
||||
.dio(iic_mux_scl));
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_iic_sda (
|
||||
.dt (iic_mux_sda_t_s),
|
||||
.di (iic_mux_sda_i_s),
|
||||
.do (iic_mux_sda_o_s),
|
||||
.dio(iic_mux_sda));
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.DDR_addr (DDR_addr),
|
||||
.DDR_ba (DDR_ba),
|
||||
.DDR_cas_n (DDR_cas_n),
|
||||
.DDR_ck_n (DDR_ck_n),
|
||||
.DDR_ck_p (DDR_ck_p),
|
||||
.DDR_cke (DDR_cke),
|
||||
.DDR_cs_n (DDR_cs_n),
|
||||
.DDR_dm (DDR_dm),
|
||||
.DDR_dq (DDR_dq),
|
||||
.DDR_dqs_n (DDR_dqs_n),
|
||||
.DDR_dqs_p (DDR_dqs_p),
|
||||
.DDR_odt (DDR_odt),
|
||||
.DDR_ras_n (DDR_ras_n),
|
||||
.DDR_reset_n (DDR_reset_n),
|
||||
.DDR_we_n (DDR_we_n),
|
||||
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
|
||||
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
|
||||
.FIXED_IO_mio (FIXED_IO_mio),
|
||||
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
|
||||
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
|
||||
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
|
||||
.GPIO_I (gpio_i),
|
||||
.GPIO_O (gpio_o),
|
||||
.GPIO_T (gpio_t),
|
||||
.hdmi_data (hdmi_data),
|
||||
.hdmi_data_e (hdmi_data_e),
|
||||
.hdmi_hsync (hdmi_hsync),
|
||||
.hdmi_out_clk (hdmi_out_clk),
|
||||
.hdmi_vsync (hdmi_vsync),
|
||||
.i2s_bclk (i2s_bclk),
|
||||
.i2s_lrclk (i2s_lrclk),
|
||||
.i2s_mclk (i2s_mclk),
|
||||
.i2s_sdata_in (i2s_sdata_in),
|
||||
.i2s_sdata_out (i2s_sdata_out),
|
||||
.iic_fmc_scl_io (iic_scl),
|
||||
.iic_fmc_sda_io (iic_sda),
|
||||
.iic_mux_scl_I (iic_mux_scl_i_s),
|
||||
.iic_mux_scl_O (iic_mux_scl_o_s),
|
||||
.iic_mux_scl_T (iic_mux_scl_t_s),
|
||||
.iic_mux_sda_I (iic_mux_sda_i_s),
|
||||
.iic_mux_sda_O (iic_mux_sda_o_s),
|
||||
.iic_mux_sda_T (iic_mux_sda_t_s),
|
||||
.otg_vbusoc (otg_vbusoc),
|
||||
.rx_clk_in_n (rx_clk_in_n),
|
||||
.rx_clk_in_p (rx_clk_in_p),
|
||||
.rx_data_in_n (rx_data_in_n),
|
||||
.rx_data_in_p (rx_data_in_p),
|
||||
.rx_frame_in_n (rx_frame_in_n),
|
||||
.rx_frame_in_p (rx_frame_in_p),
|
||||
.spdif (spdif),
|
||||
.spi_csn_i (1'b1),
|
||||
.spi_csn_o (spi_csn),
|
||||
.spi_miso_i (spi_miso),
|
||||
.spi_mosi_i (1'b0),
|
||||
.spi_mosi_o (spi_mosi),
|
||||
.spi_sclk_i (1'b0),
|
||||
.spi_sclk_o (spi_clk),
|
||||
.tx_clk_out_n (tx_clk_out_n),
|
||||
.tx_clk_out_p (tx_clk_out_p),
|
||||
.tx_data_out_n (tx_data_out_n),
|
||||
.tx_data_out_p (tx_data_out_p),
|
||||
.tx_frame_out_n (tx_frame_out_n),
|
||||
.tx_frame_out_p (tx_frame_out_p),
|
||||
.spi_udc_clk_i (1'b0),
|
||||
.spi_udc_clk_o (spi_udc_sclk),
|
||||
.spi_udc_csn_i (1'b1),
|
||||
.spi_udc_csn_tx_o (spi_udc_csn_tx),
|
||||
.spi_udc_csn_rx_o (spi_udc_csn_rx),
|
||||
.spi_udc_mosi_i (spi_udc_data),
|
||||
.spi_udc_mosi_o (spi_udc_data),
|
||||
.spi_udc_miso_i (1'b0));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
Loading…
Reference in New Issue