diff --git a/projects/common/kc705/kc705_system_bd.tcl b/projects/common/kc705/kc705_system_bd.tcl
new file mode 100644
index 000000000..7723fb9f6
--- /dev/null
+++ b/projects/common/kc705/kc705_system_bd.tcl
@@ -0,0 +1,424 @@
+
+set sys_rst         [create_bd_port -dir I -type rst sys_rst]
+set sys_clk_p       [create_bd_port -dir I sys_clk_p]
+set sys_clk_n       [create_bd_port -dir I sys_clk_n]
+set fan_pwm         [create_bd_port -dir O fan_pwm]
+
+set ddr3_1_p        [create_bd_port -dir O -from 1 -to 0 ddr3_1_p]
+set ddr3_1_n        [create_bd_port -dir O -from 2 -to 0 ddr3_1_n]
+set ddr3            [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3]
+
+set mii             [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mii_rtl:1.0 mii]
+set mdio            [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 mdio]
+
+set gpio_sw         [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_sw]
+set gpio_led        [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_led]
+set gpio_lcd        [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_lcd]
+ 
+set iic_rstn        [create_bd_port -dir O iic_rstn]
+set iic_main        [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main]
+
+set uart_sin        [create_bd_port -dir I uart_sin]
+set uart_sout       [create_bd_port -dir O uart_sout]
+
+set hdmi_out_clk    [create_bd_port -dir O hdmi_out_clk]
+set hdmi_hsync      [create_bd_port -dir O hdmi_hsync]
+set hdmi_vsync      [create_bd_port -dir O hdmi_vsync]
+set hdmi_data_e     [create_bd_port -dir O hdmi_data_e]
+set hdmi_data       [create_bd_port -dir O -from 15 -to 0 hdmi_data]
+
+# spdif audio
+
+set spdif           [create_bd_port -dir O spdif]
+
+set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] $sys_rst
+
+# instance: microblaze - processor
+
+set microblaze_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.2 microblaze_1]
+set_property -dict [list CONFIG.C_FAULT_TOLERANT {0}] $microblaze_1
+set_property -dict [list CONFIG.C_D_AXI {1}] $microblaze_1
+set_property -dict [list CONFIG.C_D_LMB {1}] $microblaze_1
+set_property -dict [list CONFIG.C_I_LMB {1}] $microblaze_1
+set_property -dict [list CONFIG.C_DEBUG_ENABLED {1}] $microblaze_1
+set_property -dict [list CONFIG.C_USE_ICACHE {1}] $microblaze_1
+set_property -dict [list CONFIG.C_ICACHE_LINE_LEN {8}] $microblaze_1
+set_property -dict [list CONFIG.C_ICACHE_ALWAYS_USED {1}] $microblaze_1
+set_property -dict [list CONFIG.C_ICACHE_FORCE_TAG_LUTRAM {1}] $microblaze_1
+set_property -dict [list CONFIG.C_USE_DCACHE {1}] $microblaze_1
+set_property -dict [list CONFIG.C_DCACHE_LINE_LEN {8}] $microblaze_1
+set_property -dict [list CONFIG.C_DCACHE_ALWAYS_USED {1}] $microblaze_1
+set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $microblaze_1
+set_property -dict [list CONFIG.C_ICACHE_HIGHADDR {0xBFFFFFFF}] $microblaze_1
+set_property -dict [list CONFIG.C_ICACHE_BASEADDR {0x80000000}] $microblaze_1
+set_property -dict [list CONFIG.C_DCACHE_HIGHADDR {0xBFFFFFFF}] $microblaze_1
+set_property -dict [list CONFIG.C_DCACHE_BASEADDR {0x80000000}] $microblaze_1
+
+# instance: microblaze - local memory & bus
+
+set dlmb [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 dlmb]
+set ilmb [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 ilmb]
+
+set dlmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 dlmb_cntlr]
+set_property -dict [list CONFIG.C_ECC {0}] $dlmb_cntlr
+
+set ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 ilmb_cntlr]
+set_property -dict [list CONFIG.C_ECC {0}] $ilmb_cntlr
+
+set lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.1 lmb_bram]
+set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $lmb_bram
+
+# instance: microblaze- mdm
+
+set mb_debug [create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.0 mb_debug]
+set_property -dict [list CONFIG.C_USE_UART {1}] $mb_debug
+
+# instance: system reset/clocks
+
+set proc_sys_reset_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1]
+
+set proc_sys_clock_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 proc_sys_clock_1]
+set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $proc_sys_clock_1
+set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {100}] $proc_sys_clock_1
+set_property -dict [list CONFIG.PRIM_SOURCE {No_buffer}] $proc_sys_clock_1
+set_property -dict [list CONFIG.USE_RESET {false}] $proc_sys_clock_1
+
+set proc_const_vcc_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 proc_const_vcc_1]
+
+# instance: ddr (mig)
+
+set axi_ddr_cntrl_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.0 axi_ddr_cntrl_1]
+set axi_ddr_cntrl_1_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl_1]]]
+file copy -force ../../scripts/kc705_system_mig.prj "$axi_ddr_cntrl_1_dir/"
+set_property -dict [list CONFIG.XML_INPUT_FILE {kc705_system_mig.prj}] $axi_ddr_cntrl_1
+set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {Custom}] $axi_ddr_cntrl_1
+
+set ddr3_const_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 ddr3_const_0]
+set_property -dict [list CONFIG.CONST_WIDTH {3}] $ddr3_const_0
+set_property -dict [list CONFIG.CONST_VAL {0}] $ddr3_const_0
+
+set ddr3_const_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 ddr3_const_1]
+set_property -dict [list CONFIG.CONST_WIDTH {2}] $ddr3_const_1
+set_property -dict [list CONFIG.CONST_VAL {1}] $ddr3_const_1
+
+# instance: axi interconnect (lite)
+
+set axi_interconnect_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_1]
+set_property -dict [list CONFIG.NUM_MI {13}] $axi_interconnect_1
+
+# instance: axi interconnect
+
+set axi_interconnect_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_2]
+set_property -dict [list CONFIG.NUM_SI {5}] $axi_interconnect_2
+set_property -dict [list CONFIG.NUM_MI {1}] $axi_interconnect_2
+set_property -dict [list CONFIG.ENABLE_ADVANCED_OPTIONS {1}] $axi_interconnect_2
+set_property -dict [list CONFIG.XBAR_DATA_WIDTH {512}] $axi_interconnect_2
+
+# instance: default peripherals
+
+set axi_ethernetlite_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernetlite:2.0 axi_ethernetlite_1]
+set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_ethernetlite_1
+set_property -dict [list CONFIG.MII_BOARD_INTERFACE {mii}] $axi_ethernetlite_1
+set_property -dict [list CONFIG.MDIO_BOARD_INTERFACE {mdio_mdc}] $axi_ethernetlite_1
+
+set axi_iic_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_1]
+
+set axi_uart_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uart_1]
+set_property -dict [list CONFIG.C_BAUDRATE {115200}] $axi_uart_1
+
+set axi_timer_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_1]
+
+set axi_gpio_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1]
+set_property -dict [list CONFIG.C_GPIO_WIDTH {7}] $axi_gpio_1
+set_property -dict [list CONFIG.C_ALL_OUTPUTS {1}] $axi_gpio_1
+set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_1
+
+set axi_gpio_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2]
+set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_gpio_2
+set_property -dict [list CONFIG.C_GPIO_WIDTH {9}] $axi_gpio_2
+set_property -dict [list CONFIG.C_GPIO2_WIDTH {8}] $axi_gpio_2
+set_property -dict [list CONFIG.C_ALL_INPUTS {1}] $axi_gpio_2
+set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_2
+set_property -dict [list CONFIG.C_ALL_OUTPUTS_2 {1}] $axi_gpio_2
+
+# instance: interrupt
+
+set axi_intc_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_1]
+set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_intc_1
+
+set concat_intc_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 concat_intc_1]
+set_property -dict [list CONFIG.NUM_PORTS {8}] $concat_intc_1
+
+# hdmi peripherals
+
+set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
+set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
+
+set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.1 axi_hdmi_dma]
+set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma
+set_property -dict [list CONFIG.c_use_mm2s_fsync {1}] $axi_hdmi_dma
+set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
+
+# audio peripherals
+
+set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
+set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
+set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
+
+set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
+set_property -dict [list CONFIG.C_DMA_TYPE {0}] $axi_spdif_tx_core
+set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core
+set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_spdif_tx_core
+set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_spdif_tx_core
+
+set axi_spdif_tx_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_spdif_tx_dma]
+set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_spdif_tx_dma
+set_property -dict [list CONFIG.c_sg_include_stscntrl_strm {0}] $axi_spdif_tx_dma
+
+# connections
+
+connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins mb_debug/Debug_SYS_Rst]
+connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins proc_sys_reset_1/mb_debug_sys_rst]
+
+connect_bd_net -net proc_sys_reset_1_mb_reset [get_bd_pins proc_sys_reset_1/mb_reset] 
+connect_bd_net -net proc_sys_reset_1_mb_reset [get_bd_pins microblaze_1/Reset] 
+
+connect_bd_net -net proc_sys_reset_1_bus_struct_reset [get_bd_pins proc_sys_reset_1/bus_struct_reset] 
+connect_bd_net -net proc_sys_reset_1_bus_struct_reset [get_bd_pins dlmb/SYS_Rst] 
+connect_bd_net -net proc_sys_reset_1_bus_struct_reset [get_bd_pins ilmb/SYS_Rst] 
+connect_bd_net -net proc_sys_reset_1_bus_struct_reset [get_bd_pins dlmb_cntlr/LMB_Rst] 
+connect_bd_net -net proc_sys_reset_1_bus_struct_reset [get_bd_pins ilmb_cntlr/LMB_Rst] 
+
+# microblaze local memory
+
+connect_bd_intf_net -intf_net lmb_cntlr_1_dlmb [get_bd_intf_pins dlmb/LMB_Sl_0] [get_bd_intf_pins dlmb_cntlr/SLMB]
+connect_bd_intf_net -intf_net lmb_cntlr_1_ilmb [get_bd_intf_pins ilmb/LMB_Sl_0] [get_bd_intf_pins ilmb_cntlr/SLMB]
+connect_bd_intf_net -intf_net lmb_cntlr_1_dlmb_bram [get_bd_intf_pins dlmb_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTA]
+connect_bd_intf_net -intf_net lmb_cntlr_1_ilmb_bram [get_bd_intf_pins ilmb_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTB]
+connect_bd_intf_net -intf_net microblaze_1_dlmb [get_bd_intf_pins microblaze_1/DLMB] [get_bd_intf_pins dlmb/LMB_M]
+connect_bd_intf_net -intf_net microblaze_1_ilmb [get_bd_intf_pins microblaze_1/ILMB] [get_bd_intf_pins ilmb/LMB_M]
+
+# microblaze debug & interrupt
+
+connect_bd_intf_net -intf_net microblaze_1_debug [get_bd_intf_pins mb_debug/MBDEBUG_0] [get_bd_intf_pins microblaze_1/DEBUG]
+connect_bd_net -net concat_intc_1_intr [get_bd_pins concat_intc_1/dout] [get_bd_pins axi_intc_1/intr]
+connect_bd_intf_net -intf_net microblaze_1_interrupt [get_bd_intf_pins axi_intc_1/interrupt] [get_bd_intf_pins microblaze_1/INTERRUPT]
+
+# defaults (peripherals)
+
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins proc_sys_reset_1/peripheral_aresetn] 
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins mb_debug/S_AXI_ARESETN] 
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_ddr_cntrl_1/aresetn] 
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_ethernetlite_1/s_axi_aresetn] 
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_uart_1/s_axi_aresetn] 
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_timer_1/s_axi_aresetn] 
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_intc_1/s_axi_aresetn] 
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_gpio_1/s_axi_aresetn] 
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_gpio_2/s_axi_aresetn] 
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_iic_1/s_axi_aresetn] 
+
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins proc_sys_clock_1/clk_out1] [get_bd_pins axi_interconnect_1/ACLK] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins proc_sys_reset_1/slowest_sync_clk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins microblaze_1/Clk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins mb_debug/S_AXI_ACLK] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins dlmb/LMB_Clk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins ilmb/LMB_Clk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins dlmb_cntlr/LMB_Clk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins ilmb_cntlr/LMB_Clk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_ethernetlite_1/s_axi_aclk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_uart_1/s_axi_aclk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_timer_1/s_axi_aclk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_intc_1/s_axi_aclk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_gpio_1/s_axi_aclk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_gpio_2/s_axi_aclk]
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_iic_1/s_axi_aclk] 
+
+connect_bd_net -net axi_ddr_cntrl_1_200mhz [get_bd_pins axi_ddr_cntrl_1/ui_clk] [get_bd_pins axi_interconnect_2/ACLK] 
+connect_bd_net -net axi_ddr_cntrl_1_200mhz [get_bd_pins proc_sys_clock_1/clk_in1] 
+
+# defaults (interconnect - processor)
+
+connect_bd_intf_net -intf_net axi_interconnect_1_s00 [get_bd_intf_pins axi_interconnect_1/S00_AXI] [get_bd_intf_pins microblaze_1/M_AXI_DP]
+connect_bd_intf_net -intf_net axi_interconnect_1_m00 [get_bd_intf_pins axi_interconnect_1/M00_AXI] [get_bd_intf_pins mb_debug/S_AXI]
+connect_bd_intf_net -intf_net axi_interconnect_1_m01 [get_bd_intf_pins axi_interconnect_1/M01_AXI] [get_bd_intf_pins axi_ethernetlite_1/s_axi]
+connect_bd_intf_net -intf_net axi_interconnect_1_m02 [get_bd_intf_pins axi_interconnect_1/M02_AXI] [get_bd_intf_pins axi_uart_1/s_axi]
+connect_bd_intf_net -intf_net axi_interconnect_1_m03 [get_bd_intf_pins axi_interconnect_1/M03_AXI] [get_bd_intf_pins axi_timer_1/s_axi]
+connect_bd_intf_net -intf_net axi_interconnect_1_m04 [get_bd_intf_pins axi_interconnect_1/M04_AXI] [get_bd_intf_pins axi_intc_1/s_axi]
+connect_bd_intf_net -intf_net axi_interconnect_1_m05 [get_bd_intf_pins axi_interconnect_1/M05_AXI] [get_bd_intf_pins axi_gpio_1/s_axi]
+connect_bd_intf_net -intf_net axi_interconnect_1_m06 [get_bd_intf_pins axi_interconnect_1/M06_AXI] [get_bd_intf_pins axi_gpio_2/s_axi]
+connect_bd_intf_net -intf_net axi_interconnect_1_m07 [get_bd_intf_pins axi_interconnect_1/M07_AXI] [get_bd_intf_pins axi_iic_1/s_axi]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/S00_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M00_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M01_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M02_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M03_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M04_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M05_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M06_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M07_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/S00_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M00_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M01_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M02_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M03_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M04_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M05_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M06_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M07_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+
+# defaults (interconnect - memory)
+
+connect_bd_intf_net -intf_net axi_interconnect_2_m00 [get_bd_intf_pins axi_interconnect_2/M00_AXI] [get_bd_intf_pins axi_ddr_cntrl_1/S_AXI]
+connect_bd_intf_net -intf_net axi_interconnect_2_s00 [get_bd_intf_pins axi_interconnect_2/S00_AXI] [get_bd_intf_pins microblaze_1/M_AXI_DC]
+connect_bd_intf_net -intf_net axi_interconnect_2_s01 [get_bd_intf_pins axi_interconnect_2/S01_AXI] [get_bd_intf_pins microblaze_1/M_AXI_IC]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/M00_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S00_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S01_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net axi_ddr_cntrl_1_200mhz [get_bd_pins axi_interconnect_2/M00_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_2/S00_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_2/S01_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+
+# defaults (interrupts)
+
+connect_bd_net -net concat_intc_1_intr_00 [get_bd_pins concat_intc_1/In0] [get_bd_pins axi_timer_1/interrupt]
+connect_bd_net -net concat_intc_1_intr_01 [get_bd_pins concat_intc_1/In1] [get_bd_pins axi_ethernetlite_1/ip2intc_irpt]
+connect_bd_net -net concat_intc_1_intr_02 [get_bd_pins concat_intc_1/In2] [get_bd_pins axi_uart_1/interrupt]
+connect_bd_net -net concat_intc_1_intr_03 [get_bd_pins concat_intc_1/In3] [get_bd_pins axi_gpio_1/ip2intc_irpt]
+connect_bd_net -net concat_intc_1_intr_04 [get_bd_pins concat_intc_1/In4] [get_bd_pins axi_gpio_2/ip2intc_irpt]
+connect_bd_net -net concat_intc_1_intr_05 [get_bd_pins concat_intc_1/In5] [get_bd_pins axi_iic_1/iic2intc_irpt]
+
+# defaults (external interface)
+
+connect_bd_net -net fan_pwm_s [get_bd_ports fan_pwm] [get_bd_pins proc_const_vcc_1/const]
+connect_bd_net -net sys_rst_s [get_bd_ports sys_rst] 
+connect_bd_net -net sys_rst_s [get_bd_pins proc_sys_reset_1/ext_reset_in]
+connect_bd_net -net sys_rst_s [get_bd_pins axi_ddr_cntrl_1/sys_rst]
+
+connect_bd_net -net sys_clk_p_s [get_bd_ports sys_clk_p] [get_bd_pins axi_ddr_cntrl_1/sys_clk_p]
+connect_bd_net -net sys_clk_n_s [get_bd_ports sys_clk_n] [get_bd_pins axi_ddr_cntrl_1/sys_clk_n]
+
+connect_bd_net -net ddr3_const_0_const [get_bd_ports ddr3_1_n] [get_bd_pins ddr3_const_0/const]
+connect_bd_net -net ddr3_const_1_const [get_bd_ports ddr3_1_p] [get_bd_pins ddr3_const_1/const]
+connect_bd_intf_net -intf_net axi_ddr_cntrl_1_ddr3 [get_bd_intf_ports ddr3] [get_bd_intf_pins axi_ddr_cntrl_1/DDR3]
+connect_bd_intf_net -intf_net axi_ethernetlite_1_mii [get_bd_intf_ports mii] [get_bd_intf_pins axi_ethernetlite_1/mii]
+connect_bd_intf_net -intf_net axi_ethernetlite_1_mdio [get_bd_intf_ports mdio] [get_bd_intf_pins axi_ethernetlite_1/mdio]
+
+connect_bd_net -net axi_uart_1_sin [get_bd_ports uart_sin] [get_bd_pins axi_uart_1/rx]
+connect_bd_net -net axi_uart_1_sout [get_bd_ports uart_sout] [get_bd_pins axi_uart_1/tx]
+
+connect_bd_intf_net -intf_net axi_gpio_1_gpio [get_bd_intf_ports gpio_lcd] [get_bd_intf_pins axi_gpio_1/gpio]
+connect_bd_intf_net -intf_net axi_gpio_2_gpio [get_bd_intf_ports gpio_sw] [get_bd_intf_pins axi_gpio_2/gpio]
+connect_bd_intf_net -intf_net axi_gpio_2_gpio2 [get_bd_intf_ports gpio_led] [get_bd_intf_pins axi_gpio_2/gpio2]
+
+connect_bd_net -net axi_iic_1_rstn [get_bd_ports iic_rstn] [get_bd_pins axi_iic_1/gpo]
+connect_bd_intf_net -intf_net axi_iic_1_iic [get_bd_intf_ports iic_main] [get_bd_intf_pins axi_iic_1/iic]
+
+# hdmi peripherals
+
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_hdmi_clkgen/s_axi_aresetn]
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_hdmi_dma/axi_resetn]
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_hdmi_core/s_axi_aresetn]
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_clkgen/s_axi_aclk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_clkgen/drp_clk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_dma/s_axi_lite_aclk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_dma/m_axi_mm2s_aclk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_dma/m_axis_mm2s_aclk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_core/s_axi_aclk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_core/m_axis_mm2s_clk] 
+connect_bd_net -net axi_ddr_cntrl_1_200mhz [get_bd_pins axi_hdmi_clkgen/clk] 
+
+connect_bd_intf_net -intf_net axi_interconnect_1_m08 [get_bd_intf_pins axi_interconnect_1/M08_AXI] [get_bd_intf_pins axi_hdmi_clkgen/s_axi]
+connect_bd_intf_net -intf_net axi_interconnect_1_m09 [get_bd_intf_pins axi_interconnect_1/M09_AXI] [get_bd_intf_pins axi_hdmi_dma/S_AXI_LITE]
+connect_bd_intf_net -intf_net axi_interconnect_1_m10 [get_bd_intf_pins axi_interconnect_1/M10_AXI] [get_bd_intf_pins axi_hdmi_core/s_axi]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M08_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M09_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M10_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M08_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M09_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M10_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+
+connect_bd_intf_net -intf_net axi_interconnect_2_s02 [get_bd_intf_pins axi_interconnect_2/S02_AXI] [get_bd_intf_pins axi_hdmi_dma/M_AXI_MM2S]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S02_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_2/S02_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+
+connect_bd_net -net concat_intc_1_intr_06 [get_bd_pins concat_intc_1/In6] [get_bd_pins axi_hdmi_dma/mm2s_introut]
+
+connect_bd_net -net axi_hdmi_core_hdmi_out_clk  [get_bd_ports hdmi_out_clk] [get_bd_pins axi_hdmi_core/hdmi_out_clk]
+connect_bd_net -net axi_hdmi_core_hdmi_hsync    [get_bd_ports hdmi_hsync]   [get_bd_pins axi_hdmi_core/hdmi_16_hsync]
+connect_bd_net -net axi_hdmi_core_hdmi_vsync    [get_bd_ports hdmi_vsync]   [get_bd_pins axi_hdmi_core/hdmi_16_vsync]
+connect_bd_net -net axi_hdmi_core_hdmi_data_e   [get_bd_ports hdmi_data_e]  [get_bd_pins axi_hdmi_core/hdmi_16_data_e]
+connect_bd_net -net axi_hdmi_core_hdmi_data     [get_bd_ports hdmi_data]    [get_bd_pins axi_hdmi_core/hdmi_16_data]
+
+connect_bd_net -net axi_hdmi_clkgen_clk [get_bd_pins axi_hdmi_clkgen/clk_0]           [get_bd_pins axi_hdmi_core/hdmi_clk]
+connect_bd_net -net axi_hdmi_core_valid [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tvalid] [get_bd_pins axi_hdmi_core/m_axis_mm2s_tvalid]
+connect_bd_net -net axi_hdmi_core_data  [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tdata]  [get_bd_pins axi_hdmi_core/m_axis_mm2s_tdata]
+connect_bd_net -net axi_hdmi_core_keep  [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tkeep]  [get_bd_pins axi_hdmi_core/m_axis_mm2s_tkeep]
+connect_bd_net -net axi_hdmi_core_last  [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tlast]  [get_bd_pins axi_hdmi_core/m_axis_mm2s_tlast]
+connect_bd_net -net axi_hdmi_core_ready [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tready] [get_bd_pins axi_hdmi_core/m_axis_mm2s_tready]
+connect_bd_net -net axi_hdmi_core_fsync [get_bd_pins axi_hdmi_dma/mm2s_fsync]         [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync]
+connect_bd_net -net axi_hdmi_core_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync_ret]
+
+# spdif audio
+
+connect_bd_intf_net -intf_net axi_interconnect_1_m11 [get_bd_intf_pins axi_interconnect_1/M11_AXI] [get_bd_intf_pins axi_spdif_tx_core/s_axi]
+connect_bd_intf_net -intf_net axi_interconnect_1_m12 [get_bd_intf_pins axi_interconnect_1/M12_AXI] [get_bd_intf_pins axi_spdif_tx_dma/S_AXI_LITE]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M11_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M12_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_spdif_tx_core/S_AXI_ARESETN]
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_spdif_tx_core/S_AXIS_ARESETN]
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_spdif_tx_dma/axi_resetn]
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M11_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M12_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_spdif_tx_core/S_AXI_ACLK]
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_spdif_tx_dma/s_axi_lite_aclk] 
+
+connect_bd_intf_net -intf_net axi_interconnect_2_s03 [get_bd_intf_pins axi_interconnect_2/S03_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_SG]
+connect_bd_intf_net -intf_net axi_interconnect_2_s04 [get_bd_intf_pins axi_interconnect_2/S04_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_MM2S]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S03_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S04_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_2/S03_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_2/S04_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_spdif_tx_core/S_AXIS_ACLK]
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_spdif_tx_dma/m_axi_mm2s_aclk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_spdif_tx_dma/m_axi_sg_aclk] 
+
+connect_bd_intf_net -intf_net axi_spdif_tx_dma_m_axis_mm2s [get_bd_intf_pins axi_spdif_tx_core/S_AXIS] [get_bd_intf_pins axi_spdif_tx_dma/M_AXIS_MM2S]
+
+connect_bd_net -net concat_intc_1_intr_07 [get_bd_pins concat_intc_1/In7] [get_bd_pins axi_spdif_tx_dma/mm2s_introut]
+
+connect_bd_net -net axi_ddr_cntrl_1_200mhz [get_bd_pins sys_audio_clkgen/clk_in1]
+connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk]
+connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o]
+
+# address mapping
+
+create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs dlmb_cntlr/SLMB/Mem]              SEG_data_dlmb_cntlr
+create_bd_addr_seg -range 0x00001000 -offset 0x41400000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs mb_debug/S_AXI/Reg]               SEG_data_mb_debug
+create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr]   SEG_data_ddr_cntrl_1
+create_bd_addr_seg -range 0x00002000 -offset 0x40E00000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs axi_ethernetlite_1/s_axi/Reg]     SEG_data_ethernetlite_1
+create_bd_addr_seg -range 0x00010000 -offset 0x40010000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs axi_gpio_1/s_axi/Reg]             SEG_data_gpio_1
+create_bd_addr_seg -range 0x00010000 -offset 0x40020000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs axi_gpio_2/s_axi/Reg]             SEG_data_gpio_2
+create_bd_addr_seg -range 0x00010000 -offset 0x41600000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs axi_iic_1/s_axi/Reg]              SEG_data_iic_1
+create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs axi_intc_1/s_axi/Reg]             SEG_data_intc_1
+create_bd_addr_seg -range 0x00010000 -offset 0x41C00000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs axi_timer_1/s_axi/Reg]            SEG_data_timer_1
+create_bd_addr_seg -range 0x00010000 -offset 0x40600000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs axi_uart_1/s_axi/Reg]             SEG_data_uart_1
+
+create_bd_addr_seg -range 0x00010000 -offset 0x79000000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite]   SEG_data_hdmi_clkgen
+create_bd_addr_seg -range 0x00010000 -offset 0x43000000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg]      SEG_data_hdmi_dma
+create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite]     SEG_data_hdmi_core
+
+create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0]     SEG_data_spdif_tx_core
+create_bd_addr_seg -range 0x00010000 -offset 0x41E00000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs axi_spdif_tx_dma/S_AXI_LITE/Reg]  SEG_data_spdif_tx_dma
+
+create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces microblaze_1/Instruction]   [get_bd_addr_segs ilmb_cntlr/SLMB/Mem]              SEG_instr_ilmb_cntlr
+create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_1/Instruction]   [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr]   SEG_instr_ddr_cntrl_1
+
+create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S]     [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr]   SEG_mem_ddr_cntrl_1
+create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_SG]   [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr]   SEG_axi_ddr_cntrl_1
+create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr]   SEG_axi_ddr_cntrl_1
+
+
diff --git a/projects/common/kc705/kc705_system_constr.xdc b/projects/common/kc705/kc705_system_constr.xdc
new file mode 100644
index 000000000..364819928
--- /dev/null
+++ b/projects/common/kc705/kc705_system_constr.xdc
@@ -0,0 +1,138 @@
+
+# constraints
+
+set_property -dict  {PACKAGE_PIN  AB7   IOSTANDARD  LVCMOS15} [get_ports sys_rst]
+
+# clocks
+
+set_property -dict  {PACKAGE_PIN  AD12  IOSTANDARD  DIFF_SSTL15} [get_ports sys_clk_p]
+set_property -dict  {PACKAGE_PIN  AD11  IOSTANDARD  DIFF_SSTL15} [get_ports sys_clk_n]
+
+create_clock -name sys_clk      -period  5.00 [get_ports sys_clk_p]
+
+# ddr
+
+set_property -dict  {PACKAGE_PIN  AF11  IOSTANDARD SSTL15} [get_ports {ddr3_1_p[0]}]
+set_property -dict  {PACKAGE_PIN  AE8   IOSTANDARD SSTL15} [get_ports {ddr3_1_p[1]}]
+set_property -dict  {PACKAGE_PIN  AE11  IOSTANDARD SSTL15} [get_ports {ddr3_1_n[0]}]
+set_property -dict  {PACKAGE_PIN  AE10  IOSTANDARD SSTL15} [get_ports {ddr3_1_n[1]}]
+set_property -dict  {PACKAGE_PIN  AC10  IOSTANDARD SSTL15} [get_ports {ddr3_1_n[2]}]
+
+set_property slave_banks {32 34} [get_iobanks 33]
+
+# ethernet
+
+set_property -dict  {PACKAGE_PIN  L20   IOSTANDARD  LVCMOS25} [get_ports mii_rst_n]
+set_property -dict  {PACKAGE_PIN  W19   IOSTANDARD  LVCMOS25} [get_ports mii_col]
+set_property -dict  {PACKAGE_PIN  R30   IOSTANDARD  LVCMOS25} [get_ports mii_crs]
+set_property -dict  {PACKAGE_PIN  R23   IOSTANDARD  LVCMOS25} [get_ports mdio_mdc]
+set_property -dict  {PACKAGE_PIN  J21   IOSTANDARD  LVCMOS25} [get_ports mdio_mdio_io]
+set_property -dict  {PACKAGE_PIN  U27   IOSTANDARD  LVCMOS25} [get_ports mii_rx_clk]
+set_property -dict  {PACKAGE_PIN  R28   IOSTANDARD  LVCMOS25} [get_ports mii_rx_dv]
+set_property -dict  {PACKAGE_PIN  V26   IOSTANDARD  LVCMOS25} [get_ports mii_rx_er]
+set_property -dict  {PACKAGE_PIN  U30   IOSTANDARD  LVCMOS25} [get_ports mii_rxd[0]]
+set_property -dict  {PACKAGE_PIN  U25   IOSTANDARD  LVCMOS25} [get_ports mii_rxd[1]]
+set_property -dict  {PACKAGE_PIN  T25   IOSTANDARD  LVCMOS25} [get_ports mii_rxd[2]]
+set_property -dict  {PACKAGE_PIN  U28   IOSTANDARD  LVCMOS25} [get_ports mii_rxd[3]]
+set_property -dict  {PACKAGE_PIN  M28   IOSTANDARD  LVCMOS25} [get_ports mii_tx_clk]
+set_property -dict  {PACKAGE_PIN  M27   IOSTANDARD  LVCMOS25} [get_ports mii_tx_en]
+set_property -dict  {PACKAGE_PIN  N27   IOSTANDARD  LVCMOS25} [get_ports mii_txd[0]]
+set_property -dict  {PACKAGE_PIN  N25   IOSTANDARD  LVCMOS25} [get_ports mii_txd[1]]
+set_property -dict  {PACKAGE_PIN  M29   IOSTANDARD  LVCMOS25} [get_ports mii_txd[2]]
+set_property -dict  {PACKAGE_PIN  L28   IOSTANDARD  LVCMOS25} [get_ports mii_txd[3]]
+
+set_false_path -through [get_ports mii_rst_n]
+set_property SLEW FAST [get_ports mii_txd*]
+set_property SLEW FAST [get_ports mii_tx_en]
+
+create_clock -add -name phy_rx_clk -period 8.000 [get_nets mii_rx_clk]
+create_clock -period 40.000 -name phy_tx_clk [get_ports mii_tx_clk]
+
+set_false_path -from [get_clocks phy_rx_clk] -to [get_clocks *]
+set_false_path -from [get_clocks phy_tx_clk] -to [get_clocks *]
+set_false_path -from [get_clocks *] -to [get_clocks phy_rx_clk]
+set_false_path -from [get_clocks *] -to [get_clocks phy_tx_clk]
+
+# uart
+
+set_property -dict  {PACKAGE_PIN  M19   IOSTANDARD  LVCMOS25} [get_ports uart_sin]
+set_property -dict  {PACKAGE_PIN  K24   IOSTANDARD  LVCMOS25} [get_ports uart_sout]
+
+# fan
+
+set_property -dict  {PACKAGE_PIN  L26   IOSTANDARD  LVCMOS25} [get_ports fan_pwm]
+
+# lcd
+
+set_property -dict  {PACKAGE_PIN  AB10  IOSTANDARD  LVCMOS15} [get_ports gpio_lcd[6]]
+set_property -dict  {PACKAGE_PIN  Y11   IOSTANDARD  LVCMOS15} [get_ports gpio_lcd[5]]
+set_property -dict  {PACKAGE_PIN  AB13  IOSTANDARD  LVCMOS15} [get_ports gpio_lcd[4]]
+set_property -dict  {PACKAGE_PIN  Y10   IOSTANDARD  LVCMOS15} [get_ports gpio_lcd[3]]
+set_property -dict  {PACKAGE_PIN  AA11  IOSTANDARD  LVCMOS15} [get_ports gpio_lcd[2]]
+set_property -dict  {PACKAGE_PIN  AA10  IOSTANDARD  LVCMOS15} [get_ports gpio_lcd[1]]
+set_property -dict  {PACKAGE_PIN  AA13  IOSTANDARD  LVCMOS15} [get_ports gpio_lcd[0]]
+
+set_property -dict  {PACKAGE_PIN  Y29   IOSTANDARD  LVCMOS25} [get_ports gpio_sw[0]]
+set_property -dict  {PACKAGE_PIN  W29   IOSTANDARD  LVCMOS25} [get_ports gpio_sw[1]]
+set_property -dict  {PACKAGE_PIN  AA28  IOSTANDARD  LVCMOS25} [get_ports gpio_sw[2]]
+set_property -dict  {PACKAGE_PIN  Y28   IOSTANDARD  LVCMOS25} [get_ports gpio_sw[3]]
+set_property -dict  {PACKAGE_PIN  AA12  IOSTANDARD  LVCMOS15} [get_ports gpio_sw[4]]
+set_property -dict  {PACKAGE_PIN  AG5   IOSTANDARD  LVCMOS15} [get_ports gpio_sw[5]]
+set_property -dict  {PACKAGE_PIN  AB12  IOSTANDARD  LVCMOS15} [get_ports gpio_sw[6]]
+set_property -dict  {PACKAGE_PIN  AC6   IOSTANDARD  LVCMOS15} [get_ports gpio_sw[7]]
+set_property -dict  {PACKAGE_PIN  G12   IOSTANDARD  LVCMOS25} [get_ports gpio_sw[8]]
+
+set_property -dict  {PACKAGE_PIN  AB8   IOSTANDARD  LVCMOS15} [get_ports gpio_led[0]]
+set_property -dict  {PACKAGE_PIN  AA8   IOSTANDARD  LVCMOS15} [get_ports gpio_led[1]]
+set_property -dict  {PACKAGE_PIN  AC9   IOSTANDARD  LVCMOS15} [get_ports gpio_led[2]]
+set_property -dict  {PACKAGE_PIN  AB9   IOSTANDARD  LVCMOS15} [get_ports gpio_led[3]]
+set_property -dict  {PACKAGE_PIN  AE26  IOSTANDARD  LVCMOS25} [get_ports gpio_led[4]]
+set_property -dict  {PACKAGE_PIN  G19   IOSTANDARD  LVCMOS25} [get_ports gpio_led[5]]
+set_property -dict  {PACKAGE_PIN  E18   IOSTANDARD  LVCMOS25} [get_ports gpio_led[6]]
+set_property -dict  {PACKAGE_PIN  F16   IOSTANDARD  LVCMOS25} [get_ports gpio_led[7]]
+
+# iic
+
+set_property -dict  {PACKAGE_PIN  P23   IOSTANDARD  LVCMOS25} [get_ports iic_rstn]
+set_property -dict  {PACKAGE_PIN  K21   IOSTANDARD  LVCMOS25  DRIVE 8 SLEW SLOW} [get_ports iic_scl]
+set_property -dict  {PACKAGE_PIN  L21   IOSTANDARD  LVCMOS25  DRIVE 8 SLEW SLOW} [get_ports iic_sda]
+
+# hdmi
+
+set_property -dict  {PACKAGE_PIN  K18   IOSTANDARD  LVCMOS25} [get_ports hdmi_out_clk]
+set_property -dict  {PACKAGE_PIN  J18   IOSTANDARD  LVCMOS25} [get_ports hdmi_hsync]
+set_property -dict  {PACKAGE_PIN  H20   IOSTANDARD  LVCMOS25} [get_ports hdmi_vsync]
+set_property -dict  {PACKAGE_PIN  H17   IOSTANDARD  LVCMOS25} [get_ports hdmi_data_e]
+set_property -dict  {PACKAGE_PIN  B23   IOSTANDARD  LVCMOS25} [get_ports hdmi_data[0]]
+set_property -dict  {PACKAGE_PIN  A23   IOSTANDARD  LVCMOS25} [get_ports hdmi_data[1]]
+set_property -dict  {PACKAGE_PIN  E23   IOSTANDARD  LVCMOS25} [get_ports hdmi_data[2]]
+set_property -dict  {PACKAGE_PIN  D23   IOSTANDARD  LVCMOS25} [get_ports hdmi_data[3]]
+set_property -dict  {PACKAGE_PIN  F25   IOSTANDARD  LVCMOS25} [get_ports hdmi_data[4]]
+set_property -dict  {PACKAGE_PIN  E25   IOSTANDARD  LVCMOS25} [get_ports hdmi_data[5]]
+set_property -dict  {PACKAGE_PIN  E24   IOSTANDARD  LVCMOS25} [get_ports hdmi_data[6]]
+set_property -dict  {PACKAGE_PIN  D24   IOSTANDARD  LVCMOS25} [get_ports hdmi_data[7]]
+set_property -dict  {PACKAGE_PIN  F26   IOSTANDARD  LVCMOS25} [get_ports hdmi_data[8]]
+set_property -dict  {PACKAGE_PIN  E26   IOSTANDARD  LVCMOS25} [get_ports hdmi_data[9]]
+set_property -dict  {PACKAGE_PIN  G23   IOSTANDARD  LVCMOS25} [get_ports hdmi_data[10]]
+set_property -dict  {PACKAGE_PIN  G24   IOSTANDARD  LVCMOS25} [get_ports hdmi_data[11]]
+set_property -dict  {PACKAGE_PIN  J19   IOSTANDARD  LVCMOS25} [get_ports hdmi_data[12]]
+set_property -dict  {PACKAGE_PIN  H19   IOSTANDARD  LVCMOS25} [get_ports hdmi_data[13]]
+set_property -dict  {PACKAGE_PIN  L17   IOSTANDARD  LVCMOS25} [get_ports hdmi_data[14]]
+set_property -dict  {PACKAGE_PIN  L18   IOSTANDARD  LVCMOS25} [get_ports hdmi_data[15]]
+
+# spdif
+
+set_property -dict  {PACKAGE_PIN  J17   IOSTANDARD  LVCMOS25} [get_ports spdif]
+
+# clocks
+
+create_clock -name cpu_clk      -period 10.00 [get_nets i_system_wrapper/system_i/proc_sys_clk_1_100mhz]
+create_clock -name m200_clk     -period  5.00 [get_nets i_system_wrapper/system_i/axi_ddr_cntrl_1_200mhz]
+create_clock -name hdmi_clk     -period  6.73 [get_nets i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s]
+create_clock -name spdif_clk    -period 50.00 [get_nets i_system_wrapper/system_i/sys_audio_clkgen_clk]
+
+set_clock_groups -asynchronous -group {cpu_clk}
+set_clock_groups -asynchronous -group {m200_clk}
+set_clock_groups -asynchronous -group {hdmi_clk}
+set_clock_groups -asynchronous -group {spdif_clk}
+
diff --git a/projects/common/kc705/kc705_system_mig.prj b/projects/common/kc705/kc705_system_mig.prj
new file mode 100644
index 000000000..00eec9cc6
--- /dev/null
+++ b/projects/common/kc705/kc705_system_mig.prj
@@ -0,0 +1,201 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
+<Project NoOfControllers="1" >
+    <ModuleName>system_axi_ddr_cntrl_1_0</ModuleName>
+    <dci_inouts_inputs>1</dci_inouts_inputs>
+    <dci_inputs>1</dci_inputs>
+    <Debug_En>OFF</Debug_En>
+    <DataDepth_En>1024</DataDepth_En>
+    <LowPower_En>ON</LowPower_En>
+    <XADC_En>Disabled</XADC_En>
+    <TargetFPGA>xc7k325t-ffg900/-2</TargetFPGA>
+    <Version>2.0</Version>
+    <SystemClock>Differential</SystemClock>
+    <ReferenceClock>Use System Clock</ReferenceClock>
+    <SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
+    <BankSelectionFlag>FALSE</BankSelectionFlag>
+    <InternalVref>0</InternalVref>
+    <dci_hr_inouts_inputs>40 Ohms</dci_hr_inouts_inputs>
+    <dci_cascade>1</dci_cascade>
+    <Controller number="0" >
+        <MemoryDevice>DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6</MemoryDevice>
+        <TimePeriod>1250</TimePeriod>
+        <VccAuxIO>2.0V</VccAuxIO>
+        <PHYRatio>4:1</PHYRatio>
+        <InputClkFreq>200</InputClkFreq>
+        <UIExtraClocks>1</UIExtraClocks>
+        <MMCMClkOut0> 8.000</MMCMClkOut0>
+        <MMCMClkOut1>1</MMCMClkOut1>
+        <MMCMClkOut2>1</MMCMClkOut2>
+        <MMCMClkOut3>1</MMCMClkOut3>
+        <MMCMClkOut4>1</MMCMClkOut4>
+        <DataWidth>64</DataWidth>
+        <DeepMemory>1</DeepMemory>
+        <DataMask>1</DataMask>
+        <ECC>Disabled</ECC>
+        <Ordering>Normal</Ordering>
+        <CustomPart>FALSE</CustomPart>
+        <NewPartName></NewPartName>
+        <RowAddress>14</RowAddress>
+        <ColAddress>10</ColAddress>
+        <BankAddress>3</BankAddress>
+        <MemoryVoltage>1.5V</MemoryVoltage>
+        <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
+        <PinSelection>
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH12" SLEW="FAST" name="ddr3_addr[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF13" SLEW="FAST" name="ddr3_addr[10]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE13" SLEW="FAST" name="ddr3_addr[11]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ11" SLEW="FAST" name="ddr3_addr[12]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH11" SLEW="FAST" name="ddr3_addr[13]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AG13" SLEW="FAST" name="ddr3_addr[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AG12" SLEW="FAST" name="ddr3_addr[2]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF12" SLEW="FAST" name="ddr3_addr[3]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ12" SLEW="FAST" name="ddr3_addr[4]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ13" SLEW="FAST" name="ddr3_addr[5]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ14" SLEW="FAST" name="ddr3_addr[6]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH14" SLEW="FAST" name="ddr3_addr[7]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AK13" SLEW="FAST" name="ddr3_addr[8]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AK14" SLEW="FAST" name="ddr3_addr[9]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH9" SLEW="FAST" name="ddr3_ba[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AG9" SLEW="FAST" name="ddr3_ba[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AK9" SLEW="FAST" name="ddr3_ba[2]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC11" SLEW="FAST" name="ddr3_cas_n" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="AH10" SLEW="FAST" name="ddr3_ck_n[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="AG10" SLEW="FAST" name="ddr3_ck_p[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF10" SLEW="FAST" name="ddr3_cke[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC12" SLEW="FAST" name="ddr3_cs_n[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="Y16" SLEW="FAST" name="ddr3_dm[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AB17" SLEW="FAST" name="ddr3_dm[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF17" SLEW="FAST" name="ddr3_dm[2]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE16" SLEW="FAST" name="ddr3_dm[3]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AK5" SLEW="FAST" name="ddr3_dm[4]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ3" SLEW="FAST" name="ddr3_dm[5]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF6" SLEW="FAST" name="ddr3_dm[6]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC7" SLEW="FAST" name="ddr3_dm[7]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AA15" SLEW="FAST" name="ddr3_dq[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC19" SLEW="FAST" name="ddr3_dq[10]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD17" SLEW="FAST" name="ddr3_dq[11]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AA18" SLEW="FAST" name="ddr3_dq[12]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AB18" SLEW="FAST" name="ddr3_dq[13]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE18" SLEW="FAST" name="ddr3_dq[14]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD18" SLEW="FAST" name="ddr3_dq[15]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG19" SLEW="FAST" name="ddr3_dq[16]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK19" SLEW="FAST" name="ddr3_dq[17]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG18" SLEW="FAST" name="ddr3_dq[18]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF18" SLEW="FAST" name="ddr3_dq[19]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AA16" SLEW="FAST" name="ddr3_dq[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH19" SLEW="FAST" name="ddr3_dq[20]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ19" SLEW="FAST" name="ddr3_dq[21]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE19" SLEW="FAST" name="ddr3_dq[22]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD19" SLEW="FAST" name="ddr3_dq[23]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK16" SLEW="FAST" name="ddr3_dq[24]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ17" SLEW="FAST" name="ddr3_dq[25]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG15" SLEW="FAST" name="ddr3_dq[26]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF15" SLEW="FAST" name="ddr3_dq[27]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH17" SLEW="FAST" name="ddr3_dq[28]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG14" SLEW="FAST" name="ddr3_dq[29]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC14" SLEW="FAST" name="ddr3_dq[2]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH15" SLEW="FAST" name="ddr3_dq[30]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK15" SLEW="FAST" name="ddr3_dq[31]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK8" SLEW="FAST" name="ddr3_dq[32]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK6" SLEW="FAST" name="ddr3_dq[33]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG7" SLEW="FAST" name="ddr3_dq[34]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF7" SLEW="FAST" name="ddr3_dq[35]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF8" SLEW="FAST" name="ddr3_dq[36]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK4" SLEW="FAST" name="ddr3_dq[37]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ8" SLEW="FAST" name="ddr3_dq[38]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ6" SLEW="FAST" name="ddr3_dq[39]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD14" SLEW="FAST" name="ddr3_dq[3]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH5" SLEW="FAST" name="ddr3_dq[40]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH6" SLEW="FAST" name="ddr3_dq[41]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ2" SLEW="FAST" name="ddr3_dq[42]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH2" SLEW="FAST" name="ddr3_dq[43]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH4" SLEW="FAST" name="ddr3_dq[44]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ4" SLEW="FAST" name="ddr3_dq[45]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK1" SLEW="FAST" name="ddr3_dq[46]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ1" SLEW="FAST" name="ddr3_dq[47]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF1" SLEW="FAST" name="ddr3_dq[48]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF2" SLEW="FAST" name="ddr3_dq[49]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AA17" SLEW="FAST" name="ddr3_dq[4]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE4" SLEW="FAST" name="ddr3_dq[50]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE3" SLEW="FAST" name="ddr3_dq[51]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF3" SLEW="FAST" name="ddr3_dq[52]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF5" SLEW="FAST" name="ddr3_dq[53]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE1" SLEW="FAST" name="ddr3_dq[54]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE5" SLEW="FAST" name="ddr3_dq[55]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC1" SLEW="FAST" name="ddr3_dq[56]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD3" SLEW="FAST" name="ddr3_dq[57]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC4" SLEW="FAST" name="ddr3_dq[58]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC5" SLEW="FAST" name="ddr3_dq[59]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AB15" SLEW="FAST" name="ddr3_dq[5]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE6" SLEW="FAST" name="ddr3_dq[60]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD6" SLEW="FAST" name="ddr3_dq[61]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC2" SLEW="FAST" name="ddr3_dq[62]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD4" SLEW="FAST" name="ddr3_dq[63]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE15" SLEW="FAST" name="ddr3_dq[6]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="Y15" SLEW="FAST" name="ddr3_dq[7]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AB19" SLEW="FAST" name="ddr3_dq[8]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD16" SLEW="FAST" name="ddr3_dq[9]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AC15" SLEW="FAST" name="ddr3_dqs_n[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="Y18" SLEW="FAST" name="ddr3_dqs_n[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AK18" SLEW="FAST" name="ddr3_dqs_n[2]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AJ16" SLEW="FAST" name="ddr3_dqs_n[3]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AJ7" SLEW="FAST" name="ddr3_dqs_n[4]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH1" SLEW="FAST" name="ddr3_dqs_n[5]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG3" SLEW="FAST" name="ddr3_dqs_n[6]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD1" SLEW="FAST" name="ddr3_dqs_n[7]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AC16" SLEW="FAST" name="ddr3_dqs_p[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="Y19" SLEW="FAST" name="ddr3_dqs_p[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AJ18" SLEW="FAST" name="ddr3_dqs_p[2]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH16" SLEW="FAST" name="ddr3_dqs_p[3]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH7" SLEW="FAST" name="ddr3_dqs_p[4]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG2" SLEW="FAST" name="ddr3_dqs_p[5]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG4" SLEW="FAST" name="ddr3_dqs_p[6]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD2" SLEW="FAST" name="ddr3_dqs_p[7]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AD8" SLEW="FAST" name="ddr3_odt[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AD9" SLEW="FAST" name="ddr3_ras_n" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="LVCMOS15" PADName="AK3" SLEW="FAST" name="ddr3_reset_n" IN_TERM="" />
+            <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE9" SLEW="FAST" name="ddr3_we_n" IN_TERM="" />
+        </PinSelection>
+        <System_Clock>
+            <Pin PADName="AD12/AD11(CC_P/N)" Bank="33" name="sys_clk_p/n" />
+        </System_Clock>
+        <System_Control>
+            <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
+            <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
+            <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
+        </System_Control>
+        <TimingParameters>
+            <Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="30" trtp="7.5" tcke="5" trfc="110" trp="13.125" tras="35" trcd="13.125" />
+        </TimingParameters>
+        <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
+        <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
+        <mrCasLatency name="CAS Latency" >11</mrCasLatency>
+        <mrMode name="Mode" >Normal</mrMode>
+        <mrDllReset name="DLL Reset" >No</mrDllReset>
+        <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
+        <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
+        <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
+        <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
+        <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
+        <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
+        <emrPosted name="Additive Latency (AL)" >0</emrPosted>
+        <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
+        <emrDQS name="TDQS enable" >Enabled</emrDQS>
+        <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
+        <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
+        <mr2CasWriteLatency name="CAS write latency" >8</mr2CasWriteLatency>
+        <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
+        <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
+        <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
+        <PortInterface>AXI</PortInterface>
+        <AXIParameters>
+            <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
+            <C0_S_AXI_ADDR_WIDTH>32</C0_S_AXI_ADDR_WIDTH>
+            <C0_S_AXI_DATA_WIDTH>512</C0_S_AXI_DATA_WIDTH>
+            <C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
+            <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
+        </AXIParameters>
+    </Controller>
+
+</Project>
diff --git a/projects/common/vc707/vc707_system_bd.tcl b/projects/common/vc707/vc707_system_bd.tcl
new file mode 100644
index 000000000..c63e54bdf
--- /dev/null
+++ b/projects/common/vc707/vc707_system_bd.tcl
@@ -0,0 +1,464 @@
+
+set sys_rst         [create_bd_port -dir I -type rst sys_rst]
+set sys_clk_p       [create_bd_port -dir I sys_clk_p]
+set sys_clk_n       [create_bd_port -dir I sys_clk_n]
+set fan_pwm         [create_bd_port -dir O fan_pwm]
+
+set ddr3            [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3]
+
+set phy_rstn        [create_bd_port -dir O -type rst phy_rstn]
+set mgt_clk         [create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 mgt_clk]
+set sgmii           [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:sgmii_rtl:1.0 sgmii]
+set mdio            [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_io:1.0 mdio]
+
+set gpio_sw         [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_sw]
+set gpio_led        [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_led]
+set gpio_lcd        [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_lcd]
+ 
+set iic_rstn        [create_bd_port -dir O iic_rstn]
+set iic_main        [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main]
+
+set uart_sin        [create_bd_port -dir I uart_sin]
+set uart_sout       [create_bd_port -dir O uart_sout]
+
+set hdmi_out_clk    [create_bd_port -dir O hdmi_out_clk]
+set hdmi_hsync      [create_bd_port -dir O hdmi_hsync]
+set hdmi_vsync      [create_bd_port -dir O hdmi_vsync]
+set hdmi_data_e     [create_bd_port -dir O hdmi_data_e]
+set hdmi_data       [create_bd_port -dir O -from 35 -to 0 hdmi_data]
+
+# spdif audio
+
+set spdif           [create_bd_port -dir O spdif]
+
+set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] $sys_rst
+
+# instance: microblaze - processor
+
+set microblaze_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.2 microblaze_1]
+set_property -dict [list CONFIG.C_FAULT_TOLERANT {0}] $microblaze_1
+set_property -dict [list CONFIG.C_D_AXI {1}] $microblaze_1
+set_property -dict [list CONFIG.C_D_LMB {1}] $microblaze_1
+set_property -dict [list CONFIG.C_I_LMB {1}] $microblaze_1
+set_property -dict [list CONFIG.C_DEBUG_ENABLED {1}] $microblaze_1
+set_property -dict [list CONFIG.C_USE_ICACHE {1}] $microblaze_1
+set_property -dict [list CONFIG.C_ICACHE_LINE_LEN {8}] $microblaze_1
+set_property -dict [list CONFIG.C_ICACHE_ALWAYS_USED {1}] $microblaze_1
+set_property -dict [list CONFIG.C_ICACHE_FORCE_TAG_LUTRAM {1}] $microblaze_1
+set_property -dict [list CONFIG.C_USE_DCACHE {1}] $microblaze_1
+set_property -dict [list CONFIG.C_DCACHE_LINE_LEN {8}] $microblaze_1
+set_property -dict [list CONFIG.C_DCACHE_ALWAYS_USED {1}] $microblaze_1
+set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $microblaze_1
+set_property -dict [list CONFIG.C_ICACHE_HIGHADDR {0xBFFFFFFF}] $microblaze_1
+set_property -dict [list CONFIG.C_ICACHE_BASEADDR {0x80000000}] $microblaze_1
+set_property -dict [list CONFIG.C_DCACHE_HIGHADDR {0xBFFFFFFF}] $microblaze_1
+set_property -dict [list CONFIG.C_DCACHE_BASEADDR {0x80000000}] $microblaze_1
+
+# instance: microblaze - local memory & bus
+
+set dlmb [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 dlmb]
+set ilmb [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 ilmb]
+
+set dlmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 dlmb_cntlr]
+set_property -dict [list CONFIG.C_ECC {0}] $dlmb_cntlr
+
+set ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 ilmb_cntlr]
+set_property -dict [list CONFIG.C_ECC {0}] $ilmb_cntlr
+
+set lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.1 lmb_bram]
+set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $lmb_bram
+
+# instance: microblaze- mdm
+
+set mb_debug [create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.0 mb_debug]
+set_property -dict [list CONFIG.C_USE_UART {1}] $mb_debug
+
+# instance: system reset/clocks
+
+set proc_sys_reset_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1]
+
+set proc_sys_clock_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 proc_sys_clock_1]
+set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000}] $proc_sys_clock_1
+set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {100}] $proc_sys_clock_1
+set_property -dict [list CONFIG.PRIM_SOURCE {No_buffer}] $proc_sys_clock_1
+set_property -dict [list CONFIG.USE_RESET {false}] $proc_sys_clock_1
+set_property -dict [list CONFIG.CLKOUT2_USED {true}] $proc_sys_clock_1
+set_property -dict [list CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200.000}] $proc_sys_clock_1
+
+set proc_const_vcc_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 proc_const_vcc_1]
+
+# instance: ddr (mig)
+
+set axi_ddr_cntrl_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.0 axi_ddr_cntrl_1]
+set axi_ddr_cntrl_1_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl_1]]]
+file copy -force ../../scripts/vc707_system_mig.prj "$axi_ddr_cntrl_1_dir/"
+set_property -dict [list CONFIG.XML_INPUT_FILE {vc707_system_mig.prj}] $axi_ddr_cntrl_1
+set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {Custom}] $axi_ddr_cntrl_1
+
+# instance: axi interconnect (lite)
+
+set axi_interconnect_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_1]
+set_property -dict [list CONFIG.NUM_MI {14}] $axi_interconnect_1
+
+# instance: axi interconnect
+
+set axi_interconnect_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_2]
+set_property -dict [list CONFIG.NUM_SI {8}] $axi_interconnect_2
+set_property -dict [list CONFIG.NUM_MI {1}] $axi_interconnect_2
+set_property -dict [list CONFIG.ENABLE_ADVANCED_OPTIONS {1}] $axi_interconnect_2
+set_property -dict [list CONFIG.XBAR_DATA_WIDTH {512}] $axi_interconnect_2
+
+# instance: default peripherals
+
+set axi_ethernet_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:6.0 axi_ethernet_1]
+set_property -dict [list CONFIG.PHY_TYPE {SGMII}] $axi_ethernet_1
+
+set axi_ethernet_dma_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_ethernet_dma_1]
+set_property -dict [list CONFIG.c_include_mm2s_dre {1}] $axi_ethernet_dma_1
+set_property -dict [list CONFIG.c_sg_use_stsapp_length {1}] $axi_ethernet_dma_1
+set_property -dict [list CONFIG.c_include_s2mm_dre {1}] $axi_ethernet_dma_1
+
+set axi_iic_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_1]
+
+set axi_uart_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uart_1]
+set_property -dict [list CONFIG.C_BAUDRATE {115200}] $axi_uart_1
+
+set axi_timer_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_1]
+
+set axi_gpio_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1]
+set_property -dict [list CONFIG.C_GPIO_WIDTH {7}] $axi_gpio_1
+set_property -dict [list CONFIG.C_ALL_OUTPUTS {1}] $axi_gpio_1
+set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_1
+
+set axi_gpio_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2]
+set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_gpio_2
+set_property -dict [list CONFIG.C_GPIO_WIDTH {13}] $axi_gpio_2
+set_property -dict [list CONFIG.C_GPIO2_WIDTH {8}] $axi_gpio_2
+set_property -dict [list CONFIG.C_ALL_INPUTS {1}] $axi_gpio_2
+set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_2
+set_property -dict [list CONFIG.C_ALL_OUTPUTS_2 {1}] $axi_gpio_2
+
+# instance: interrupt
+
+set axi_intc_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_1]
+set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_intc_1
+
+set concat_intc_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 concat_intc_1]
+set_property -dict [list CONFIG.NUM_PORTS {10}] $concat_intc_1
+
+# hdmi peripherals
+
+set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
+set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
+
+set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.1 axi_hdmi_dma]
+set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma
+set_property -dict [list CONFIG.c_use_mm2s_fsync {1}] $axi_hdmi_dma
+set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
+
+# audio peripherals
+
+set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
+set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
+set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
+
+set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
+set_property -dict [list CONFIG.C_DMA_TYPE {0}] $axi_spdif_tx_core
+set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core
+set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_spdif_tx_core
+set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_spdif_tx_core
+
+set axi_spdif_tx_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_spdif_tx_dma]
+set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_spdif_tx_dma
+set_property -dict [list CONFIG.c_sg_include_stscntrl_strm {0}] $axi_spdif_tx_dma
+
+# connections
+
+connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins mb_debug/Debug_SYS_Rst]
+connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins proc_sys_reset_1/mb_debug_sys_rst]
+
+connect_bd_net -net proc_sys_reset_1_mb_reset [get_bd_pins proc_sys_reset_1/mb_reset] 
+connect_bd_net -net proc_sys_reset_1_mb_reset [get_bd_pins microblaze_1/Reset] 
+
+connect_bd_net -net proc_sys_reset_1_bus_struct_reset [get_bd_pins proc_sys_reset_1/bus_struct_reset] 
+connect_bd_net -net proc_sys_reset_1_bus_struct_reset [get_bd_pins dlmb/SYS_Rst] 
+connect_bd_net -net proc_sys_reset_1_bus_struct_reset [get_bd_pins ilmb/SYS_Rst] 
+connect_bd_net -net proc_sys_reset_1_bus_struct_reset [get_bd_pins dlmb_cntlr/LMB_Rst] 
+connect_bd_net -net proc_sys_reset_1_bus_struct_reset [get_bd_pins ilmb_cntlr/LMB_Rst] 
+
+# microblaze local memory
+
+connect_bd_intf_net -intf_net lmb_cntlr_1_dlmb [get_bd_intf_pins dlmb/LMB_Sl_0] [get_bd_intf_pins dlmb_cntlr/SLMB]
+connect_bd_intf_net -intf_net lmb_cntlr_1_ilmb [get_bd_intf_pins ilmb/LMB_Sl_0] [get_bd_intf_pins ilmb_cntlr/SLMB]
+connect_bd_intf_net -intf_net lmb_cntlr_1_dlmb_bram [get_bd_intf_pins dlmb_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTA]
+connect_bd_intf_net -intf_net lmb_cntlr_1_ilmb_bram [get_bd_intf_pins ilmb_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTB]
+connect_bd_intf_net -intf_net microblaze_1_dlmb [get_bd_intf_pins microblaze_1/DLMB] [get_bd_intf_pins dlmb/LMB_M]
+connect_bd_intf_net -intf_net microblaze_1_ilmb [get_bd_intf_pins microblaze_1/ILMB] [get_bd_intf_pins ilmb/LMB_M]
+
+# microblaze debug & interrupt
+
+connect_bd_intf_net -intf_net microblaze_1_debug [get_bd_intf_pins mb_debug/MBDEBUG_0] [get_bd_intf_pins microblaze_1/DEBUG]
+connect_bd_net -net concat_intc_1_intr [get_bd_pins concat_intc_1/dout] [get_bd_pins axi_intc_1/intr]
+connect_bd_intf_net -intf_net microblaze_1_interrupt [get_bd_intf_pins axi_intc_1/interrupt] [get_bd_intf_pins microblaze_1/INTERRUPT]
+
+# defaults (peripherals)
+
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins proc_sys_reset_1/peripheral_aresetn] 
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins mb_debug/S_AXI_ARESETN] 
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_ddr_cntrl_1/aresetn] 
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_ethernet_1/s_axi_lite_resetn] [get_bd_pins proc_sys_reset_1/peripheral_aresetn] 
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_uart_1/s_axi_aresetn] 
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_timer_1/s_axi_aresetn] 
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_intc_1/s_axi_aresetn] 
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_gpio_1/s_axi_aresetn] 
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_gpio_2/s_axi_aresetn] 
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_iic_1/s_axi_aresetn] 
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_ethernet_dma_1/axi_resetn] 
+
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins proc_sys_clock_1/clk_out1] [get_bd_pins axi_interconnect_1/ACLK] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins proc_sys_reset_1/slowest_sync_clk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins microblaze_1/Clk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins mb_debug/S_AXI_ACLK] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins dlmb/LMB_Clk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins ilmb/LMB_Clk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins dlmb_cntlr/LMB_Clk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins ilmb_cntlr/LMB_Clk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_ethernet_1/s_axi_lite_clk] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_uart_1/s_axi_aclk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_timer_1/s_axi_aclk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_intc_1/s_axi_aclk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_gpio_1/s_axi_aclk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_gpio_2/s_axi_aclk]
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_iic_1/s_axi_aclk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_ethernet_1/axis_clk] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_ethernet_dma_1/m_axi_sg_aclk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_ethernet_dma_1/m_axi_mm2s_aclk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_ethernet_dma_1/m_axi_s2mm_aclk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_ethernet_dma_1/s_axi_lite_aclk] 
+
+connect_bd_net -net proc_sys_clk_1_200mhz [get_bd_pins proc_sys_clock_1/clk_out2] [get_bd_pins axi_interconnect_2/ACLK] 
+
+connect_bd_net -net axi_ddr_cntrl_1_100mhz [get_bd_pins axi_ddr_cntrl_1/ui_clk] 
+connect_bd_net -net axi_ddr_cntrl_1_100mhz [get_bd_pins proc_sys_clock_1/clk_in1] 
+connect_bd_net -net axi_ddr_cntrl_1_100mhz [get_bd_pins axi_ethernet_1/ref_clk] [get_bd_pins axi_ddr_cntrl_1/ui_clk] 
+
+
+# defaults (interconnect - processor)
+
+connect_bd_intf_net -intf_net axi_interconnect_1_s00 [get_bd_intf_pins axi_interconnect_1/S00_AXI] [get_bd_intf_pins microblaze_1/M_AXI_DP]
+connect_bd_intf_net -intf_net axi_interconnect_1_m00 [get_bd_intf_pins axi_interconnect_1/M00_AXI] [get_bd_intf_pins mb_debug/S_AXI]
+connect_bd_intf_net -intf_net axi_interconnect_1_m01 [get_bd_intf_pins axi_interconnect_1/M01_AXI] [get_bd_intf_pins axi_ethernet_1/s_axi]
+connect_bd_intf_net -intf_net axi_interconnect_1_m02 [get_bd_intf_pins axi_interconnect_1/M02_AXI] [get_bd_intf_pins axi_uart_1/s_axi]
+connect_bd_intf_net -intf_net axi_interconnect_1_m03 [get_bd_intf_pins axi_interconnect_1/M03_AXI] [get_bd_intf_pins axi_timer_1/s_axi]
+connect_bd_intf_net -intf_net axi_interconnect_1_m04 [get_bd_intf_pins axi_interconnect_1/M04_AXI] [get_bd_intf_pins axi_intc_1/s_axi]
+connect_bd_intf_net -intf_net axi_interconnect_1_m05 [get_bd_intf_pins axi_interconnect_1/M05_AXI] [get_bd_intf_pins axi_gpio_1/s_axi]
+connect_bd_intf_net -intf_net axi_interconnect_1_m06 [get_bd_intf_pins axi_interconnect_1/M06_AXI] [get_bd_intf_pins axi_gpio_2/s_axi]
+connect_bd_intf_net -intf_net axi_interconnect_1_m07 [get_bd_intf_pins axi_interconnect_1/M07_AXI] [get_bd_intf_pins axi_iic_1/s_axi]
+connect_bd_intf_net -intf_net axi_interconnect_1_m13 [get_bd_intf_pins axi_interconnect_1/M13_AXI] [get_bd_intf_pins axi_ethernet_dma_1/S_AXI_LITE]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/S00_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M00_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M01_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M02_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M03_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M04_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M05_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M06_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M07_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M13_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/S00_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M00_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M01_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M02_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M03_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M04_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M05_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M06_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M07_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M13_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+
+# defaults (interconnect - memory)
+
+connect_bd_intf_net -intf_net axi_interconnect_2_m00 [get_bd_intf_pins axi_interconnect_2/M00_AXI] [get_bd_intf_pins axi_ddr_cntrl_1/S_AXI]
+connect_bd_intf_net -intf_net axi_interconnect_2_s00 [get_bd_intf_pins axi_interconnect_2/S00_AXI] [get_bd_intf_pins microblaze_1/M_AXI_DC]
+connect_bd_intf_net -intf_net axi_interconnect_2_s01 [get_bd_intf_pins axi_interconnect_2/S01_AXI] [get_bd_intf_pins microblaze_1/M_AXI_IC]
+connect_bd_intf_net -intf_net axi_interconnect_2_s05 [get_bd_intf_pins axi_interconnect_2/S05_AXI] [get_bd_intf_pins axi_ethernet_dma_1/M_AXI_SG]
+connect_bd_intf_net -intf_net axi_interconnect_2_s06 [get_bd_intf_pins axi_interconnect_2/S06_AXI] [get_bd_intf_pins axi_ethernet_dma_1/M_AXI_MM2S]
+connect_bd_intf_net -intf_net axi_interconnect_2_s07 [get_bd_intf_pins axi_interconnect_2/S07_AXI] [get_bd_intf_pins axi_ethernet_dma_1/M_AXI_S2MM]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/M00_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S00_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S01_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S05_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S06_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S07_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net axi_ddr_cntrl_1_100mhz [get_bd_pins axi_interconnect_2/M00_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_2/S00_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_2/S01_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_2/S05_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_2/S06_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_2/S07_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+
+# ethernet & ethernet dma
+
+connect_bd_net -net axi_ethernet_dma_1_txd_rstn [get_bd_pins axi_ethernet_1/axi_txd_arstn] [get_bd_pins axi_ethernet_dma_1/mm2s_prmry_reset_out_n]
+connect_bd_net -net axi_ethernet_dma_1_txc_rstn [get_bd_pins axi_ethernet_1/axi_txc_arstn] [get_bd_pins axi_ethernet_dma_1/mm2s_cntrl_reset_out_n]
+connect_bd_net -net axi_ethernet_dma_1_rxd_rstn [get_bd_pins axi_ethernet_1/axi_rxd_arstn] [get_bd_pins axi_ethernet_dma_1/s2mm_prmry_reset_out_n]
+connect_bd_net -net axi_ethernet_dma_1_rxs_rstn [get_bd_pins axi_ethernet_1/axi_rxs_arstn] [get_bd_pins axi_ethernet_dma_1/s2mm_sts_reset_out_n]
+
+connect_bd_intf_net -intf_net axi_ethernet_dma_1_txd [get_bd_intf_pins axi_ethernet_1/s_axis_txd] [get_bd_intf_pins axi_ethernet_dma_1/M_AXIS_MM2S]
+connect_bd_intf_net -intf_net axi_ethernet_dma_1_txc [get_bd_intf_pins axi_ethernet_1/s_axis_txc] [get_bd_intf_pins axi_ethernet_dma_1/M_AXIS_CNTRL]
+connect_bd_intf_net -intf_net axi_ethernet_dma_1_rxd [get_bd_intf_pins axi_ethernet_1/m_axis_rxd] [get_bd_intf_pins axi_ethernet_dma_1/S_AXIS_S2MM]
+connect_bd_intf_net -intf_net axi_ethernet_dma_1_rxs [get_bd_intf_pins axi_ethernet_1/m_axis_rxs] [get_bd_intf_pins axi_ethernet_dma_1/S_AXIS_STS]
+
+# defaults (interrupts)
+
+connect_bd_net -net concat_intc_1_intr_00 [get_bd_pins concat_intc_1/In0] [get_bd_pins axi_timer_1/interrupt]
+connect_bd_net -net concat_intc_1_intr_01 [get_bd_pins concat_intc_1/In1] [get_bd_pins axi_ethernet_1/interrupt]
+connect_bd_net -net concat_intc_1_intr_02 [get_bd_pins concat_intc_1/In2] [get_bd_pins axi_uart_1/interrupt]
+connect_bd_net -net concat_intc_1_intr_03 [get_bd_pins concat_intc_1/In3] [get_bd_pins axi_gpio_1/ip2intc_irpt]
+connect_bd_net -net concat_intc_1_intr_04 [get_bd_pins concat_intc_1/In4] [get_bd_pins axi_gpio_2/ip2intc_irpt]
+connect_bd_net -net concat_intc_1_intr_05 [get_bd_pins concat_intc_1/In5] [get_bd_pins axi_iic_1/iic2intc_irpt]
+connect_bd_net -net concat_intc_1_intr_08 [get_bd_pins concat_intc_1/In8] [get_bd_pins axi_ethernet_dma_1/mm2s_introut]
+connect_bd_net -net concat_intc_1_intr_09 [get_bd_pins concat_intc_1/In9] [get_bd_pins axi_ethernet_dma_1/s2mm_introut]
+
+# defaults (external interface)
+
+connect_bd_net -net proc_const_vcc_1_vcc [get_bd_pins proc_const_vcc_1/const] [get_bd_ports fan_pwm] [get_bd_pins axi_ethernet_1/signal_detect]
+connect_bd_net -net sys_rst_s [get_bd_ports sys_rst] 
+connect_bd_net -net sys_rst_s [get_bd_pins proc_sys_reset_1/ext_reset_in]
+connect_bd_net -net sys_rst_s [get_bd_pins axi_ddr_cntrl_1/sys_rst]
+
+connect_bd_net -net sys_clk_p_s [get_bd_ports sys_clk_p] [get_bd_pins axi_ddr_cntrl_1/sys_clk_p]
+connect_bd_net -net sys_clk_n_s [get_bd_ports sys_clk_n] [get_bd_pins axi_ddr_cntrl_1/sys_clk_n]
+
+connect_bd_intf_net -intf_net axi_ddr_cntrl_1_ddr3 [get_bd_intf_ports ddr3] [get_bd_intf_pins axi_ddr_cntrl_1/DDR3]
+connect_bd_net -net axi_ethernet_1_phy_rstn [get_bd_ports phy_rstn] [get_bd_pins axi_ethernet_1/phy_rst_n]
+connect_bd_intf_net -intf_net axi_ethernet_1_mgt_clk [get_bd_intf_ports mgt_clk] [get_bd_intf_pins axi_ethernet_1/mgt_clk]
+connect_bd_intf_net -intf_net axi_ethernet_1_sgmii [get_bd_intf_ports sgmii] [get_bd_intf_pins axi_ethernet_1/sgmii]
+connect_bd_intf_net -intf_net axi_ethernet_1_mdio [get_bd_intf_ports mdio] [get_bd_intf_pins axi_ethernet_1/mdio]
+
+connect_bd_net -net axi_uart_1_sin [get_bd_ports uart_sin] [get_bd_pins axi_uart_1/rx]
+connect_bd_net -net axi_uart_1_sout [get_bd_ports uart_sout] [get_bd_pins axi_uart_1/tx]
+
+connect_bd_intf_net -intf_net axi_gpio_1_gpio [get_bd_intf_ports gpio_lcd] [get_bd_intf_pins axi_gpio_1/gpio]
+connect_bd_intf_net -intf_net axi_gpio_2_gpio [get_bd_intf_ports gpio_sw] [get_bd_intf_pins axi_gpio_2/gpio]
+connect_bd_intf_net -intf_net axi_gpio_2_gpio2 [get_bd_intf_ports gpio_led] [get_bd_intf_pins axi_gpio_2/gpio2]
+
+connect_bd_net -net axi_iic_1_rstn [get_bd_ports iic_rstn] [get_bd_pins axi_iic_1/gpo]
+connect_bd_intf_net -intf_net axi_iic_1_iic [get_bd_intf_ports iic_main] [get_bd_intf_pins axi_iic_1/iic]
+
+# hdmi peripherals
+
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_hdmi_clkgen/s_axi_aresetn]
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_hdmi_dma/axi_resetn]
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_hdmi_core/s_axi_aresetn]
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_clkgen/s_axi_aclk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_clkgen/drp_clk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_dma/s_axi_lite_aclk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_dma/m_axi_mm2s_aclk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_dma/m_axis_mm2s_aclk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_core/s_axi_aclk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_core/m_axis_mm2s_clk] 
+connect_bd_net -net proc_sys_clk_1_200mhz [get_bd_pins axi_hdmi_clkgen/clk] 
+
+connect_bd_intf_net -intf_net axi_interconnect_1_m08 [get_bd_intf_pins axi_interconnect_1/M08_AXI] [get_bd_intf_pins axi_hdmi_clkgen/s_axi]
+connect_bd_intf_net -intf_net axi_interconnect_1_m09 [get_bd_intf_pins axi_interconnect_1/M09_AXI] [get_bd_intf_pins axi_hdmi_dma/S_AXI_LITE]
+connect_bd_intf_net -intf_net axi_interconnect_1_m10 [get_bd_intf_pins axi_interconnect_1/M10_AXI] [get_bd_intf_pins axi_hdmi_core/s_axi]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M08_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M09_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M10_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M08_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M09_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M10_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+
+connect_bd_intf_net -intf_net axi_interconnect_2_s02 [get_bd_intf_pins axi_interconnect_2/S02_AXI] [get_bd_intf_pins axi_hdmi_dma/M_AXI_MM2S]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S02_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_2/S02_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+
+connect_bd_net -net concat_intc_1_intr_06 [get_bd_pins concat_intc_1/In6] [get_bd_pins axi_hdmi_dma/mm2s_introut]
+
+connect_bd_net -net axi_hdmi_core_hdmi_out_clk  [get_bd_ports hdmi_out_clk] [get_bd_pins axi_hdmi_core/hdmi_out_clk]
+connect_bd_net -net axi_hdmi_core_hdmi_hsync    [get_bd_ports hdmi_hsync]   [get_bd_pins axi_hdmi_core/hdmi_36_hsync]
+connect_bd_net -net axi_hdmi_core_hdmi_vsync    [get_bd_ports hdmi_vsync]   [get_bd_pins axi_hdmi_core/hdmi_36_vsync]
+connect_bd_net -net axi_hdmi_core_hdmi_data_e   [get_bd_ports hdmi_data_e]  [get_bd_pins axi_hdmi_core/hdmi_36_data_e]
+connect_bd_net -net axi_hdmi_core_hdmi_data     [get_bd_ports hdmi_data]    [get_bd_pins axi_hdmi_core/hdmi_36_data]
+
+connect_bd_net -net axi_hdmi_clkgen_clk [get_bd_pins axi_hdmi_clkgen/clk_0]           [get_bd_pins axi_hdmi_core/hdmi_clk]
+connect_bd_net -net axi_hdmi_core_valid [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tvalid] [get_bd_pins axi_hdmi_core/m_axis_mm2s_tvalid]
+connect_bd_net -net axi_hdmi_core_data  [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tdata]  [get_bd_pins axi_hdmi_core/m_axis_mm2s_tdata]
+connect_bd_net -net axi_hdmi_core_keep  [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tkeep]  [get_bd_pins axi_hdmi_core/m_axis_mm2s_tkeep]
+connect_bd_net -net axi_hdmi_core_last  [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tlast]  [get_bd_pins axi_hdmi_core/m_axis_mm2s_tlast]
+connect_bd_net -net axi_hdmi_core_ready [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tready] [get_bd_pins axi_hdmi_core/m_axis_mm2s_tready]
+connect_bd_net -net axi_hdmi_core_fsync [get_bd_pins axi_hdmi_dma/mm2s_fsync]         [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync]
+connect_bd_net -net axi_hdmi_core_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync_ret]
+
+# spdif audio
+
+connect_bd_intf_net -intf_net axi_interconnect_1_m11 [get_bd_intf_pins axi_interconnect_1/M11_AXI] [get_bd_intf_pins axi_spdif_tx_core/s_axi]
+connect_bd_intf_net -intf_net axi_interconnect_1_m12 [get_bd_intf_pins axi_interconnect_1/M12_AXI] [get_bd_intf_pins axi_spdif_tx_dma/S_AXI_LITE]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M11_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M12_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_spdif_tx_core/S_AXI_ARESETN]
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_spdif_tx_core/S_AXIS_ARESETN]
+connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_spdif_tx_dma/axi_resetn]
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M11_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M12_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_spdif_tx_core/S_AXI_ACLK]
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_spdif_tx_dma/s_axi_lite_aclk] 
+
+connect_bd_intf_net -intf_net axi_interconnect_2_s03 [get_bd_intf_pins axi_interconnect_2/S03_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_SG]
+connect_bd_intf_net -intf_net axi_interconnect_2_s04 [get_bd_intf_pins axi_interconnect_2/S04_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_MM2S]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S03_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S04_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_2/S03_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_2/S04_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_spdif_tx_core/S_AXIS_ACLK]
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_spdif_tx_dma/m_axi_mm2s_aclk] 
+connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_spdif_tx_dma/m_axi_sg_aclk] 
+
+connect_bd_net -net axi_spdif_tx_dma_mm2s_valid [get_bd_pins axi_spdif_tx_core/S_AXIS_TVALID] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tvalid]
+connect_bd_net -net axi_spdif_tx_dma_mm2s_data  [get_bd_pins axi_spdif_tx_core/S_AXIS_TDATA]  [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tdata]
+connect_bd_net -net axi_spdif_tx_dma_mm2s_last  [get_bd_pins axi_spdif_tx_core/S_AXIS_TLAST]  [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tlast]
+connect_bd_net -net axi_spdif_tx_dma_mm2s_ready [get_bd_pins axi_spdif_tx_core/S_AXIS_TREADY] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tready]
+
+connect_bd_net -net concat_intc_1_intr_07 [get_bd_pins concat_intc_1/In7] [get_bd_pins axi_spdif_tx_dma/mm2s_introut]
+ 
+connect_bd_net -net proc_sys_clk_1_200mhz [get_bd_pins sys_audio_clkgen/clk_in1]
+connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk]
+connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o]
+
+# address mapping
+
+create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs dlmb_cntlr/SLMB/Mem]              SEG_data_dlmb_cntlr
+create_bd_addr_seg -range 0x00001000 -offset 0x41400000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs mb_debug/S_AXI/Reg]               SEG_data_mb_debug
+create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr]   SEG_data_ddr_cntrl_1
+create_bd_addr_seg -range 0x00040000 -offset 0x40E00000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs axi_ethernet_1/eth_buf/S_AXI/REG] SEG_data_ethernetlite_1
+create_bd_addr_seg -range 0x00010000 -offset 0x40010000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs axi_gpio_1/s_axi/Reg]             SEG_data_gpio_1
+create_bd_addr_seg -range 0x00010000 -offset 0x40020000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs axi_gpio_2/s_axi/Reg]             SEG_data_gpio_2
+create_bd_addr_seg -range 0x00010000 -offset 0x41600000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs axi_iic_1/s_axi/Reg]              SEG_data_iic_1
+create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs axi_intc_1/s_axi/Reg]             SEG_data_intc_1
+create_bd_addr_seg -range 0x00010000 -offset 0x41C00000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs axi_timer_1/s_axi/Reg]            SEG_data_timer_1
+create_bd_addr_seg -range 0x00010000 -offset 0x40600000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs axi_uart_1/s_axi/Reg]             SEG_data_uart_1
+create_bd_addr_seg -range 0x00010000 -offset 0x41E10000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs axi_ethernet_dma_1/S_AXI_LITE/Reg] SEG_data_ethernet_dma_1
+
+create_bd_addr_seg -range 0x00010000 -offset 0x79000000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite]   SEG_data_hdmi_clkgen
+create_bd_addr_seg -range 0x00010000 -offset 0x43000000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg]      SEG_data_hdmi_dma
+create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite]     SEG_data_hdmi_core
+
+create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0]     SEG_data_spdif_tx_core
+create_bd_addr_seg -range 0x00010000 -offset 0x41E00000 [get_bd_addr_spaces microblaze_1/Data]          [get_bd_addr_segs axi_spdif_tx_dma/S_AXI_LITE/Reg]  SEG_data_spdif_tx_dma
+
+create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces microblaze_1/Instruction]   [get_bd_addr_segs ilmb_cntlr/SLMB/Mem]              SEG_instr_ilmb_cntlr
+create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_1/Instruction]   [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr]   SEG_instr_ddr_cntrl_1
+
+create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S]     [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr]   SEG_mem_ddr_cntrl_1
+create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_SG]   [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr]   SEG_axi_ddr_cntrl_1
+create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr]   SEG_axi_ddr_cntrl_1
+
+create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_dma_1/Data_SG]   [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr] SEG_axi_ddr_cntrl_1
+create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_dma_1/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr] SEG_axi_ddr_cntrl_1
+create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_dma_1/Data_S2MM] [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr] SEG_axi_ddr_cntrl_1
+
diff --git a/projects/common/vc707/vc707_system_constr.xdc b/projects/common/vc707/vc707_system_constr.xdc
new file mode 100644
index 000000000..b1f9b77e7
--- /dev/null
+++ b/projects/common/vc707/vc707_system_constr.xdc
@@ -0,0 +1,136 @@
+
+# constraints
+
+set_property -dict  {PACKAGE_PIN  AV40  IOSTANDARD  LVCMOS18} [get_ports sys_rst]
+
+# clocks
+
+set_property -dict  {PACKAGE_PIN  E19   IOSTANDARD  LVDS} [get_ports sys_clk_p]
+set_property -dict  {PACKAGE_PIN  E18   IOSTANDARD  LVDS} [get_ports sys_clk_n]
+
+create_clock -name sys_clk      -period  5.00 [get_ports sys_clk_p]
+
+# ethernet
+
+set_property PACKAGE_PIN AN2 [get_ports sgmii_txp]
+set_property PACKAGE_PIN AN1 [get_ports sgmii_txn]
+set_property PACKAGE_PIN AM8 [get_ports sgmii_rxp]
+set_property PACKAGE_PIN AM7 [get_ports sgmii_rxn]
+
+set_property PACKAGE_PIN AH8 [get_ports mgt_clk_p]
+set_property PACKAGE_PIN AH7 [get_ports mgt_clk_n]
+
+set_property -dict  {PACKAGE_PIN  AJ33  IOSTANDARD  LVCMOS18} [get_ports phy_rstn]
+set_property -dict  {PACKAGE_PIN  AH31  IOSTANDARD  LVCMOS18} [get_ports mdio_mdc]
+set_property -dict  {PACKAGE_PIN  AK33  IOSTANDARD  LVCMOS18} [get_ports mdio_mdio]
+
+set_false_path -through [get_nets phy_rstn]
+
+# uart
+
+set_property -dict  {PACKAGE_PIN  AU33  IOSTANDARD  LVCMOS18} [get_ports uart_sin]
+set_property -dict  {PACKAGE_PIN  AU36  IOSTANDARD  LVCMOS18} [get_ports uart_sout]
+
+# fan
+
+set_property -dict  {PACKAGE_PIN  BA37  IOSTANDARD  LVCMOS18} [get_ports fan_pwm]
+
+# lcd
+
+set_property -dict  {PACKAGE_PIN  AT40  IOSTANDARD  LVCMOS18} [get_ports gpio_lcd[6]]   ; ## lcd_e    
+set_property -dict  {PACKAGE_PIN  AN41  IOSTANDARD  LVCMOS18} [get_ports gpio_lcd[5]]   ; ## lcd_rs   
+set_property -dict  {PACKAGE_PIN  AR42  IOSTANDARD  LVCMOS18} [get_ports gpio_lcd[4]]   ; ## lcd_rw   
+set_property -dict  {PACKAGE_PIN  AN40  IOSTANDARD  LVCMOS18} [get_ports gpio_lcd[3]]   ; ## lcd_db[7]
+set_property -dict  {PACKAGE_PIN  AR39  IOSTANDARD  LVCMOS18} [get_ports gpio_lcd[2]]   ; ## lcd_db[6]
+set_property -dict  {PACKAGE_PIN  AR38  IOSTANDARD  LVCMOS18} [get_ports gpio_lcd[1]]   ; ## lcd_db[5]
+set_property -dict  {PACKAGE_PIN  AT42  IOSTANDARD  LVCMOS18} [get_ports gpio_lcd[0]]   ; ## lcd_db[4]
+set_property -dict  {PACKAGE_PIN  AV30  IOSTANDARD  LVCMOS18} [get_ports gpio_sw[0]]    ; ## GPIO_DIP_SW0  
+set_property -dict  {PACKAGE_PIN  AY33  IOSTANDARD  LVCMOS18} [get_ports gpio_sw[1]]    ; ## GPIO_DIP_SW1  
+set_property -dict  {PACKAGE_PIN  BA31  IOSTANDARD  LVCMOS18} [get_ports gpio_sw[2]]    ; ## GPIO_DIP_SW2  
+set_property -dict  {PACKAGE_PIN  BA32  IOSTANDARD  LVCMOS18} [get_ports gpio_sw[3]]    ; ## GPIO_DIP_SW3  
+set_property -dict  {PACKAGE_PIN  AW30  IOSTANDARD  LVCMOS18} [get_ports gpio_sw[4]]    ; ## GPIO_DIP_SW4  
+set_property -dict  {PACKAGE_PIN  AY30  IOSTANDARD  LVCMOS18} [get_ports gpio_sw[5]]    ; ## GPIO_DIP_SW5  
+set_property -dict  {PACKAGE_PIN  BA30  IOSTANDARD  LVCMOS18} [get_ports gpio_sw[6]]    ; ## GPIO_DIP_SW6  
+set_property -dict  {PACKAGE_PIN  BB31  IOSTANDARD  LVCMOS18} [get_ports gpio_sw[7]]    ; ## GPIO_DIP_SW7  
+set_property -dict  {PACKAGE_PIN  AR40  IOSTANDARD  LVCMOS18} [get_ports gpio_sw[8]]    ; ## GPIO_SW_N     
+set_property -dict  {PACKAGE_PIN  AU38  IOSTANDARD  LVCMOS18} [get_ports gpio_sw[9]]    ; ## GPIO_SW_E     
+set_property -dict  {PACKAGE_PIN  AP40  IOSTANDARD  LVCMOS18} [get_ports gpio_sw[10]]   ; ## GPIO_SW_S     
+set_property -dict  {PACKAGE_PIN  AW40  IOSTANDARD  LVCMOS18} [get_ports gpio_sw[11]]   ; ## GPIO_SW_W     
+set_property -dict  {PACKAGE_PIN  AV39  IOSTANDARD  LVCMOS18} [get_ports gpio_sw[12]]   ; ## GPIO_SW_C     
+set_property -dict  {PACKAGE_PIN  AM39  IOSTANDARD  LVCMOS18} [get_ports gpio_led[0]]   ; ## GPIO_LED_0_LS
+set_property -dict  {PACKAGE_PIN  AN39  IOSTANDARD  LVCMOS18} [get_ports gpio_led[1]]   ; ## GPIO_LED_1_LS
+set_property -dict  {PACKAGE_PIN  AR37  IOSTANDARD  LVCMOS18} [get_ports gpio_led[2]]   ; ## GPIO_LED_2_LS
+set_property -dict  {PACKAGE_PIN  AT37  IOSTANDARD  LVCMOS18} [get_ports gpio_led[3]]   ; ## GPIO_LED_3_LS
+set_property -dict  {PACKAGE_PIN  AR35  IOSTANDARD  LVCMOS18} [get_ports gpio_led[4]]   ; ## GPIO_LED_4_LS
+set_property -dict  {PACKAGE_PIN  AP41  IOSTANDARD  LVCMOS18} [get_ports gpio_led[5]]   ; ## GPIO_LED_5_LS
+set_property -dict  {PACKAGE_PIN  AP42  IOSTANDARD  LVCMOS18} [get_ports gpio_led[6]]   ; ## GPIO_LED_6_LS
+set_property -dict  {PACKAGE_PIN  AU39  IOSTANDARD  LVCMOS18} [get_ports gpio_led[7]]   ; ## GPIO_LED_7_LS
+
+# iic
+
+set_property -dict  {PACKAGE_PIN  AY42  IOSTANDARD  LVCMOS18} [get_ports iic_rstn]
+set_property -dict  {PACKAGE_PIN  AT35  IOSTANDARD  LVCMOS18  DRIVE 8 SLEW SLOW} [get_ports iic_scl]
+set_property -dict  {PACKAGE_PIN  AU32  IOSTANDARD  LVCMOS18  DRIVE 8 SLEW SLOW} [get_ports iic_sda]
+
+# hdmi
+
+set_property -dict  {PACKAGE_PIN  AU23  IOSTANDARD  LVCMOS18} [get_ports hdmi_out_clk]
+set_property -dict  {PACKAGE_PIN  AU22  IOSTANDARD  LVCMOS18} [get_ports hdmi_hsync]
+set_property -dict  {PACKAGE_PIN  AT22  IOSTANDARD  LVCMOS18} [get_ports hdmi_vsync]
+set_property -dict  {PACKAGE_PIN  AP21  IOSTANDARD  LVCMOS18} [get_ports hdmi_data_e]
+set_property -dict  {PACKAGE_PIN  AM22  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[0]]
+set_property -dict  {PACKAGE_PIN  AL22  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[1]]
+set_property -dict  {PACKAGE_PIN  AJ20  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[2]]
+set_property -dict  {PACKAGE_PIN  AJ21  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[3]]
+set_property -dict  {PACKAGE_PIN  AM21  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[4]]
+set_property -dict  {PACKAGE_PIN  AL21  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[5]]
+set_property -dict  {PACKAGE_PIN  AK22  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[6]]
+set_property -dict  {PACKAGE_PIN  AJ22  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[7]]
+set_property -dict  {PACKAGE_PIN  AL20  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[8]]
+set_property -dict  {PACKAGE_PIN  AK20  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[9]]
+set_property -dict  {PACKAGE_PIN  AK23  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[10]]
+set_property -dict  {PACKAGE_PIN  AJ23  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[11]]
+set_property -dict  {PACKAGE_PIN  AN21  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[12]]
+set_property -dict  {PACKAGE_PIN  AP22  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[13]]
+set_property -dict  {PACKAGE_PIN  AP23  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[14]]
+set_property -dict  {PACKAGE_PIN  AN23  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[15]]
+set_property -dict  {PACKAGE_PIN  AM23  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[16]]
+set_property -dict  {PACKAGE_PIN  AN24  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[17]]
+set_property -dict  {PACKAGE_PIN  AY24  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[18]]
+set_property -dict  {PACKAGE_PIN  BB22  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[19]]
+set_property -dict  {PACKAGE_PIN  BA22  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[20]]
+set_property -dict  {PACKAGE_PIN  BA25  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[21]]
+set_property -dict  {PACKAGE_PIN  AY25  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[22]]
+set_property -dict  {PACKAGE_PIN  AY22  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[23]]
+set_property -dict  {PACKAGE_PIN  AY23  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[24]]
+set_property -dict  {PACKAGE_PIN  AV24  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[25]]
+set_property -dict  {PACKAGE_PIN  AU24  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[26]]
+set_property -dict  {PACKAGE_PIN  AW21  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[27]]
+set_property -dict  {PACKAGE_PIN  AV21  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[28]]
+set_property -dict  {PACKAGE_PIN  AT24  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[29]]
+set_property -dict  {PACKAGE_PIN  AR24  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[30]]
+set_property -dict  {PACKAGE_PIN  AU21  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[31]]
+set_property -dict  {PACKAGE_PIN  AT21  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[32]]
+set_property -dict  {PACKAGE_PIN  AW22  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[33]]
+set_property -dict  {PACKAGE_PIN  AW23  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[34]]
+set_property -dict  {PACKAGE_PIN  AV23  IOSTANDARD  LVCMOS18} [get_ports hdmi_data[35]]
+
+# spdif
+
+set_property -dict  {PACKAGE_PIN  AR23  IOSTANDARD  LVCMOS18} [get_ports spdif]
+
+# clocks
+
+create_clock -name ddr_clk      -period 10.00 [get_nets i_system_wrapper/system_i/axi_ddr_cntrl_1_100mhz]
+create_clock -name cpu_clk      -period 10.00 [get_nets i_system_wrapper/system_i/proc_sys_clk_1_100mhz]
+create_clock -name m200_clk     -period  5.00 [get_nets i_system_wrapper/system_i/proc_sys_clk_1_200mhz]
+create_clock -name hdmi_clk     -period  6.73 [get_nets i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s]
+create_clock -name spdif_clk    -period 50.00 [get_nets i_system_wrapper/system_i/sys_audio_clkgen_clk]
+
+set_clock_groups -asynchronous -group {cpu_clk}
+set_clock_groups -asynchronous -group {m200_clk}
+set_clock_groups -asynchronous -group {hdmi_clk}
+set_clock_groups -asynchronous -group {spdif_clk}
+
+
+
diff --git a/projects/common/vc707/vc707_system_mig.prj b/projects/common/vc707/vc707_system_mig.prj
new file mode 100644
index 000000000..829ed4d81
--- /dev/null
+++ b/projects/common/vc707/vc707_system_mig.prj
@@ -0,0 +1,201 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
+<Project NoOfControllers="1" >
+    <ModuleName>system_axi_ddr_cntrl_1_0</ModuleName>
+    <dci_inouts_inputs>1</dci_inouts_inputs>
+    <dci_inputs>1</dci_inputs>
+    <Debug_En>OFF</Debug_En>
+    <DataDepth_En>1024</DataDepth_En>
+    <LowPower_En>ON</LowPower_En>
+    <XADC_En>Disabled</XADC_En>
+    <TargetFPGA>xc7vx485t-ffg1761/-2</TargetFPGA>
+    <Version>2.0</Version>
+    <SystemClock>Differential</SystemClock>
+    <ReferenceClock>Use System Clock</ReferenceClock>
+    <SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
+    <BankSelectionFlag>FALSE</BankSelectionFlag>
+    <InternalVref>0</InternalVref>
+    <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
+    <dci_cascade>0</dci_cascade>
+    <Controller number="0" >
+        <MemoryDevice>DDR3_SDRAM/sodimms/MT8JTF12864HZ-1G6</MemoryDevice>
+        <TimePeriod>2500</TimePeriod>
+        <VccAuxIO>1.8V</VccAuxIO>
+        <PHYRatio>4:1</PHYRatio>
+        <InputClkFreq>200</InputClkFreq>
+        <UIExtraClocks>0</UIExtraClocks>
+        <MMCMClkOut0> 1.000</MMCMClkOut0>
+        <MMCMClkOut1>1</MMCMClkOut1>
+        <MMCMClkOut2>1</MMCMClkOut2>
+        <MMCMClkOut3>1</MMCMClkOut3>
+        <MMCMClkOut4>1</MMCMClkOut4>
+        <DataWidth>64</DataWidth>
+        <DeepMemory>1</DeepMemory>
+        <DataMask>1</DataMask>
+        <ECC>Disabled</ECC>
+        <Ordering>Normal</Ordering>
+        <CustomPart>FALSE</CustomPart>
+        <NewPartName></NewPartName>
+        <RowAddress>14</RowAddress>
+        <ColAddress>10</ColAddress>
+        <BankAddress>3</BankAddress>
+        <MemoryVoltage>1.5V</MemoryVoltage>
+        <UserMemoryAddressMap>ROW_BANK_COLUMN</UserMemoryAddressMap>
+        <PinSelection>
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A20" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B21" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B17" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A15" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A21" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B19" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C20" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A19" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A17" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A16" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D20" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C18" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D17" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C19" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D21" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C21" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D18" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="K17" SLEW="" name="ddr3_cas_n" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15" PADName="G18" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15" PADName="H19" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="K19" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="J17" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="M13" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="K15" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="F12" SLEW="" name="ddr3_dm[2]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A14" SLEW="" name="ddr3_dm[3]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C23" SLEW="" name="ddr3_dm[4]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D25" SLEW="" name="ddr3_dm[5]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C31" SLEW="" name="ddr3_dm[6]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="F31" SLEW="" name="ddr3_dm[7]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="N14" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="H13" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="J13" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L16" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L15" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="H14" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="J15" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E15" SLEW="" name="ddr3_dq[16]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E13" SLEW="" name="ddr3_dq[17]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F15" SLEW="" name="ddr3_dq[18]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E14" SLEW="" name="ddr3_dq[19]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="N13" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G13" SLEW="" name="ddr3_dq[20]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G12" SLEW="" name="ddr3_dq[21]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F14" SLEW="" name="ddr3_dq[22]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G14" SLEW="" name="ddr3_dq[23]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B14" SLEW="" name="ddr3_dq[24]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C13" SLEW="" name="ddr3_dq[25]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B16" SLEW="" name="ddr3_dq[26]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D15" SLEW="" name="ddr3_dq[27]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D13" SLEW="" name="ddr3_dq[28]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E12" SLEW="" name="ddr3_dq[29]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L14" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C16" SLEW="" name="ddr3_dq[30]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D16" SLEW="" name="ddr3_dq[31]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A24" SLEW="" name="ddr3_dq[32]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B23" SLEW="" name="ddr3_dq[33]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B27" SLEW="" name="ddr3_dq[34]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B26" SLEW="" name="ddr3_dq[35]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A22" SLEW="" name="ddr3_dq[36]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B22" SLEW="" name="ddr3_dq[37]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A25" SLEW="" name="ddr3_dq[38]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C24" SLEW="" name="ddr3_dq[39]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="M14" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E24" SLEW="" name="ddr3_dq[40]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D23" SLEW="" name="ddr3_dq[41]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D26" SLEW="" name="ddr3_dq[42]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C25" SLEW="" name="ddr3_dq[43]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E23" SLEW="" name="ddr3_dq[44]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D22" SLEW="" name="ddr3_dq[45]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F22" SLEW="" name="ddr3_dq[46]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E22" SLEW="" name="ddr3_dq[47]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A30" SLEW="" name="ddr3_dq[48]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D27" SLEW="" name="ddr3_dq[49]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="M12" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A29" SLEW="" name="ddr3_dq[50]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C28" SLEW="" name="ddr3_dq[51]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D28" SLEW="" name="ddr3_dq[52]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B31" SLEW="" name="ddr3_dq[53]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A31" SLEW="" name="ddr3_dq[54]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A32" SLEW="" name="ddr3_dq[55]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E30" SLEW="" name="ddr3_dq[56]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F29" SLEW="" name="ddr3_dq[57]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F30" SLEW="" name="ddr3_dq[58]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F27" SLEW="" name="ddr3_dq[59]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="N15" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C30" SLEW="" name="ddr3_dq[60]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E29" SLEW="" name="ddr3_dq[61]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F26" SLEW="" name="ddr3_dq[62]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D30" SLEW="" name="ddr3_dq[63]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="M11" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L12" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="K14" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="K13" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="M16" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="J12" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="G16" SLEW="" name="ddr3_dqs_n[2]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="C14" SLEW="" name="ddr3_dqs_n[3]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A27" SLEW="" name="ddr3_dqs_n[4]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E25" SLEW="" name="ddr3_dqs_n[5]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B29" SLEW="" name="ddr3_dqs_n[6]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E28" SLEW="" name="ddr3_dqs_n[7]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="N16" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="K12" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="H16" SLEW="" name="ddr3_dqs_p[2]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="C15" SLEW="" name="ddr3_dqs_p[3]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A26" SLEW="" name="ddr3_dqs_p[4]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="F25" SLEW="" name="ddr3_dqs_p[5]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B28" SLEW="" name="ddr3_dqs_p[6]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E27" SLEW="" name="ddr3_dqs_p[7]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="H20" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="E20" SLEW="" name="ddr3_ras_n" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="LVCMOS15" PADName="C29" SLEW="" name="ddr3_reset_n" IN_TERM="" />
+            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="F20" SLEW="" name="ddr3_we_n" IN_TERM="" />
+        </PinSelection>
+        <System_Clock>
+            <Pin PADName="E19/E18(CC_P/N)" Bank="38" name="sys_clk_p/n" />
+        </System_Clock>
+        <System_Control>
+            <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
+            <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
+            <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
+        </System_Control>
+        <TimingParameters>
+            <Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="30" trtp="7.5" tcke="5" trfc="110" trp="13.125" tras="35" trcd="13.125" />
+        </TimingParameters>
+        <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
+        <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
+        <mrCasLatency name="CAS Latency" >6</mrCasLatency>
+        <mrMode name="Mode" >Normal</mrMode>
+        <mrDllReset name="DLL Reset" >No</mrDllReset>
+        <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
+        <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
+        <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/6</emrOutputDriveStrength>
+        <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
+        <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
+        <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/4</emrRTT>
+        <emrPosted name="Additive Latency (AL)" >0</emrPosted>
+        <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
+        <emrDQS name="TDQS enable" >Enabled</emrDQS>
+        <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
+        <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
+        <mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
+        <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
+        <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
+        <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
+        <PortInterface>AXI</PortInterface>
+        <AXIParameters>
+            <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
+            <C0_S_AXI_ADDR_WIDTH>32</C0_S_AXI_ADDR_WIDTH>
+            <C0_S_AXI_DATA_WIDTH>512</C0_S_AXI_DATA_WIDTH>
+            <C0_S_AXI_ID_WIDTH>3</C0_S_AXI_ID_WIDTH>
+            <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
+        </AXIParameters>
+    </Controller>
+
+</Project>
diff --git a/projects/common/zc702/zc702_system_bd.tcl b/projects/common/zc702/zc702_system_bd.tcl
new file mode 100644
index 000000000..76293fbcc
--- /dev/null
+++ b/projects/common/zc702/zc702_system_bd.tcl
@@ -0,0 +1,191 @@
+
+# create board design
+# interface ports
+
+set DDR [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR]
+set FIXED_IO [create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO]
+set IIC_MAIN [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 IIC_MAIN]
+
+set GPIO_I [create_bd_port -dir I -from 31 -to 0 GPIO_I]
+set GPIO_O [create_bd_port -dir O -from 31 -to 0 GPIO_O]
+set GPIO_T [create_bd_port -dir O -from 31 -to 0 GPIO_T]
+
+# hdmi interface
+
+set hdmi_out_clk    [create_bd_port -dir O hdmi_out_clk]
+set hdmi_hsync      [create_bd_port -dir O hdmi_hsync]
+set hdmi_vsync      [create_bd_port -dir O hdmi_vsync]
+set hdmi_data_e     [create_bd_port -dir O hdmi_data_e]
+set hdmi_data       [create_bd_port -dir O -from 15 -to 0 hdmi_data]
+
+# spdif audio
+
+set spdif           [create_bd_port -dir O spdif]
+
+# instance: sys_ps7
+
+set sys_ps7  [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.3 sys_ps7]
+set_property -dict [list CONFIG.PCW_IMPORT_BOARD_PRESET {ZC702}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_S_AXI_HP0 {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {32}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_DMA0 {1}] $sys_ps7
+
+set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
+set_property -dict [list CONFIG.USE_BOARD_FLOW {true} CONFIG.IIC_BOARD_INTERFACE {IIC_MAIN}] $axi_iic_main
+
+set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 sys_concat_intc]
+set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc
+
+set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect]
+set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect
+
+# hdmi peripherals
+
+set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
+set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
+
+set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.1 axi_hdmi_dma]
+set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma
+set_property -dict [list CONFIG.c_use_mm2s_fsync {1}] $axi_hdmi_dma
+set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
+
+set axi_hdmi_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hdmi_interconnect]
+set_property -dict [list CONFIG.NUM_MI {1}] $axi_hdmi_interconnect
+
+# audio peripherals
+
+set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
+set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
+set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
+
+set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
+set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_spdif_tx_core
+set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core
+set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_spdif_tx_core
+set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_spdif_tx_core
+
+# interface connections
+
+connect_bd_intf_net -intf_net sys_ps7_ddr [get_bd_intf_ports DDR] [get_bd_intf_pins sys_ps7/DDR]
+connect_bd_net -net sys_ps7_GPIO_I [get_bd_ports GPIO_I] [get_bd_pins sys_ps7/GPIO_I]
+connect_bd_net -net sys_ps7_GPIO_O [get_bd_ports GPIO_O] [get_bd_pins sys_ps7/GPIO_O]
+connect_bd_net -net sys_ps7_GPIO_T [get_bd_ports GPIO_T] [get_bd_pins sys_ps7/GPIO_T]
+connect_bd_intf_net -intf_net sys_ps7_fixed_io [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins sys_ps7/FIXED_IO]
+connect_bd_intf_net -intf_net axi_iic_main_iic [get_bd_intf_ports IIC_MAIN] [get_bd_intf_pins axi_iic_main/iic]
+
+connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_200m_clk [get_bd_pins sys_ps7/FCLK_CLK1]
+
+connect_bd_net -net sys_100m_resetn [get_bd_pins sys_ps7/FCLK_RESET0_N]
+
+connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/M_AXI_GP0_ACLK]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+
+connect_bd_intf_net -intf_net axi_cpu_interconnect_s00_axi [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] [get_bd_intf_pins sys_ps7/M_AXI_GP0]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/S00_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/S00_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+
+connect_bd_intf_net -intf_net axi_cpu_interconnect_m00_axi [get_bd_intf_pins axi_cpu_interconnect/M00_AXI] [get_bd_intf_pins axi_iic_main/s_axi]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M00_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M00_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_iic_main/s_axi_aclk]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_iic_main/s_axi_aresetn]
+connect_bd_net -net sys_concat_intc_din_1 [get_bd_pins sys_concat_intc/In1] [get_bd_pins axi_iic_main/iic2intc_irpt]
+
+connect_bd_net -net sys_ps7_interrupt [get_bd_pins sys_concat_intc/dout] [get_bd_pins sys_ps7/IRQ_F2P]
+
+# hdmi
+
+connect_bd_net -net sys_200m_clk   [get_bd_pins axi_hdmi_clkgen/clk]
+
+connect_bd_intf_net -intf_net axi_cpu_interconnect_m01_axi [get_bd_intf_pins axi_cpu_interconnect/M01_AXI] [get_bd_intf_pins axi_hdmi_clkgen/s_axi]
+connect_bd_intf_net -intf_net axi_cpu_interconnect_m02_axi [get_bd_intf_pins axi_cpu_interconnect/M02_AXI] [get_bd_intf_pins axi_hdmi_core/s_axi]
+connect_bd_intf_net -intf_net axi_cpu_interconnect_m03_axi [get_bd_intf_pins axi_cpu_interconnect/M03_AXI] [get_bd_intf_pins axi_hdmi_dma/S_AXI_LITE]
+
+connect_bd_intf_net -intf_net axi_hdmi_interconnect_s00_axi [get_bd_intf_pins axi_hdmi_interconnect/S00_AXI] [get_bd_intf_pins axi_hdmi_dma/M_AXI_MM2S]
+connect_bd_intf_net -intf_net axi_hdmi_interconnect_m00_axi [get_bd_intf_pins axi_hdmi_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP0]
+
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M01_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M02_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M03_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_interconnect/ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_interconnect/S00_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_interconnect/M00_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/s_axi_aclk]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/drp_clk]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/s_axi_aclk]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/m_axis_mm2s_clk]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/s_axi_lite_aclk]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axi_mm2s_aclk]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axis_mm2s_aclk]
+connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP0_ACLK]
+
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M01_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M02_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M03_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_interconnect/ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_interconnect/S00_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_interconnect/M00_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_clkgen/s_axi_aresetn]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_core/s_axi_aresetn]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_dma/axi_resetn]
+
+connect_bd_net -net axi_hdmi_tx_core_hdmi_clk      [get_bd_pins axi_hdmi_core/hdmi_clk]              [get_bd_pins axi_hdmi_clkgen/clk_0]
+connect_bd_net -net axi_hdmi_tx_core_hdmi_out_clk  [get_bd_pins axi_hdmi_core/hdmi_out_clk]          [get_bd_ports hdmi_out_clk] 
+connect_bd_net -net axi_hdmi_tx_core_hdmi_hsync    [get_bd_pins axi_hdmi_core/hdmi_16_hsync]         [get_bd_ports hdmi_hsync]   
+connect_bd_net -net axi_hdmi_tx_core_hdmi_vsync    [get_bd_pins axi_hdmi_core/hdmi_16_vsync]         [get_bd_ports hdmi_vsync]   
+connect_bd_net -net axi_hdmi_tx_core_hdmi_data_e   [get_bd_pins axi_hdmi_core/hdmi_16_data_e]        [get_bd_ports hdmi_data_e]  
+connect_bd_net -net axi_hdmi_tx_core_hdmi_data     [get_bd_pins axi_hdmi_core/hdmi_16_data]          [get_bd_ports hdmi_data]    
+connect_bd_net -net axi_hdmi_tx_core_mm2s_tvalid   [get_bd_pins axi_hdmi_core/m_axis_mm2s_tvalid]    [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tvalid]
+connect_bd_net -net axi_hdmi_tx_core_mm2s_tdata    [get_bd_pins axi_hdmi_core/m_axis_mm2s_tdata]     [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tdata] 
+connect_bd_net -net axi_hdmi_tx_core_mm2s_tkeep    [get_bd_pins axi_hdmi_core/m_axis_mm2s_tkeep]     [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tkeep] 
+connect_bd_net -net axi_hdmi_tx_core_mm2s_tlast    [get_bd_pins axi_hdmi_core/m_axis_mm2s_tlast]     [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tlast] 
+connect_bd_net -net axi_hdmi_tx_core_mm2s_tready   [get_bd_pins axi_hdmi_core/m_axis_mm2s_tready]    [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tready]
+connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync    [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync]     [get_bd_pins axi_hdmi_dma/mm2s_fsync]        
+connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync    [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync_ret]
+
+connect_bd_net -net sys_concat_intc_din_0 [get_bd_pins sys_concat_intc/In0] [get_bd_pins axi_hdmi_dma/mm2s_introut] 
+
+# spdif audio
+
+connect_bd_intf_net -intf_net axi_cpu_interconnect_m04_axi [get_bd_intf_pins axi_cpu_interconnect/M04_AXI] [get_bd_intf_pins axi_spdif_tx_core/s_axi]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M04_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/S_AXI_ACLK]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M04_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_core/S_AXI_ARESETN]
+
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/DMA_REQ_ACLK]
+connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/DMA0_ACLK]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_core/DMA_REQ_RSTN]
+connect_bd_intf_net -intf_net axi_spdif_dma_req_tx [get_bd_intf_pins sys_ps7/DMA0_REQ] [get_bd_intf_pins axi_spdif_tx_core/DMA_REQ]
+connect_bd_intf_net -intf_net axi_spdif_dma_ack_tx [get_bd_intf_pins sys_ps7/DMA0_ACK] [get_bd_intf_pins axi_spdif_tx_core/DMA_ACK]
+
+connect_bd_net -net sys_200m_clk [get_bd_pins sys_audio_clkgen/clk_in1]
+connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk]
+connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o]
+
+# match up interconnects
+
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M05_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M05_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M06_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M06_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+
+# address map
+
+create_bd_addr_seg -range 0x00010000 -offset 0x41600000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_iic_main/s_axi/Reg]             SEG_data_iic_main
+create_bd_addr_seg -range 0x00010000 -offset 0x79000000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite]     SEG_data_hdmi_clkgen
+create_bd_addr_seg -range 0x00010000 -offset 0x43000000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg]        SEG_data_hdmi_dma
+create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite]       SEG_data_hdmi_core
+create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0]       SEG_data_spdif_core
+
+create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S]     [get_bd_addr_segs sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_sys_ps7_hp0_ddr_lowocm
+
diff --git a/projects/common/zc702/zc702_system_constr.xdc b/projects/common/zc702/zc702_system_constr.xdc
new file mode 100644
index 000000000..f4988d70f
--- /dev/null
+++ b/projects/common/zc702/zc702_system_constr.xdc
@@ -0,0 +1,67 @@
+
+# constraints
+# hdmi 
+
+set_property  -dict {PACKAGE_PIN  L16   IOSTANDARD LVCMOS25} [get_ports hdmi_out_clk]
+set_property  -dict {PACKAGE_PIN  H15   IOSTANDARD LVCMOS25} [get_ports hdmi_vsync]
+set_property  -dict {PACKAGE_PIN  R18   IOSTANDARD LVCMOS25} [get_ports hdmi_hsync]
+set_property  -dict {PACKAGE_PIN  T18   IOSTANDARD LVCMOS25} [get_ports hdmi_data_e]
+set_property  -dict {PACKAGE_PIN  AB21  IOSTANDARD LVCMOS25} [get_ports hdmi_data[0]]
+set_property  -dict {PACKAGE_PIN  AA21  IOSTANDARD LVCMOS25} [get_ports hdmi_data[1]]
+set_property  -dict {PACKAGE_PIN  AB22  IOSTANDARD LVCMOS25} [get_ports hdmi_data[2]]
+set_property  -dict {PACKAGE_PIN  AA22  IOSTANDARD LVCMOS25} [get_ports hdmi_data[3]]
+set_property  -dict {PACKAGE_PIN  V19   IOSTANDARD LVCMOS25} [get_ports hdmi_data[4]]
+set_property  -dict {PACKAGE_PIN  V18   IOSTANDARD LVCMOS25} [get_ports hdmi_data[5]]
+set_property  -dict {PACKAGE_PIN  V20   IOSTANDARD LVCMOS25} [get_ports hdmi_data[6]]
+set_property  -dict {PACKAGE_PIN  U20   IOSTANDARD LVCMOS25} [get_ports hdmi_data[7]]
+set_property  -dict {PACKAGE_PIN  W21   IOSTANDARD LVCMOS25} [get_ports hdmi_data[8]]
+set_property  -dict {PACKAGE_PIN  W20   IOSTANDARD LVCMOS25} [get_ports hdmi_data[9]]
+set_property  -dict {PACKAGE_PIN  W18   IOSTANDARD LVCMOS25} [get_ports hdmi_data[10]]
+set_property  -dict {PACKAGE_PIN  T19   IOSTANDARD LVCMOS25} [get_ports hdmi_data[11]]
+set_property  -dict {PACKAGE_PIN  U19   IOSTANDARD LVCMOS25} [get_ports hdmi_data[12]]
+set_property  -dict {PACKAGE_PIN  R19   IOSTANDARD LVCMOS25} [get_ports hdmi_data[13]]
+set_property  -dict {PACKAGE_PIN  T17   IOSTANDARD LVCMOS25} [get_ports hdmi_data[14]]
+set_property  -dict {PACKAGE_PIN  T16   IOSTANDARD LVCMOS25} [get_ports hdmi_data[15]]
+
+# spdif
+
+set_property  -dict {PACKAGE_PIN  R15   IOSTANDARD LVCMOS25} [get_ports spdif]
+
+# iic
+
+set_property  -dict {PACKAGE_PIN  W11   IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl]
+set_property  -dict {PACKAGE_PIN  W8    IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda]
+
+# gpio (switches, leds and such)
+
+set_property  -dict {PACKAGE_PIN  G19   IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]]   ; ## GPIO_SW_N
+set_property  -dict {PACKAGE_PIN  F19   IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]]   ; ## GPIO_SW_S
+set_property  -dict {PACKAGE_PIN  W6    IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]]   ; ## GPIO_DIP_SW0
+set_property  -dict {PACKAGE_PIN  W7    IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]]   ; ## GPIO_DIP_SW1
+
+set_property  -dict {PACKAGE_PIN  P17   IOSTANDARD LVCMOS25} [get_ports gpio_bd[4]]   ; ## PMOD2_3_LS
+set_property  -dict {PACKAGE_PIN  P18   IOSTANDARD LVCMOS25} [get_ports gpio_bd[5]]   ; ## PMOD2_2_LS
+set_property  -dict {PACKAGE_PIN  W10   IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]]   ; ## PMOD2_1_LS
+set_property  -dict {PACKAGE_PIN  V7    IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]]   ; ## PMOD2_0_LS
+set_property  -dict {PACKAGE_PIN  E15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[8]]   ; ## PMOD1_0_LS
+set_property  -dict {PACKAGE_PIN  D15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[9]]   ; ## PMOD1_1_LS
+set_property  -dict {PACKAGE_PIN  W17   IOSTANDARD LVCMOS25} [get_ports gpio_bd[10]]  ; ## PMOD1_2_LS
+set_property  -dict {PACKAGE_PIN  W5    IOSTANDARD LVCMOS25} [get_ports gpio_bd[11]]  ; ## PMOD1_3_LS
+
+set_property  -dict {PACKAGE_PIN  H17   IOSTANDARD LVCMOS25} [get_ports gpio_bd[12]]  ; ## XADC_GPIO_0
+set_property  -dict {PACKAGE_PIN  H22   IOSTANDARD LVCMOS25} [get_ports gpio_bd[13]]  ; ## XADC_GPIO_1
+set_property  -dict {PACKAGE_PIN  G22   IOSTANDARD LVCMOS25} [get_ports gpio_bd[14]]  ; ## XADC_GPIO_2
+set_property  -dict {PACKAGE_PIN  H18   IOSTANDARD LVCMOS25} [get_ports gpio_bd[15]]  ; ## XADC_GPIO_3
+
+# clocks
+
+create_clock -name cpu_clk      -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK0]
+create_clock -name m200_clk     -period  5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK1]
+create_clock -name hdmi_clk     -period  6.73 [get_pins i_system_wrapper/system_i/axi_hdmi_clkgen/clk_0]
+create_clock -name spdif_clk    -period 50.00 [get_pins i_system_wrapper/system_i/sys_audio_clkgen/clk_out1]
+
+set_clock_groups -asynchronous -group {cpu_clk}
+set_clock_groups -asynchronous -group {m200_clk}
+set_clock_groups -asynchronous -group {hdmi_clk}
+set_clock_groups -asynchronous -group {spdif_clk}
+
diff --git a/projects/common/zc706/zc706_system_bd.tcl b/projects/common/zc706/zc706_system_bd.tcl
new file mode 100644
index 000000000..7ca4dde71
--- /dev/null
+++ b/projects/common/zc706/zc706_system_bd.tcl
@@ -0,0 +1,191 @@
+
+# create board design
+# interface ports
+
+set DDR [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR]
+set FIXED_IO [create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO]
+set IIC_MAIN [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 IIC_MAIN]
+
+set GPIO_I [create_bd_port -dir I -from 31 -to 0 GPIO_I]
+set GPIO_O [create_bd_port -dir O -from 31 -to 0 GPIO_O]
+set GPIO_T [create_bd_port -dir O -from 31 -to 0 GPIO_T]
+
+# hdmi interface
+
+set hdmi_out_clk    [create_bd_port -dir O hdmi_out_clk]
+set hdmi_hsync      [create_bd_port -dir O hdmi_hsync]
+set hdmi_vsync      [create_bd_port -dir O hdmi_vsync]
+set hdmi_data_e     [create_bd_port -dir O hdmi_data_e]
+set hdmi_data       [create_bd_port -dir O -from 23 -to 0 hdmi_data]
+
+# spdif audio
+
+set spdif           [create_bd_port -dir O spdif]
+
+# instance: sys_ps7
+
+set sys_ps7  [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.3 sys_ps7]
+set_property -dict [list CONFIG.PCW_IMPORT_BOARD_PRESET {ZC706}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_S_AXI_HP0 {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {32}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_DMA0 {1}] $sys_ps7
+
+set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
+set_property -dict [list CONFIG.USE_BOARD_FLOW {true} CONFIG.IIC_BOARD_INTERFACE {IIC_MAIN}] $axi_iic_main
+
+set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 sys_concat_intc]
+set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc
+
+set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect]
+set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect
+
+# hdmi peripherals
+
+set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
+set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
+
+set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.1 axi_hdmi_dma]
+set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma
+set_property -dict [list CONFIG.c_use_mm2s_fsync {1}] $axi_hdmi_dma
+set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
+
+set axi_hdmi_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hdmi_interconnect]
+set_property -dict [list CONFIG.NUM_MI {1}] $axi_hdmi_interconnect
+
+# audio peripherals
+
+set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
+set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
+set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
+
+set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
+set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_spdif_tx_core
+set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core
+set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_spdif_tx_core
+set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_spdif_tx_core
+
+# interface connections
+
+connect_bd_intf_net -intf_net sys_ps7_ddr [get_bd_intf_ports DDR] [get_bd_intf_pins sys_ps7/DDR]
+connect_bd_net -net sys_ps7_GPIO_I [get_bd_ports GPIO_I] [get_bd_pins sys_ps7/GPIO_I]
+connect_bd_net -net sys_ps7_GPIO_O [get_bd_ports GPIO_O] [get_bd_pins sys_ps7/GPIO_O]
+connect_bd_net -net sys_ps7_GPIO_T [get_bd_ports GPIO_T] [get_bd_pins sys_ps7/GPIO_T]
+connect_bd_intf_net -intf_net sys_ps7_fixed_io [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins sys_ps7/FIXED_IO]
+connect_bd_intf_net -intf_net axi_iic_main_iic [get_bd_intf_ports IIC_MAIN] [get_bd_intf_pins axi_iic_main/iic]
+
+connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_200m_clk [get_bd_pins sys_ps7/FCLK_CLK1]
+
+connect_bd_net -net sys_100m_resetn [get_bd_pins sys_ps7/FCLK_RESET0_N]
+
+connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/M_AXI_GP0_ACLK]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+
+connect_bd_intf_net -intf_net axi_cpu_interconnect_s00_axi [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] [get_bd_intf_pins sys_ps7/M_AXI_GP0]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/S00_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/S00_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+
+connect_bd_intf_net -intf_net axi_cpu_interconnect_m00_axi [get_bd_intf_pins axi_cpu_interconnect/M00_AXI] [get_bd_intf_pins axi_iic_main/s_axi]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M00_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M00_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_iic_main/s_axi_aclk]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_iic_main/s_axi_aresetn]
+connect_bd_net -net sys_concat_intc_din_1 [get_bd_pins sys_concat_intc/In1] [get_bd_pins axi_iic_main/iic2intc_irpt]
+
+connect_bd_net -net sys_ps7_interrupt [get_bd_pins sys_concat_intc/dout] [get_bd_pins sys_ps7/IRQ_F2P]
+
+# hdmi
+
+connect_bd_net -net sys_200m_clk   [get_bd_pins axi_hdmi_clkgen/clk]
+
+connect_bd_intf_net -intf_net axi_cpu_interconnect_m01_axi [get_bd_intf_pins axi_cpu_interconnect/M01_AXI] [get_bd_intf_pins axi_hdmi_clkgen/s_axi]
+connect_bd_intf_net -intf_net axi_cpu_interconnect_m02_axi [get_bd_intf_pins axi_cpu_interconnect/M02_AXI] [get_bd_intf_pins axi_hdmi_core/s_axi]
+connect_bd_intf_net -intf_net axi_cpu_interconnect_m03_axi [get_bd_intf_pins axi_cpu_interconnect/M03_AXI] [get_bd_intf_pins axi_hdmi_dma/S_AXI_LITE]
+
+connect_bd_intf_net -intf_net axi_hdmi_interconnect_s00_axi [get_bd_intf_pins axi_hdmi_interconnect/S00_AXI] [get_bd_intf_pins axi_hdmi_dma/M_AXI_MM2S]
+connect_bd_intf_net -intf_net axi_hdmi_interconnect_m00_axi [get_bd_intf_pins axi_hdmi_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP0]
+
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M01_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M02_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M03_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_interconnect/ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_interconnect/S00_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_interconnect/M00_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/s_axi_aclk]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/drp_clk]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/s_axi_aclk]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/m_axis_mm2s_clk]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/s_axi_lite_aclk]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axi_mm2s_aclk]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axis_mm2s_aclk]
+connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP0_ACLK]
+
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M01_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M02_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M03_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_interconnect/ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_interconnect/S00_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_interconnect/M00_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_clkgen/s_axi_aresetn]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_core/s_axi_aresetn]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_dma/axi_resetn]
+
+connect_bd_net -net axi_hdmi_tx_core_hdmi_clk      [get_bd_pins axi_hdmi_core/hdmi_clk]              [get_bd_pins axi_hdmi_clkgen/clk_0]
+connect_bd_net -net axi_hdmi_tx_core_hdmi_out_clk  [get_bd_pins axi_hdmi_core/hdmi_out_clk]          [get_bd_ports hdmi_out_clk] 
+connect_bd_net -net axi_hdmi_tx_core_hdmi_hsync    [get_bd_pins axi_hdmi_core/hdmi_24_hsync]         [get_bd_ports hdmi_hsync]   
+connect_bd_net -net axi_hdmi_tx_core_hdmi_vsync    [get_bd_pins axi_hdmi_core/hdmi_24_vsync]         [get_bd_ports hdmi_vsync]   
+connect_bd_net -net axi_hdmi_tx_core_hdmi_data_e   [get_bd_pins axi_hdmi_core/hdmi_24_data_e]        [get_bd_ports hdmi_data_e]  
+connect_bd_net -net axi_hdmi_tx_core_hdmi_data     [get_bd_pins axi_hdmi_core/hdmi_24_data]          [get_bd_ports hdmi_data]    
+connect_bd_net -net axi_hdmi_tx_core_mm2s_tvalid   [get_bd_pins axi_hdmi_core/m_axis_mm2s_tvalid]    [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tvalid]
+connect_bd_net -net axi_hdmi_tx_core_mm2s_tdata    [get_bd_pins axi_hdmi_core/m_axis_mm2s_tdata]     [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tdata] 
+connect_bd_net -net axi_hdmi_tx_core_mm2s_tkeep    [get_bd_pins axi_hdmi_core/m_axis_mm2s_tkeep]     [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tkeep] 
+connect_bd_net -net axi_hdmi_tx_core_mm2s_tlast    [get_bd_pins axi_hdmi_core/m_axis_mm2s_tlast]     [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tlast] 
+connect_bd_net -net axi_hdmi_tx_core_mm2s_tready   [get_bd_pins axi_hdmi_core/m_axis_mm2s_tready]    [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tready]
+connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync    [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync]     [get_bd_pins axi_hdmi_dma/mm2s_fsync]        
+connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync    [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync_ret]
+
+connect_bd_net -net sys_concat_intc_din_0 [get_bd_pins sys_concat_intc/In0] [get_bd_pins axi_hdmi_dma/mm2s_introut] 
+
+# spdif audio
+
+connect_bd_intf_net -intf_net axi_cpu_interconnect_m04_axi [get_bd_intf_pins axi_cpu_interconnect/M04_AXI] [get_bd_intf_pins axi_spdif_tx_core/s_axi]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M04_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/S_AXI_ACLK]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M04_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_core/S_AXI_ARESETN]
+
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/DMA_REQ_ACLK]
+connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/DMA0_ACLK]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_core/DMA_REQ_RSTN]
+connect_bd_intf_net -intf_net axi_spdif_dma_req_tx [get_bd_intf_pins sys_ps7/DMA0_REQ] [get_bd_intf_pins axi_spdif_tx_core/DMA_REQ]
+connect_bd_intf_net -intf_net axi_spdif_dma_ack_tx [get_bd_intf_pins sys_ps7/DMA0_ACK] [get_bd_intf_pins axi_spdif_tx_core/DMA_ACK]
+
+connect_bd_net -net sys_200m_clk [get_bd_pins sys_audio_clkgen/clk_in1]
+connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk]
+connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o]
+
+# match up interconnects
+
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M05_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M05_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M06_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M06_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+
+# address map
+
+create_bd_addr_seg -range 0x00010000 -offset 0x41600000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_iic_main/s_axi/Reg]             SEG_data_iic_main
+create_bd_addr_seg -range 0x00010000 -offset 0x79000000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite]     SEG_data_hdmi_clkgen
+create_bd_addr_seg -range 0x00010000 -offset 0x43000000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg]        SEG_data_hdmi_dma
+create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite]       SEG_data_hdmi_core
+create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0]       SEG_data_spdif_core
+
+create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S]     [get_bd_addr_segs sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_sys_ps7_hp0_ddr_lowocm
+
diff --git a/projects/common/zc706/zc706_system_constr.xdc b/projects/common/zc706/zc706_system_constr.xdc
new file mode 100644
index 000000000..1eb1c2adb
--- /dev/null
+++ b/projects/common/zc706/zc706_system_constr.xdc
@@ -0,0 +1,74 @@
+
+# constraints
+# hdmi 
+
+set_property  -dict {PACKAGE_PIN  P28   IOSTANDARD LVCMOS25} [get_ports hdmi_out_clk]
+set_property  -dict {PACKAGE_PIN  U21   IOSTANDARD LVCMOS25} [get_ports hdmi_vsync]
+set_property  -dict {PACKAGE_PIN  R22   IOSTANDARD LVCMOS25} [get_ports hdmi_hsync]
+set_property  -dict {PACKAGE_PIN  V24   IOSTANDARD LVCMOS25} [get_ports hdmi_data_e]
+set_property  -dict {PACKAGE_PIN  U24   IOSTANDARD LVCMOS25} [get_ports hdmi_data[0]]
+set_property  -dict {PACKAGE_PIN  T22   IOSTANDARD LVCMOS25} [get_ports hdmi_data[1]]
+set_property  -dict {PACKAGE_PIN  R23   IOSTANDARD LVCMOS25} [get_ports hdmi_data[2]]
+set_property  -dict {PACKAGE_PIN  AA25  IOSTANDARD LVCMOS25} [get_ports hdmi_data[3]]
+set_property  -dict {PACKAGE_PIN  AE28  IOSTANDARD LVCMOS25} [get_ports hdmi_data[4]]
+set_property  -dict {PACKAGE_PIN  T23   IOSTANDARD LVCMOS25} [get_ports hdmi_data[5]]
+set_property  -dict {PACKAGE_PIN  AB25  IOSTANDARD LVCMOS25} [get_ports hdmi_data[6]]
+set_property  -dict {PACKAGE_PIN  T27   IOSTANDARD LVCMOS25} [get_ports hdmi_data[7]]
+set_property  -dict {PACKAGE_PIN  AD26  IOSTANDARD LVCMOS25} [get_ports hdmi_data[8]]
+set_property  -dict {PACKAGE_PIN  AB26  IOSTANDARD LVCMOS25} [get_ports hdmi_data[9]]
+set_property  -dict {PACKAGE_PIN  AA28  IOSTANDARD LVCMOS25} [get_ports hdmi_data[10]]
+set_property  -dict {PACKAGE_PIN  AC26  IOSTANDARD LVCMOS25} [get_ports hdmi_data[11]]
+set_property  -dict {PACKAGE_PIN  AE30  IOSTANDARD LVCMOS25} [get_ports hdmi_data[12]]
+set_property  -dict {PACKAGE_PIN  Y25   IOSTANDARD LVCMOS25} [get_ports hdmi_data[13]]
+set_property  -dict {PACKAGE_PIN  AA29  IOSTANDARD LVCMOS25} [get_ports hdmi_data[14]]
+set_property  -dict {PACKAGE_PIN  AD30  IOSTANDARD LVCMOS25} [get_ports hdmi_data[15]]
+set_property  -dict {PACKAGE_PIN  Y28   IOSTANDARD LVCMOS25} [get_ports hdmi_data[16]]
+set_property  -dict {PACKAGE_PIN  AF28  IOSTANDARD LVCMOS25} [get_ports hdmi_data[17]]
+set_property  -dict {PACKAGE_PIN  V22   IOSTANDARD LVCMOS25} [get_ports hdmi_data[18]]
+set_property  -dict {PACKAGE_PIN  AA27  IOSTANDARD LVCMOS25} [get_ports hdmi_data[19]]
+set_property  -dict {PACKAGE_PIN  U22   IOSTANDARD LVCMOS25} [get_ports hdmi_data[20]]
+set_property  -dict {PACKAGE_PIN  N28   IOSTANDARD LVCMOS25} [get_ports hdmi_data[21]]
+set_property  -dict {PACKAGE_PIN  V21   IOSTANDARD LVCMOS25} [get_ports hdmi_data[22]]
+set_property  -dict {PACKAGE_PIN  AC22  IOSTANDARD LVCMOS25} [get_ports hdmi_data[23]]
+
+# spdif
+
+set_property  -dict {PACKAGE_PIN  AC21  IOSTANDARD LVCMOS25} [get_ports spdif]
+
+# iic
+
+set_property  -dict {PACKAGE_PIN  AJ14  IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl]
+set_property  -dict {PACKAGE_PIN  AJ18  IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda]
+
+# gpio (switches, leds and such)
+
+set_property  -dict {PACKAGE_PIN  AB17  IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]]           ; ## GPIO_DIP_SW0   
+set_property  -dict {PACKAGE_PIN  AC16  IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]]           ; ## GPIO_DIP_SW1   
+set_property  -dict {PACKAGE_PIN  AC17  IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]]           ; ## GPIO_DIP_SW2   
+set_property  -dict {PACKAGE_PIN  AJ13  IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]]           ; ## GPIO_DIP_SW3   
+set_property  -dict {PACKAGE_PIN  AK25  IOSTANDARD LVCMOS25} [get_ports gpio_bd[4]]           ; ## GPIO_SW_LEFT   
+set_property  -dict {PACKAGE_PIN  K15   IOSTANDARD LVCMOS15} [get_ports gpio_bd[5]]           ; ## GPIO_SW_CENTER 
+set_property  -dict {PACKAGE_PIN  R27   IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]]           ; ## GPIO_SW_RIGHT  
+
+set_property  -dict {PACKAGE_PIN  Y21   IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]]           ; ## GPIO_LED_LEFT  
+set_property  -dict {PACKAGE_PIN  G2    IOSTANDARD LVCMOS15} [get_ports gpio_bd[8]]           ; ## GPIO_LED_CENTER
+set_property  -dict {PACKAGE_PIN  W21   IOSTANDARD LVCMOS25} [get_ports gpio_bd[9]]           ; ## GPIO_LED_RIGHT 
+set_property  -dict {PACKAGE_PIN  A17   IOSTANDARD LVCMOS15} [get_ports gpio_bd[10]]          ; ## GPIO_LED_0     
+
+set_property  -dict {PACKAGE_PIN  H14   IOSTANDARD LVCMOS15} [get_ports gpio_bd[11]]          ; ## XADC_GPIO_0
+set_property  -dict {PACKAGE_PIN  J15   IOSTANDARD LVCMOS15} [get_ports gpio_bd[12]]          ; ## XADC_GPIO_1
+set_property  -dict {PACKAGE_PIN  J16   IOSTANDARD LVCMOS15} [get_ports gpio_bd[13]]          ; ## XADC_GPIO_2
+set_property  -dict {PACKAGE_PIN  J14   IOSTANDARD LVCMOS15} [get_ports gpio_bd[14]]          ; ## XADC_GPIO_3
+
+# clocks
+
+create_clock -name cpu_clk      -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK0]
+create_clock -name m200_clk     -period  5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK1]
+create_clock -name hdmi_clk     -period  6.73 [get_pins i_system_wrapper/system_i/axi_hdmi_clkgen/clk_0]
+create_clock -name spdif_clk    -period 50.00 [get_pins i_system_wrapper/system_i/sys_audio_clkgen/clk_out1]
+
+set_clock_groups -asynchronous -group {cpu_clk}
+set_clock_groups -asynchronous -group {m200_clk}
+set_clock_groups -asynchronous -group {hdmi_clk}
+set_clock_groups -asynchronous -group {spdif_clk}
+
diff --git a/projects/common/zed/zed_system_bd.tcl b/projects/common/zed/zed_system_bd.tcl
new file mode 100644
index 000000000..7418e143f
--- /dev/null
+++ b/projects/common/zed/zed_system_bd.tcl
@@ -0,0 +1,278 @@
+
+# create board design
+# interface ports
+
+set DDR [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR]
+set FIXED_IO [create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO]
+set IIC_FMC [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 IIC_FMC]
+
+set GPIO_I [create_bd_port -dir I -from 31 -to 0 GPIO_I]
+set GPIO_O [create_bd_port -dir O -from 31 -to 0 GPIO_O]
+set GPIO_T [create_bd_port -dir O -from 31 -to 0 GPIO_T]
+
+# hdmi interface
+
+set hdmi_out_clk    [create_bd_port -dir O hdmi_out_clk]
+set hdmi_hsync      [create_bd_port -dir O hdmi_hsync]
+set hdmi_vsync      [create_bd_port -dir O hdmi_vsync]
+set hdmi_data_e     [create_bd_port -dir O hdmi_data_e]
+set hdmi_data       [create_bd_port -dir O -from 15 -to 0 hdmi_data]
+
+# i2s
+
+set i2s_mclk        [create_bd_port -dir O -type clk i2s_mclk]
+set i2s_bclk        [create_bd_port -dir O i2s_bclk]
+set i2s_lrclk       [create_bd_port -dir O i2s_lrclk]
+set i2s_sdata_out   [create_bd_port -dir O i2s_sdata_out]
+set i2s_sdata_in    [create_bd_port -dir I i2s_sdata_in]
+
+# iic mux
+
+set iic_mux_scl_I   [create_bd_port -dir I -from 1 -to 0 iic_mux_scl_I]
+set iic_mux_scl_O   [create_bd_port -dir O -from 1 -to 0 iic_mux_scl_O]
+set iic_mux_scl_T   [create_bd_port -dir O iic_mux_scl_T]
+set iic_mux_sda_I   [create_bd_port -dir I -from 1 -to 0 iic_mux_sda_I]
+set iic_mux_sda_O   [create_bd_port -dir O -from 1 -to 0 iic_mux_sda_O]
+set iic_mux_sda_T   [create_bd_port -dir O iic_mux_sda_T ]
+
+set otg_vbusoc      [create_bd_port -dir I otg_vbusoc]
+
+# spdif audio
+
+set spdif           [create_bd_port -dir O spdif]
+
+# instance: sys_ps7
+
+set sys_ps7  [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.3 sys_ps7]
+set_property -dict [list CONFIG.PCW_IMPORT_BOARD_PRESET {ZedBoard}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_S_AXI_HP0 {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {32}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_DMA0 {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_DMA1 {1}] $sys_ps7
+set_property -dict [list CONFIG.PCW_USE_DMA2 {1}] $sys_ps7
+
+set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
+set_property -dict [list CONFIG.USE_BOARD_FLOW {true} CONFIG.IIC_BOARD_INTERFACE {IIC_MAIN}] $axi_iic_main
+
+set sys_i2c_mixer [create_bd_cell -type ip -vlnv analog.com:user:util_i2c_mixer:1.0 sys_i2c_mixer]
+
+set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 sys_concat_intc]
+set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc
+
+set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect]
+set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect
+
+set sys_logic_inv [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:1.0 sys_logic_inv]
+set_property -dict [list CONFIG.C_SIZE {1}] $sys_logic_inv
+set_property -dict [list CONFIG.C_OPERATION {not}] $sys_logic_inv
+
+# hdmi peripherals
+
+set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
+set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
+
+set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.1 axi_hdmi_dma]
+set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma
+set_property -dict [list CONFIG.c_use_mm2s_fsync {1}] $axi_hdmi_dma
+set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
+
+set axi_hdmi_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hdmi_interconnect]
+set_property -dict [list CONFIG.NUM_MI {1}] $axi_hdmi_interconnect
+
+# audio peripherals
+
+set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
+set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
+set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
+
+set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
+set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_spdif_tx_core
+set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core
+set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_spdif_tx_core
+set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_spdif_tx_core
+
+set axi_i2s_adi [create_bd_cell -type ip -vlnv analog.com:user:axi_i2s_adi:1.0 axi_i2s_adi]
+set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_i2s_adi
+set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_i2s_adi
+set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_i2s_adi
+set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_i2s_adi
+
+# iic (fmc)
+
+set axi_iic_fmc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_fmc]
+
+# interface connections
+
+connect_bd_intf_net -intf_net sys_ps7_ddr [get_bd_intf_ports DDR] [get_bd_intf_pins sys_ps7/DDR]
+connect_bd_net -net sys_ps7_GPIO_I [get_bd_ports GPIO_I] [get_bd_pins sys_ps7/GPIO_I]
+connect_bd_net -net sys_ps7_GPIO_O [get_bd_ports GPIO_O] [get_bd_pins sys_ps7/GPIO_O]
+connect_bd_net -net sys_ps7_GPIO_T [get_bd_ports GPIO_T] [get_bd_pins sys_ps7/GPIO_T]
+connect_bd_intf_net -intf_net sys_ps7_fixed_io [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins sys_ps7/FIXED_IO]
+
+connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_200m_clk [get_bd_pins sys_ps7/FCLK_CLK1]
+
+connect_bd_net -net sys_100m_resetn [get_bd_pins sys_ps7/FCLK_RESET0_N]
+
+connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/M_AXI_GP0_ACLK]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+
+connect_bd_intf_net -intf_net axi_cpu_interconnect_s00_axi [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] [get_bd_intf_pins sys_ps7/M_AXI_GP0]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/S00_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/S00_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+
+connect_bd_intf_net -intf_net axi_cpu_interconnect_m00_axi [get_bd_intf_pins axi_cpu_interconnect/M00_AXI] [get_bd_intf_pins axi_iic_main/s_axi]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M00_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M00_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_iic_main/s_axi_aclk]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_iic_main/s_axi_aresetn]
+connect_bd_net -net sys_concat_intc_din_1 [get_bd_pins sys_concat_intc/In1] [get_bd_pins axi_iic_main/iic2intc_irpt]
+
+connect_bd_net -net axi_iic_main_scl_i [get_bd_pins axi_iic_main/scl_i] [get_bd_pins sys_i2c_mixer/upstream_scl_O]
+connect_bd_net -net axi_iic_main_scl_o [get_bd_pins axi_iic_main/scl_o] [get_bd_pins sys_i2c_mixer/upstream_scl_I]
+connect_bd_net -net axi_iic_main_scl_t [get_bd_pins axi_iic_main/scl_t] [get_bd_pins sys_i2c_mixer/upstream_scl_T]
+connect_bd_net -net axi_iic_main_sda_i [get_bd_pins axi_iic_main/sda_i] [get_bd_pins sys_i2c_mixer/upstream_sda_O]
+connect_bd_net -net axi_iic_main_sda_o [get_bd_pins axi_iic_main/sda_o] [get_bd_pins sys_i2c_mixer/upstream_sda_I]
+connect_bd_net -net axi_iic_main_sda_t [get_bd_pins axi_iic_main/sda_t] [get_bd_pins sys_i2c_mixer/upstream_sda_T]
+
+connect_bd_net -net sys_i2c_mixer_downstream_scl_i [get_bd_ports iic_mux_scl_I] [get_bd_pins sys_i2c_mixer/downstream_scl_I]
+connect_bd_net -net sys_i2c_mixer_downstream_scl_o [get_bd_ports iic_mux_scl_O] [get_bd_pins sys_i2c_mixer/downstream_scl_O]
+connect_bd_net -net sys_i2c_mixer_downstream_scl_t [get_bd_ports iic_mux_scl_T] [get_bd_pins sys_i2c_mixer/downstream_scl_T]
+connect_bd_net -net sys_i2c_mixer_downstream_sda_i [get_bd_ports iic_mux_sda_I] [get_bd_pins sys_i2c_mixer/downstream_sda_I]
+connect_bd_net -net sys_i2c_mixer_downstream_sda_o [get_bd_ports iic_mux_sda_O] [get_bd_pins sys_i2c_mixer/downstream_sda_O]
+connect_bd_net -net sys_i2c_mixer_downstream_sda_t [get_bd_ports iic_mux_sda_T] [get_bd_pins sys_i2c_mixer/downstream_sda_T]
+
+connect_bd_net -net sys_ps7_interrupt [get_bd_pins sys_concat_intc/dout] [get_bd_pins sys_ps7/IRQ_F2P]
+
+connect_bd_net -net sys_logic_inv_o [get_bd_pins sys_logic_inv/Res] [get_bd_pins sys_ps7/USB0_VBUS_PWRFAULT]
+connect_bd_net -net sys_logic_inv_i [get_bd_pins sys_logic_inv/Op1] [get_bd_ports otg_vbusoc]
+
+# hdmi
+
+connect_bd_net -net sys_200m_clk   [get_bd_pins axi_hdmi_clkgen/clk]
+
+connect_bd_intf_net -intf_net axi_cpu_interconnect_m01_axi [get_bd_intf_pins axi_cpu_interconnect/M01_AXI] [get_bd_intf_pins axi_hdmi_clkgen/s_axi]
+connect_bd_intf_net -intf_net axi_cpu_interconnect_m02_axi [get_bd_intf_pins axi_cpu_interconnect/M02_AXI] [get_bd_intf_pins axi_hdmi_core/s_axi]
+connect_bd_intf_net -intf_net axi_cpu_interconnect_m03_axi [get_bd_intf_pins axi_cpu_interconnect/M03_AXI] [get_bd_intf_pins axi_hdmi_dma/S_AXI_LITE]
+
+connect_bd_intf_net -intf_net axi_hdmi_interconnect_s00_axi [get_bd_intf_pins axi_hdmi_interconnect/S00_AXI] [get_bd_intf_pins axi_hdmi_dma/M_AXI_MM2S]
+connect_bd_intf_net -intf_net axi_hdmi_interconnect_m00_axi [get_bd_intf_pins axi_hdmi_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP0]
+
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M01_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M02_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M03_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_interconnect/ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_interconnect/S00_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_interconnect/M00_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/s_axi_aclk]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/drp_clk]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/s_axi_aclk]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/m_axis_mm2s_clk]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/s_axi_lite_aclk]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axi_mm2s_aclk]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axis_mm2s_aclk]
+connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP0_ACLK]
+
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M01_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M02_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M03_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_interconnect/ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_interconnect/S00_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_interconnect/M00_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_clkgen/s_axi_aresetn]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_core/s_axi_aresetn]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_dma/axi_resetn]
+
+connect_bd_net -net axi_hdmi_tx_core_hdmi_clk      [get_bd_pins axi_hdmi_core/hdmi_clk]              [get_bd_pins axi_hdmi_clkgen/clk_0]
+connect_bd_net -net axi_hdmi_tx_core_hdmi_out_clk  [get_bd_pins axi_hdmi_core/hdmi_out_clk]          [get_bd_ports hdmi_out_clk] 
+connect_bd_net -net axi_hdmi_tx_core_hdmi_hsync    [get_bd_pins axi_hdmi_core/hdmi_16_hsync]         [get_bd_ports hdmi_hsync]   
+connect_bd_net -net axi_hdmi_tx_core_hdmi_vsync    [get_bd_pins axi_hdmi_core/hdmi_16_vsync]         [get_bd_ports hdmi_vsync]   
+connect_bd_net -net axi_hdmi_tx_core_hdmi_data_e   [get_bd_pins axi_hdmi_core/hdmi_16_data_e]        [get_bd_ports hdmi_data_e]  
+connect_bd_net -net axi_hdmi_tx_core_hdmi_data     [get_bd_pins axi_hdmi_core/hdmi_16_data]          [get_bd_ports hdmi_data]    
+connect_bd_net -net axi_hdmi_tx_core_mm2s_tvalid   [get_bd_pins axi_hdmi_core/m_axis_mm2s_tvalid]    [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tvalid]
+connect_bd_net -net axi_hdmi_tx_core_mm2s_tdata    [get_bd_pins axi_hdmi_core/m_axis_mm2s_tdata]     [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tdata] 
+connect_bd_net -net axi_hdmi_tx_core_mm2s_tkeep    [get_bd_pins axi_hdmi_core/m_axis_mm2s_tkeep]     [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tkeep] 
+connect_bd_net -net axi_hdmi_tx_core_mm2s_tlast    [get_bd_pins axi_hdmi_core/m_axis_mm2s_tlast]     [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tlast] 
+connect_bd_net -net axi_hdmi_tx_core_mm2s_tready   [get_bd_pins axi_hdmi_core/m_axis_mm2s_tready]    [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tready]
+connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync    [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync]     [get_bd_pins axi_hdmi_dma/mm2s_fsync]        
+connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync    [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync_ret]
+
+connect_bd_net -net sys_concat_intc_din_0 [get_bd_pins sys_concat_intc/In0] [get_bd_pins axi_hdmi_dma/mm2s_introut] 
+
+# spdif audio
+
+connect_bd_intf_net -intf_net axi_cpu_interconnect_m04_axi [get_bd_intf_pins axi_cpu_interconnect/M04_AXI] [get_bd_intf_pins axi_spdif_tx_core/s_axi]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M04_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/S_AXI_ACLK]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M04_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_core/S_AXI_ARESETN]
+
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/DMA_REQ_ACLK]
+connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/DMA0_ACLK]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_core/DMA_REQ_RSTN]
+connect_bd_intf_net -intf_net axi_spdif_dma_req_tx [get_bd_intf_pins sys_ps7/DMA0_REQ] [get_bd_intf_pins axi_spdif_tx_core/DMA_REQ]
+connect_bd_intf_net -intf_net axi_spdif_dma_ack_tx [get_bd_intf_pins sys_ps7/DMA0_ACK] [get_bd_intf_pins axi_spdif_tx_core/DMA_ACK]
+
+connect_bd_net -net sys_200m_clk [get_bd_pins sys_audio_clkgen/clk_in1]
+connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk]
+connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o]
+
+# i2s audio
+
+connect_bd_intf_net -intf_net axi_cpu_interconnect_m05_axi [get_bd_intf_pins axi_cpu_interconnect/M05_AXI] [get_bd_intf_pins axi_i2s_adi/s_axi]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M05_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_i2s_adi/S_AXI_ACLK] 
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_i2s_adi/DMA_REQ_RX_ACLK] 
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_i2s_adi/DMA_REQ_TX_ACLK] 
+connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/DMA1_ACLK] 
+connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/DMA2_ACLK]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M05_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_i2s_adi/S_AXI_ARESETN] 
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_i2s_adi/DMA_REQ_RX_RSTN] 
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_i2s_adi/DMA_REQ_TX_RSTN] 
+
+connect_bd_net -net sys_audio_clkgen_clk [get_bd_ports i2s_mclk] 
+connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins axi_i2s_adi/DATA_CLK_I]
+
+connect_bd_net -net i2s_bclk_s      [get_bd_ports i2s_bclk]       [get_bd_pins axi_i2s_adi/BCLK_O]
+connect_bd_net -net i2s_lrclk_s     [get_bd_ports i2s_lrclk]      [get_bd_pins axi_i2s_adi/LRCLK_O]
+connect_bd_net -net i2s_sdata_out_s [get_bd_ports i2s_sdata_out]  [get_bd_pins axi_i2s_adi/SDATA_O]
+connect_bd_net -net i2s_sdata_in_s  [get_bd_ports i2s_sdata_in]   [get_bd_pins axi_i2s_adi/SDATA_I]
+
+connect_bd_intf_net -intf_net axi_i2s_adi_dma_req_tx [get_bd_intf_pins sys_ps7/DMA1_REQ] [get_bd_intf_pins axi_i2s_adi/DMA_REQ_TX]
+connect_bd_intf_net -intf_net axi_i2s_adi_dma_ack_tx [get_bd_intf_pins sys_ps7/DMA1_ACK] [get_bd_intf_pins axi_i2s_adi/DMA_ACK_TX]
+connect_bd_intf_net -intf_net axi_i2s_adi_dma_req_rx [get_bd_intf_pins sys_ps7/DMA2_REQ] [get_bd_intf_pins axi_i2s_adi/DMA_REQ_RX]
+connect_bd_intf_net -intf_net axi_i2s_adi_dma_ack_rx [get_bd_intf_pins sys_ps7/DMA2_ACK] [get_bd_intf_pins axi_i2s_adi/DMA_ACK_RX]
+
+# iic (fmc)
+
+connect_bd_intf_net -intf_net axi_cpu_interconnect_m06_axi [get_bd_intf_pins axi_cpu_interconnect/M06_AXI] [get_bd_intf_pins axi_iic_fmc/s_axi]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M06_ACLK] [get_bd_pins sys_ps7/FCLK_CLK0]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_iic_fmc/s_axi_aclk]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M06_ARESETN] [get_bd_pins sys_ps7/FCLK_RESET0_N]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_iic_fmc/s_axi_aresetn]
+
+connect_bd_intf_net -intf_net axi_iic_fmc_iic [get_bd_intf_ports IIC_FMC] [get_bd_intf_pins axi_iic_fmc/iic]
+
+connect_bd_net -net sys_concat_intc_din_4 [get_bd_pins sys_concat_intc/In4] [get_bd_pins axi_iic_fmc/iic2intc_irpt]
+
+# address map
+
+create_bd_addr_seg -range 0x00010000 -offset 0x41600000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_iic_main/s_axi/Reg]             SEG_data_iic_main
+create_bd_addr_seg -range 0x00010000 -offset 0x79000000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite]     SEG_data_hdmi_clkgen
+create_bd_addr_seg -range 0x00010000 -offset 0x43000000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg]        SEG_data_hdmi_dma
+create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite]       SEG_data_hdmi_core
+create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0]       SEG_data_spdif_core
+create_bd_addr_seg -range 0x00010000 -offset 0x77600000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_i2s_adi/S_AXI/reg0]             SEG_data_i2s_adi
+create_bd_addr_seg -range 0x00010000 -offset 0x41620000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_iic_fmc/s_axi/Reg]              SEG_data_iic_fmc
+
+create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S]     [get_bd_addr_segs sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_sys_ps7_hp0_ddr_lowocm
+
diff --git a/projects/common/zed/zed_system_constr.xdc b/projects/common/zed/zed_system_constr.xdc
new file mode 100644
index 000000000..cdabe69ae
--- /dev/null
+++ b/projects/common/zed/zed_system_constr.xdc
@@ -0,0 +1,101 @@
+
+# constraints
+# hdmi 
+
+set_property  -dict {PACKAGE_PIN  W18   IOSTANDARD LVCMOS33} [get_ports hdmi_out_clk]
+set_property  -dict {PACKAGE_PIN  W17   IOSTANDARD LVCMOS33} [get_ports hdmi_vsync]
+set_property  -dict {PACKAGE_PIN  V17   IOSTANDARD LVCMOS33} [get_ports hdmi_hsync]
+set_property  -dict {PACKAGE_PIN  U16   IOSTANDARD LVCMOS33} [get_ports hdmi_data_e]
+set_property  -dict {PACKAGE_PIN  Y13   IOSTANDARD LVCMOS33} [get_ports hdmi_data[0]]
+set_property  -dict {PACKAGE_PIN  AA13  IOSTANDARD LVCMOS33} [get_ports hdmi_data[1]]
+set_property  -dict {PACKAGE_PIN  AA14  IOSTANDARD LVCMOS33} [get_ports hdmi_data[2]]
+set_property  -dict {PACKAGE_PIN  Y14   IOSTANDARD LVCMOS33} [get_ports hdmi_data[3]]
+set_property  -dict {PACKAGE_PIN  AB15  IOSTANDARD LVCMOS33} [get_ports hdmi_data[4]]
+set_property  -dict {PACKAGE_PIN  AB16  IOSTANDARD LVCMOS33} [get_ports hdmi_data[5]]
+set_property  -dict {PACKAGE_PIN  AA16  IOSTANDARD LVCMOS33} [get_ports hdmi_data[6]]
+set_property  -dict {PACKAGE_PIN  AB17  IOSTANDARD LVCMOS33} [get_ports hdmi_data[7]]
+set_property  -dict {PACKAGE_PIN  AA17  IOSTANDARD LVCMOS33} [get_ports hdmi_data[8]]
+set_property  -dict {PACKAGE_PIN  Y15   IOSTANDARD LVCMOS33} [get_ports hdmi_data[9]]
+set_property  -dict {PACKAGE_PIN  W13   IOSTANDARD LVCMOS33} [get_ports hdmi_data[10]]
+set_property  -dict {PACKAGE_PIN  W15   IOSTANDARD LVCMOS33} [get_ports hdmi_data[11]]
+set_property  -dict {PACKAGE_PIN  V15   IOSTANDARD LVCMOS33} [get_ports hdmi_data[12]]
+set_property  -dict {PACKAGE_PIN  U17   IOSTANDARD LVCMOS33} [get_ports hdmi_data[13]]
+set_property  -dict {PACKAGE_PIN  V14   IOSTANDARD LVCMOS33} [get_ports hdmi_data[14]]
+set_property  -dict {PACKAGE_PIN  V13   IOSTANDARD LVCMOS33} [get_ports hdmi_data[15]]
+
+# spdif
+
+set_property  -dict {PACKAGE_PIN  U15   IOSTANDARD LVCMOS33} [get_ports spdif]
+
+# i2s
+
+set_property  -dict {PACKAGE_PIN  AB2   IOSTANDARD LVCMOS33} [get_ports i2s_mclk]
+set_property  -dict {PACKAGE_PIN  AA6   IOSTANDARD LVCMOS33} [get_ports i2s_bclk]
+set_property  -dict {PACKAGE_PIN  Y6    IOSTANDARD LVCMOS33} [get_ports i2s_lrclk]
+set_property  -dict {PACKAGE_PIN  Y8    IOSTANDARD LVCMOS33} [get_ports i2s_sdata_out]
+set_property  -dict {PACKAGE_PIN  AA7   IOSTANDARD LVCMOS33} [get_ports i2s_sdata_in]
+
+# iic
+
+set_property  -dict {PACKAGE_PIN  R7    IOSTANDARD LVCMOS33} [get_ports iic_scl]
+set_property  -dict {PACKAGE_PIN  U7    IOSTANDARD LVCMOS33} [get_ports iic_sda]
+set_property  -dict {PACKAGE_PIN  AA18  IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_scl[1]]
+set_property  -dict {PACKAGE_PIN  Y16   IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_sda[1]]
+set_property  -dict {PACKAGE_PIN  AB4   IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_scl[0]]
+set_property  -dict {PACKAGE_PIN  AB5   IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_sda[0]]
+
+# otg
+
+set_property  -dict {PACKAGE_PIN  L16   IOSTANDARD LVCMOS25} [get_ports otg_vbusoc]
+
+# gpio (switches, leds and such)
+
+set_property  -dict {PACKAGE_PIN  P16   IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]]       ; ## BTNC
+set_property  -dict {PACKAGE_PIN  R16   IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]]       ; ## BTND
+set_property  -dict {PACKAGE_PIN  N15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]]       ; ## BTNL
+set_property  -dict {PACKAGE_PIN  R18   IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]]       ; ## BTNR
+set_property  -dict {PACKAGE_PIN  T18   IOSTANDARD LVCMOS25} [get_ports gpio_bd[4]]       ; ## BTNU
+set_property  -dict {PACKAGE_PIN  U10   IOSTANDARD LVCMOS33} [get_ports gpio_bd[5]]       ; ## OLED-DC
+set_property  -dict {PACKAGE_PIN  U9    IOSTANDARD LVCMOS33} [get_ports gpio_bd[6]]       ; ## OLED-RES
+set_property  -dict {PACKAGE_PIN  AB12  IOSTANDARD LVCMOS33} [get_ports gpio_bd[7]]       ; ## OLED-SCLK
+set_property  -dict {PACKAGE_PIN  AA12  IOSTANDARD LVCMOS33} [get_ports gpio_bd[8]]       ; ## OLED-SDIN
+set_property  -dict {PACKAGE_PIN  U11   IOSTANDARD LVCMOS33} [get_ports gpio_bd[9]]       ; ## OLED-VBAT
+set_property  -dict {PACKAGE_PIN  U12   IOSTANDARD LVCMOS33} [get_ports gpio_bd[10]]      ; ## OLED-VDD
+
+set_property  -dict {PACKAGE_PIN  F22   IOSTANDARD LVCMOS25} [get_ports gpio_bd[11]]      ; ## SW0
+set_property  -dict {PACKAGE_PIN  G22   IOSTANDARD LVCMOS25} [get_ports gpio_bd[12]]      ; ## SW1
+set_property  -dict {PACKAGE_PIN  H22   IOSTANDARD LVCMOS25} [get_ports gpio_bd[13]]      ; ## SW2
+set_property  -dict {PACKAGE_PIN  F21   IOSTANDARD LVCMOS25} [get_ports gpio_bd[14]]      ; ## SW3
+set_property  -dict {PACKAGE_PIN  H19   IOSTANDARD LVCMOS25} [get_ports gpio_bd[15]]      ; ## SW4
+set_property  -dict {PACKAGE_PIN  H18   IOSTANDARD LVCMOS25} [get_ports gpio_bd[16]]      ; ## SW5
+set_property  -dict {PACKAGE_PIN  H17   IOSTANDARD LVCMOS25} [get_ports gpio_bd[17]]      ; ## SW6
+set_property  -dict {PACKAGE_PIN  M15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[18]]      ; ## SW7
+
+set_property  -dict {PACKAGE_PIN  T22   IOSTANDARD LVCMOS33} [get_ports gpio_bd[19]]      ; ## LD0
+set_property  -dict {PACKAGE_PIN  T21   IOSTANDARD LVCMOS33} [get_ports gpio_bd[20]]      ; ## LD1
+set_property  -dict {PACKAGE_PIN  U22   IOSTANDARD LVCMOS33} [get_ports gpio_bd[21]]      ; ## LD2
+set_property  -dict {PACKAGE_PIN  U21   IOSTANDARD LVCMOS33} [get_ports gpio_bd[22]]      ; ## LD3
+set_property  -dict {PACKAGE_PIN  V22   IOSTANDARD LVCMOS33} [get_ports gpio_bd[23]]      ; ## LD4
+set_property  -dict {PACKAGE_PIN  W22   IOSTANDARD LVCMOS33} [get_ports gpio_bd[24]]      ; ## LD5
+set_property  -dict {PACKAGE_PIN  U19   IOSTANDARD LVCMOS33} [get_ports gpio_bd[25]]      ; ## LD6
+set_property  -dict {PACKAGE_PIN  U14   IOSTANDARD LVCMOS33} [get_ports gpio_bd[26]]      ; ## LD7
+
+set_property  -dict {PACKAGE_PIN  H15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[27]]      ; ## XADC-GIO0
+set_property  -dict {PACKAGE_PIN  R15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[28]]      ; ## XADC-GIO1
+set_property  -dict {PACKAGE_PIN  K15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[29]]      ; ## XADC-GIO2
+set_property  -dict {PACKAGE_PIN  J15   IOSTANDARD LVCMOS25} [get_ports gpio_bd[30]]      ; ## XADC-GIO3
+
+set_property  -dict {PACKAGE_PIN  G17   IOSTANDARD LVCMOS25} [get_ports gpio_bd[31]]      ; ## OTG-RESETN
+
+# clocks
+
+create_clock -name cpu_clk      -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK0]
+create_clock -name m200_clk     -period  5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK1]
+create_clock -name hdmi_clk     -period  6.73 [get_pins i_system_wrapper/system_i/axi_hdmi_clkgen/clk_0]
+create_clock -name spdif_clk    -period 50.00 [get_pins i_system_wrapper/system_i/sys_audio_clkgen/clk_out1]
+
+set_clock_groups -asynchronous -group {cpu_clk}
+set_clock_groups -asynchronous -group {m200_clk}
+set_clock_groups -asynchronous -group {hdmi_clk}
+set_clock_groups -asynchronous -group {spdif_clk}
+
diff --git a/projects/scripts/adi_env.tcl b/projects/scripts/adi_env.tcl
new file mode 100644
index 000000000..ed79b8dd0
--- /dev/null
+++ b/projects/scripts/adi_env.tcl
@@ -0,0 +1,14 @@
+
+# environment related stuff
+
+set ad_hdl_dir  ".."
+set ad_phdl_dir ".."
+
+if [info exists ::env(ADI_HDL_DIR)] {
+  set ad_hdl_dir $::env(ADI_HDL_DIR)
+}
+
+if [info exists ::env(ADI_PHDL_DIR)] {
+  set ad_phdl_dir $::env(ADI_PHDL_DIR)
+}
+
diff --git a/projects/scripts/adi_project.tcl b/projects/scripts/adi_project.tcl
new file mode 100644
index 000000000..7cb7fccfe
--- /dev/null
+++ b/projects/scripts/adi_project.tcl
@@ -0,0 +1,79 @@
+
+
+proc adi_project_create {project_name} {
+
+  set project_part "none"
+  set project_board "none"
+
+  if [regexp "_ac701$" $project_name] {
+    set project_part "xc7a200tfbg676-2"
+    set project_board "xilinx.com:artix7:ac701:1.0"
+  }
+  if [regexp "_kc705$" $project_name] {
+    set project_part "xc7k325tffg900-2"
+    set project_board "xilinx.com:kintex7:kc705:1.1"
+  }
+  if [regexp "_vc707$" $project_name] {
+    set project_part "xc7vx485tffg1761-2"
+    set project_board "xilinx.com:virtex7:vc707:1.1"
+  }
+  if [regexp "_zed$" $project_name] {
+    set project_part "xc7z020clg484-1"
+    set project_board "em.avnet.com:zynq:zed:d"
+  }
+  if [regexp "_zc702$" $project_name] {
+    set project_part "xc7z020clg484-1"
+    set project_board "xilinx.com:zynq:zc702:1.0"
+  }
+  if [regexp "_zc706$" $project_name] {
+    set project_part "xc7z045ffg900-2"
+    set project_board "xilinx.com:zynq:zc706:1.1"
+  }
+
+  set project_system_dir "./$project_name.srcs/sources_1/bd/system"
+
+  create_project $project_name . -part $project_part -force
+  set_property board $project_board [current_project]
+  set_property ip_repo_paths ../../../library [current_fileset]
+  update_ip_catalog
+
+  create_bd_design "system"
+  source system_bd.tcl
+
+  generate_target {synthesis implementation} [get_files  $project_system_dir/system.bd]
+  make_wrapper -files [get_files $project_system_dir/system.bd] -top
+  import_files -force -norecurse -fileset sources_1 $project_system_dir/hdl/system_wrapper.v
+}
+
+proc adi_project_files {project_name project_files} {
+
+  add_files -norecurse -fileset sources_1 $project_files
+  set_property top system_top [current_fileset]
+}
+
+proc adi_project_run {project_name} {
+
+  set project_system_dir "./$project_name.srcs/sources_1/bd/system"
+
+  launch_runs synth_1
+  wait_on_run synth_1
+  open_run synth_1
+  report_timing_summary -file timing_synth.log
+
+  launch_runs impl_1 -to_step write_bitstream
+  wait_on_run impl_1
+  open_run impl_1
+  report_timing_summary -file timing_impl.log
+
+  #get_property STATS.THS [get_runs impl_1]
+  #get_property STATS.TNS [get_runs impl_1]
+  #get_property STATS.TPWS [get_runs impl_1]
+
+  if [expr [get_property SLACK [get_timing_paths]] < 0] {
+    puts "ERROR: Timing Constraints NOT met."
+    use_this_invalid_command_to_crash
+  }
+
+  export_hardware [get_files $project_system_dir/system.bd] [get_runs impl_1] -bitstream
+}
+