jesd204: Intel: NP12 support
Dual clock mode is introduced in link layer to support different datapath widths on the transport layer than on physical layer. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - Device clock : Link clock * input data path width / output datapath width Supports four clock configurations, single or dual clock mode with or without external device clock. The configuration interface reflects the dual clock domain.main
Laszlo Nagy
Laszlo Nagy
parent
6fe6864447
commit
dd58759cd8
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@ -135,6 +135,12 @@ ad_ip_parameter EXT_DEVICE_CLK_EN BOOLEAN 0 false { \
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DISPLAY_NAME "External Device Clock Enable" \
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}
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ad_ip_parameter TPL_DATA_PATH_WIDTH INTEGER 4 false { \
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DISPLAY_NAME "Transport layer datapath width" \
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DISPLAY_UNITS "octets" \
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ALLOWED_RANGES {4 6 8 12} \
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}
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proc create_phy_reset_control {tx num_of_lanes sysclk_frequency} {
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global version
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@ -348,9 +354,13 @@ proc jesd204_compose {} {
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set ext_device_clk_en [get_parameter_value "EXT_DEVICE_CLK_EN"]
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set bonding_clocks_en [get_parameter_value "BONDING_CLOCKS_EN"]
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set input_pipeline [get_parameter_value "INPUT_PIPELINE_STAGES"]
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set tpl_data_path_width [get_parameter_value "TPL_DATA_PATH_WIDTH"]
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set pllclk_frequency [expr $lane_rate / 2]
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set linkclk_frequency [expr $lane_rate / 40]
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set deviceclk_frequency [expr $linkclk_frequency * 4 / $tpl_data_path_width]
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set dual_clk_mode [expr $tpl_data_path_width > 4]
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if {![jesd204_validate true]} {
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return
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@ -366,6 +376,7 @@ proc jesd204_compose {} {
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add_instance ref_clock altera_clock_bridge $version
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set_instance_parameter_value ref_clock {EXPLICIT_CLOCK_RATE} [expr $refclk_frequency*1000000]
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set_instance_parameter_value ref_clock {NUM_CLOCK_OUTPUTS} 2
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add_interface ref_clk clock sink
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set_interface_property ref_clk EXPORT_OF ref_clock.in_clk
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@ -381,6 +392,28 @@ proc jesd204_compose {} {
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add_instance link_reset altera_reset_bridge $version
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set_instance_parameter_value link_reset {NUM_RESET_OUTPUTS} 2
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if {$dual_clk_mode} {
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if {$ext_device_clk_en} {
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set link_clock link_clock.out_clk
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set device_clock ext_device_clock.out_clk
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set device_clock_export ext_device_clock.out_clk_1
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} else {
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set link_clock link_clock.out_clk
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set device_clock ref_clock.out_clk
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set device_clock_export ref_clock.out_clk_1
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}
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} else {
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if {$ext_device_clk_en} {
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set link_clock ext_device_clock.out_clk
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set device_clock ext_device_clock.out_clk
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set device_clock_export ext_device_clock.out_clk_1
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} else {
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set link_clock link_clock.out_clk
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set device_clock link_clock.out_clk
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set device_clock_export link_clock.out_clk_1
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}
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}
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if {$device_family == "Arria 10"} {
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add_instance link_pll altera_xcvr_fpll_a10 $version
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@ -477,10 +510,8 @@ proc jesd204_compose {} {
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set_instance_parameter_value phy NUM_OF_LANES $num_of_lanes
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set_instance_parameter_value phy REGISTER_INPUTS $input_pipeline
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set_instance_parameter_value phy LANE_INVERT $lane_invert
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set_instance_parameter_value phy EXT_DEVICE_CLK_EN $ext_device_clk_en
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set_instance_parameter_value phy BONDING_CLOCKS_EN $bonding_clocks_en
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add_connection link_clock.out_clk_1 phy.link_clk
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add_connection link_reset.out_reset phy.link_reset
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add_connection sys_clock.clk phy.reconfig_clk
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add_connection sys_clock.clk_reset phy.reconfig_reset
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@ -489,22 +520,20 @@ proc jesd204_compose {} {
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if {$ext_device_clk_en} {
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add_instance ext_device_clock altera_clock_bridge $version
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set_instance_parameter_value ext_device_clock {EXPLICIT_CLOCK_RATE} [expr $linkclk_frequency*1000000]
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set_instance_parameter_value ext_device_clock {EXPLICIT_CLOCK_RATE} [expr $deviceclk_frequency*1000000]
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set_instance_parameter_value ext_device_clock {NUM_CLOCK_OUTPUTS} 2
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add_interface device_clk clock sink
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set_interface_property device_clk EXPORT_OF ext_device_clock.in_clk
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add_connection ext_device_clock.out_clk phy.device_clk
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set_interface_property link_clk EXPORT_OF ext_device_clock.out_clk_1
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} else {
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set_interface_property link_clk EXPORT_OF link_clock.out_clk
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}
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add_connection $link_clock phy.link_clk
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set_interface_property link_clk EXPORT_OF $device_clock_export
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set phy_reset_intfs_s10 {analogreset_stat digitalreset_stat}
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if {$tx_or_rx_n} {
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set tx_rx "tx"
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set data_direction sink
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set jesd204_intfs {config control ilas_config event status}
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set jesd204_intfs {config device_config control ilas_config device_event status}
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set phy_reset_intfs {analogreset digitalreset cal_busy}
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create_lane_pll $id $tx_or_rx_n $pllclk_frequency $refclk_frequency $num_of_lanes $bonding_clocks_en
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@ -521,7 +550,7 @@ proc jesd204_compose {} {
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} else {
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set tx_rx "rx"
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set data_direction source
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set jesd204_intfs {config ilas_config event status}
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set jesd204_intfs {config device_config ilas_config device_event status}
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set phy_reset_intfs {analogreset digitalreset cal_busy is_lockedtodata}
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add_connection ref_clock.out_clk phy.ref_clk
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@ -535,17 +564,17 @@ proc jesd204_compose {} {
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add_instance jesd204_${tx_rx} jesd204_${tx_rx} 1.0
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set_instance_parameter_value jesd204_${tx_rx} {NUM_LANES} $num_of_lanes
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set_instance_parameter_value jesd204_${tx_rx} {ASYNC_CLK} $dual_clk_mode
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set_instance_parameter_value jesd204_${tx_rx} {TPL_DATA_PATH_WIDTH} $tpl_data_path_width
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if {$ext_device_clk_en} {
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add_connection ext_device_clock.out_clk axi_jesd204_${tx_rx}.core_clock
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add_connection ext_device_clock.out_clk jesd204_${tx_rx}.clock
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} else {
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add_connection link_clock.out_clk_1 axi_jesd204_${tx_rx}.core_clock
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add_connection link_clock.out_clk_1 jesd204_${tx_rx}.clock
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}
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add_connection $link_clock axi_jesd204_${tx_rx}.core_clock
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add_connection $device_clock axi_jesd204_${tx_rx}.device_clock
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add_connection $link_clock jesd204_${tx_rx}.clock
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add_connection $device_clock jesd204_${tx_rx}.device_clock
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add_connection link_reset.out_reset axi_jesd204_${tx_rx}.core_reset_ext
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add_connection axi_jesd204_${tx_rx}.core_reset jesd204_${tx_rx}.reset
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add_connection axi_jesd204_${tx_rx}.device_reset jesd204_${tx_rx}.device_reset
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foreach intf $jesd204_intfs {
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add_connection axi_jesd204_${tx_rx}.${intf} jesd204_${tx_rx}.${intf}
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@ -61,6 +61,10 @@ set_false_path \
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-from [get_registers {*|jesd204_up_common:i_up_common|up_reset_core}] \
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-to [get_registers {*|jesd204_up_common:i_up_common|core_reset_vector[*]}]
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set_false_path \
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-from [get_registers {*|jesd204_up_common:i_up_common|up_reset_core}] \
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-to [get_registers {*|jesd204_up_common:i_up_common|device_reset_vector[*]}]
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set_false_path \
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-from [get_registers {*|jesd204_up_common:i_up_common|core_reset_vector[0]}] \
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-to [get_registers {*|jesd204_up_common:i_up_common|up_reset_synchronizer_vector[*]}]
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@ -72,10 +76,18 @@ set_false_path \
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-from [get_registers {*|jesd204_up_common:i_up_common|up_cfg_*}] \
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-to [get_registers {*|jesd204_up_common:i_up_common|core_cfg_*}]
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set_false_path \
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-from [get_registers {*|jesd204_up_common:i_up_common|up_cfg_*}] \
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-to [get_registers {*|jesd204_up_common:i_up_common|device_cfg_*}]
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set_false_path \
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-from [get_registers {*|jesd204_up_rx:i_up_rx|up_cfg_*}] \
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-to [get_registers {*|jesd204_up_common:i_up_common|core_extra_cfg[*]}]
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set_false_path \
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-from [get_registers {*|jesd204_up_rx:i_up_rx|up_cfg_*}] \
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-to [get_registers {*|jesd204_up_common:i_up_common|device_extra_cfg[*]}]
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set_false_path \
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-from [get_registers {*|jesd204_up_sysref:i_up_sysref|up_cfg_*}] \
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-to [get_registers {*|jesd204_up_common:i_up_common|core_extra_cfg[*]}]
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-to [get_registers {*|jesd204_up_common:i_up_common|device_extra_cfg[*]}]
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@ -103,6 +103,11 @@ add_interface_port interrupt irq irq Output 1
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add_interface core_clock clock end
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add_interface_port core_clock core_clk clk Input 1
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# device clock
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add_interface device_clock clock end
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add_interface_port device_clock device_clk clk Input 1
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# core reset ext
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add_interface core_reset_ext reset end
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@ -116,27 +121,44 @@ set_interface_property core_reset associatedClock core_clock
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set_interface_property core_reset associatedResetSinks core_reset_ext
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add_interface_port core_reset core_reset reset Output 1
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# config interface
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# device reset
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add_interface device_reset reset start
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set_interface_property device_reset associatedClock device_clock
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set_interface_property device_reset associatedResetSinks core_reset_ext
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add_interface_port device_reset device_reset reset Output 1
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# link clock domain config interface
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add_interface config conduit end
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set_interface_property config associatedClock core_clock
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set_interface_property config associatedReset core_reset
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add_interface_port config core_cfg_octets_per_multiframe octets_per_multiframe Output 10
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add_interface_port config core_cfg_buffer_delay buffer_delay Output 8
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add_interface_port config core_cfg_buffer_early_release buffer_early_release Output 1
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add_interface_port config core_cfg_disable_char_replacement disable_char_replacement Output 1
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add_interface_port config core_cfg_disable_scrambler disable_scrambler Output 1
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add_interface_port config core_cfg_lanes_disable lanes_disable Output NUM_LANES
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add_interface_port config core_cfg_links_disable links_disable Output NUM_LINKS
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add_interface_port config core_cfg_lmfc_offset lmfc_offset Output 8
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add_interface_port config core_cfg_octets_per_multiframe octets_per_multiframe Output 10
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add_interface_port config core_cfg_octets_per_frame octets_per_frame Output 8
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add_interface_port config core_cfg_sysref_disable sysref_disable Output 1
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add_interface_port config core_cfg_sysref_oneshot sysref_oneshot Output 1
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add_interface_port config core_cfg_disable_scrambler disable_scrambler Output 1
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add_interface_port config core_cfg_disable_char_replacement disable_char_replacement Output 1
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add_interface_port config core_cfg_frame_align_err_threshold frame_align_err_threshold Output 8
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add_interface_port config core_ctrl_err_statistics_reset err_statistics_reset Output 1
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add_interface_port config core_ctrl_err_statistics_mask err_statistics_mask Output 3
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# device clock domain config interface
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add_interface device_config conduit end
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set_interface_property device_config associatedClock device_clock
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set_interface_property device_config associatedReset device_reset
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add_interface_port device_config device_cfg_octets_per_multiframe octets_per_multiframe Output 10
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add_interface_port device_config device_cfg_octets_per_frame octets_per_frame Output 8
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add_interface_port device_config device_cfg_beats_per_multiframe beats_per_multiframe Output 8
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add_interface_port device_config device_cfg_lmfc_offset lmfc_offset Output 8
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add_interface_port device_config device_cfg_sysref_disable sysref_disable Output 1
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add_interface_port device_config device_cfg_sysref_oneshot sysref_oneshot Output 1
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add_interface_port device_config device_cfg_buffer_delay buffer_delay Output 8
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add_interface_port device_config device_cfg_buffer_early_release buffer_early_release Output 1
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# status interface
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add_interface status conduit end
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@ -149,15 +171,18 @@ add_interface_port status core_status_lane_ifs_ready lane_ifs_ready Input NUM_LA
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add_interface_port status core_status_lane_latency lane_latency Input 14*NUM_LANES
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add_interface_port status core_status_lane_frame_align_err_cnt lane_frame_align_err_cnt Input 8*NUM_LANES
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add_interface_port status core_status_err_statistics_cnt err_statistics_cnt Input 32*NUM_LANES
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add_interface_port status status_synth_params0 synth_params0 Input 32
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add_interface_port status status_synth_params1 synth_params1 Input 32
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add_interface_port status status_synth_params2 synth_params2 Input 32
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# event interface
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add_interface event conduit end
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set_interface_property event associatedClock core_clock
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set_interface_property event associatedReset core_reset
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add_interface device_event conduit end
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set_interface_property device_event associatedClock device_clock
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set_interface_property device_event associatedReset device_reset
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add_interface_port event core_event_sysref_alignment_error sysref_alignment_error Input 1
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add_interface_port event core_event_sysref_edge sysref_edge Input 1
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add_interface_port device_event device_event_sysref_alignment_error sysref_alignment_error Input 1
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add_interface_port device_event device_event_sysref_edge sysref_edge Input 1
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# ilas_config
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@ -55,6 +55,10 @@ set_false_path \
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-from [get_registers {*|jesd204_up_common:i_up_common|up_reset_core}] \
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-to [get_registers {*|jesd204_up_common:i_up_common|core_reset_vector[*]}]
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set_false_path \
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-from [get_registers {*|jesd204_up_common:i_up_common|up_reset_core}] \
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-to [get_registers {*|jesd204_up_common:i_up_common|device_reset_vector[*]}]
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set_false_path \
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-from [get_registers {*|jesd204_up_common:i_up_common|core_reset_vector[0]}] \
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-to [get_registers {*|jesd204_up_common:i_up_common|up_reset_synchronizer_vector[*]}]
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@ -66,6 +70,10 @@ set_false_path \
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-from [get_registers {*|jesd204_up_common:i_up_common|up_cfg_*}] \
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-to [get_registers {*|jesd204_up_common:i_up_common|core_cfg_*}]
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set_false_path \
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-from [get_registers {*|jesd204_up_common:i_up_common|up_cfg_*}] \
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-to [get_registers {*|jesd204_up_common:i_up_common|device_cfg_*}]
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set_false_path \
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-from [get_registers {*|jesd204_up_tx:i_up_tx|up_cfg_ilas_data_*}] \
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-to [get_registers {*|jesd204_up_tx:i_up_tx|core_ilas_config_data[*]}]
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@ -74,6 +82,10 @@ set_false_path \
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-from [get_registers {*|jesd204_up_tx:i_up_tx|up_cfg_*}] \
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-to [get_registers {*|jesd204_up_common:i_up_common|core_extra_cfg[*]}]
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set_false_path \
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-from [get_registers {*|jesd204_up_tx:i_up_tx|up_cfg_*}] \
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-to [get_registers {*|jesd204_up_common:i_up_common|device_extra_cfg[*]}]
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set_false_path \
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-from [get_registers {*|jesd204_up_sysref:i_up_sysref|up_cfg_*}] \
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-to [get_registers {*|jesd204_up_common:i_up_common|core_extra_cfg[*]}]
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-to [get_registers {*|jesd204_up_common:i_up_common|device_extra_cfg[*]}]
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@ -101,6 +101,11 @@ add_interface_port interrupt irq irq Output 1
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add_interface core_clock clock end
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add_interface_port core_clock core_clk clk Input 1
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# device clock
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add_interface device_clock clock end
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add_interface_port device_clock device_clk clk Input 1
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# core reset ext
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add_interface core_reset_ext reset end
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@ -114,8 +119,15 @@ set_interface_property core_reset associatedClock core_clock
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set_interface_property core_reset associatedResetSinks core_reset_ext
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add_interface_port core_reset core_reset reset Output 1
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# config interface
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# device reset
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add_interface device_reset reset start
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set_interface_property device_reset associatedClock device_clock
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set_interface_property device_reset associatedResetSinks core_reset_ext
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add_interface_port device_reset device_reset reset Output 1
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# config interface
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#
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add_interface config conduit end
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set_interface_property config associatedClock core_clock
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set_interface_property config associatedReset core_reset
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@ -127,12 +139,22 @@ add_interface_port config core_cfg_disable_char_replacement disable_char_replace
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add_interface_port config core_cfg_disable_scrambler disable_scrambler Output 1
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add_interface_port config core_cfg_lanes_disable lanes_disable Output NUM_LANES
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add_interface_port config core_cfg_links_disable links_disable Output NUM_LINKS
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add_interface_port config core_cfg_lmfc_offset lmfc_offset Output 8
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add_interface_port config core_cfg_mframes_per_ilas mframes_per_ilas Output 8
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add_interface_port config core_cfg_octets_per_frame octets_per_frame Output 8
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add_interface_port config core_cfg_skip_ilas skip_ilas Output 1
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add_interface_port config core_cfg_sysref_disable sysref_disable Output 1
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add_interface_port config core_cfg_sysref_oneshot sysref_oneshot Output 1
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# device clock domain config interface
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add_interface device_config conduit end
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set_interface_property device_config associatedClock device_clock
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set_interface_property device_config associatedReset device_reset
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add_interface_port device_config device_cfg_octets_per_multiframe octets_per_multiframe Output 10
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add_interface_port device_config device_cfg_octets_per_frame octets_per_frame Output 8
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add_interface_port device_config device_cfg_beats_per_multiframe beats_per_multiframe Output 8
|
||||
add_interface_port device_config device_cfg_lmfc_offset lmfc_offset Output 8
|
||||
add_interface_port device_config device_cfg_sysref_disable sysref_disable Output 1
|
||||
add_interface_port device_config device_cfg_sysref_oneshot sysref_oneshot Output 1
|
||||
|
||||
# control interface
|
||||
|
||||
|
|
@ -154,12 +176,12 @@ add_interface_port ilas_config core_ilas_config_rd rd Input 1
|
|||
|
||||
# event interface
|
||||
|
||||
add_interface event conduit end
|
||||
set_interface_property event associatedClock core_clock
|
||||
set_interface_property event associatedReset core_reset
|
||||
add_interface device_event conduit end
|
||||
set_interface_property device_event associatedClock device_clock
|
||||
set_interface_property device_event associatedReset device_reset
|
||||
|
||||
add_interface_port event core_event_sysref_alignment_error sysref_alignment_error Input 1
|
||||
add_interface_port event core_event_sysref_edge sysref_edge Input 1
|
||||
add_interface_port device_event device_event_sysref_alignment_error sysref_alignment_error Input 1
|
||||
add_interface_port device_event device_event_sysref_edge sysref_edge Input 1
|
||||
|
||||
# status interface
|
||||
|
||||
|
|
@ -169,3 +191,6 @@ set_interface_property status associatedReset core_reset
|
|||
|
||||
add_interface_port status core_status_state state Input 2
|
||||
add_interface_port status core_status_sync sync Input 1
|
||||
add_interface_port status status_synth_params0 synth_params0 Input 32
|
||||
add_interface_port status status_synth_params1 synth_params1 Input 32
|
||||
add_interface_port status status_synth_params2 synth_params2 Input 32
|
||||
|
|
|
|||
|
|
@ -42,6 +42,13 @@
|
|||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
|
||||
set script_dir [file dirname [info script]]
|
||||
|
||||
source "$script_dir/util_cdc_constr.tcl"
|
||||
|
||||
# SYNC~ is a asynchronous interface
|
||||
set_false_path \
|
||||
-from [get_registers *|jesd204_rx_ctrl:i_rx_ctrl|sync_n[0]]
|
||||
|
||||
util_cdc_sync_bits_constr {*|sync_bits:i_all_buffer_ready_cdc}
|
||||
util_cdc_sync_event_constr {*|sync_event:i_sync_lmfc}
|
||||
|
|
|
|||
|
|
@ -66,9 +66,15 @@ ad_ip_files jesd204_rx [list \
|
|||
jesd204_rx_constr.sdc \
|
||||
../jesd204_common/jesd204_eof_generator.v \
|
||||
../jesd204_common/jesd204_frame_mark.v \
|
||||
../jesd204_common/jesd204_frame_align_replace.v \
|
||||
../jesd204_common/jesd204_lmfc.v \
|
||||
../jesd204_common/jesd204_scrambler.v \
|
||||
../jesd204_common/pipeline_stage.v \
|
||||
$ad_hdl_dir/library/util_cdc/sync_bits.v \
|
||||
$ad_hdl_dir/library/util_cdc/sync_data.v \
|
||||
$ad_hdl_dir/library/util_cdc/sync_event.v \
|
||||
$ad_hdl_dir/library/util_cdc/util_cdc_constr.tcl \
|
||||
../../common/ad_pack.v \
|
||||
]
|
||||
|
||||
# parameters
|
||||
|
|
@ -88,16 +94,26 @@ set_parameter_property NUM_INPUT_PIPELINE DISPLAY_NAME "Number of input pipeline
|
|||
set_parameter_property NUM_INPUT_PIPELINE ALLOWED_RANGES 1:3
|
||||
set_parameter_property NUM_INPUT_PIPELINE HDL_PARAMETER true
|
||||
|
||||
add_parameter ASYNC_CLK BOOLEAN false
|
||||
set_parameter_property ASYNC_CLK DISPLAY_NAME "Link and device clock asynchronous"
|
||||
set_parameter_property ASYNC_CLK HDL_PARAMETER true
|
||||
|
||||
ad_ip_parameter TPL_DATA_PATH_WIDTH INTEGER 4 true { \
|
||||
DISPLAY_NAME "Transport layer datapath width" \
|
||||
DISPLAY_UNITS "octets" \
|
||||
ALLOWED_RANGES {4 6 8 12} \
|
||||
}
|
||||
|
||||
#ad_ip_parameter PORT_ENABLE_RX_EOF BOOLEAN false false
|
||||
#ad_ip_parameter PORT_ENABLE_LMFC_CLK BOOLEAN false false
|
||||
#ad_ip_parameter PORT_ENABLE_LMFC_EDGE BOOLEAN false false
|
||||
|
||||
# clock
|
||||
# link clock
|
||||
|
||||
add_interface clock clock end
|
||||
add_interface_port clock clk clk Input 1
|
||||
|
||||
# reset
|
||||
# link clock reset
|
||||
|
||||
add_interface reset reset end
|
||||
set_interface_property reset associatedClock clock
|
||||
|
|
@ -105,11 +121,24 @@ set_interface_property reset synchronousEdges DEASSERT
|
|||
|
||||
add_interface_port reset reset reset Input 1
|
||||
|
||||
# device clock
|
||||
|
||||
add_interface device_clock clock end
|
||||
add_interface_port device_clock device_clk clk Input 1
|
||||
|
||||
# device clock reset
|
||||
|
||||
add_interface device_reset reset end
|
||||
set_interface_property device_reset associatedClock device_clock
|
||||
set_interface_property device_reset synchronousEdges DEASSERT
|
||||
|
||||
add_interface_port device_reset device_reset reset Input 1
|
||||
|
||||
# SYSREF~ interface
|
||||
|
||||
add_interface sysref conduit end
|
||||
set_interface_property sysref associatedClock clock
|
||||
set_interface_property sysref associatedReset reset
|
||||
set_interface_property sysref associatedClock device_clock
|
||||
set_interface_property sysref associatedReset device_reset
|
||||
add_interface_port sysref sysref export Input 1
|
||||
|
||||
# SYNC interface
|
||||
|
|
@ -119,27 +148,37 @@ set_interface_property sync associatedClock clock
|
|||
set_interface_property sync associatedReset reset
|
||||
add_interface_port sync sync export Output NUM_LINKS
|
||||
|
||||
# config interface
|
||||
# link clock domain config interface
|
||||
|
||||
add_interface config conduit end
|
||||
set_interface_property config associatedClock clock
|
||||
set_interface_property config associatedReset reset
|
||||
|
||||
add_interface_port config cfg_octets_per_multiframe octets_per_multiframe Input 10
|
||||
add_interface_port config cfg_buffer_delay buffer_delay Input 8
|
||||
add_interface_port config cfg_buffer_early_release buffer_early_release Input 1
|
||||
add_interface_port config cfg_disable_char_replacement disable_char_replacement Input 1
|
||||
add_interface_port config cfg_disable_scrambler disable_scrambler Input 1
|
||||
add_interface_port config cfg_lanes_disable lanes_disable Input NUM_LANES
|
||||
add_interface_port config cfg_links_disable links_disable Input NUM_LINKS
|
||||
add_interface_port config cfg_lmfc_offset lmfc_offset Input 8
|
||||
add_interface_port config cfg_octets_per_multiframe octets_per_multiframe Input 10
|
||||
add_interface_port config cfg_octets_per_frame octets_per_frame Input 8
|
||||
add_interface_port config cfg_sysref_disable sysref_disable Input 1
|
||||
add_interface_port config cfg_sysref_oneshot sysref_oneshot Input 1
|
||||
add_interface_port config cfg_disable_scrambler disable_scrambler Input 1
|
||||
add_interface_port config cfg_disable_char_replacement disable_char_replacement Input 1
|
||||
add_interface_port config cfg_frame_align_err_threshold frame_align_err_threshold Input 8
|
||||
add_interface_port config ctrl_err_statistics_reset err_statistics_reset Input 1
|
||||
add_interface_port config ctrl_err_statistics_mask err_statistics_mask Input 3
|
||||
|
||||
# device clock domain config interface
|
||||
|
||||
add_interface device_config conduit end
|
||||
set_interface_property device_config associatedClock device_clock
|
||||
set_interface_property device_config associatedReset device_reset
|
||||
|
||||
add_interface_port device_config device_cfg_octets_per_multiframe octets_per_multiframe Input 10
|
||||
add_interface_port device_config device_cfg_octets_per_frame octets_per_frame Input 8
|
||||
add_interface_port device_config device_cfg_beats_per_multiframe beats_per_multiframe Input 8
|
||||
add_interface_port device_config device_cfg_lmfc_offset lmfc_offset Input 8
|
||||
add_interface_port device_config device_cfg_sysref_disable sysref_disable Input 1
|
||||
add_interface_port device_config device_cfg_sysref_oneshot sysref_oneshot Input 1
|
||||
add_interface_port device_config device_cfg_buffer_delay buffer_delay Input 8
|
||||
add_interface_port device_config device_cfg_buffer_early_release buffer_early_release Input 1
|
||||
|
||||
# status interface
|
||||
|
||||
add_interface status conduit end
|
||||
|
|
@ -152,15 +191,18 @@ add_interface_port status status_lane_ifs_ready lane_ifs_ready Output NUM_LANES
|
|||
add_interface_port status status_lane_latency lane_latency Output 14*NUM_LANES
|
||||
add_interface_port status status_err_statistics_cnt err_statistics_cnt Output 32*NUM_LANES
|
||||
add_interface_port status status_lane_frame_align_err_cnt lane_frame_align_err_cnt Output 8*NUM_LANES
|
||||
add_interface_port status status_synth_params0 synth_params0 Output 32
|
||||
add_interface_port status status_synth_params1 synth_params1 Output 32
|
||||
add_interface_port status status_synth_params2 synth_params2 Output 32
|
||||
|
||||
# event interface
|
||||
|
||||
add_interface event conduit end
|
||||
set_interface_property event associatedClock clock
|
||||
set_interface_property event associatedReset reset
|
||||
add_interface device_event conduit end
|
||||
set_interface_property device_event associatedClock device_clock
|
||||
set_interface_property device_event associatedReset device_reset
|
||||
|
||||
add_interface_port event event_sysref_alignment_error sysref_alignment_error Output 1
|
||||
add_interface_port event event_sysref_edge sysref_edge Output 1
|
||||
add_interface_port device_event device_event_sysref_alignment_error sysref_alignment_error Output 1
|
||||
add_interface_port device_event device_event_sysref_edge sysref_edge Output 1
|
||||
|
||||
# ilas_config interface
|
||||
|
||||
|
|
@ -205,15 +247,16 @@ set_port_property lmfc_edge TERMINATION TRUE
|
|||
|
||||
proc jesd204_rx_elaboration_callback {} {
|
||||
set num_lanes [get_parameter_value "NUM_LANES"]
|
||||
set tpl_width [get_parameter_value "TPL_DATA_PATH_WIDTH"]
|
||||
|
||||
# rx_data interface
|
||||
|
||||
add_interface rx_data avalon_streaming source
|
||||
set_interface_property rx_data associatedClock clock
|
||||
set_interface_property rx_data associatedClock device_clock
|
||||
|
||||
add_interface_port rx_data rx_data data output [expr 32*$num_lanes]
|
||||
add_interface_port rx_data rx_data data output [expr 8*$tpl_width*$num_lanes]
|
||||
add_interface_port rx_data rx_valid valid output 1
|
||||
set_interface_property rx_data dataBitsPerSymbol [expr 32*$num_lanes]
|
||||
set_interface_property rx_data dataBitsPerSymbol [expr 8*$tpl_width*$num_lanes]
|
||||
|
||||
# phy interfaces
|
||||
|
||||
|
|
|
|||
|
|
@ -48,3 +48,13 @@ source "$script_dir/util_cdc_constr.tcl"
|
|||
|
||||
# SYNC~ is a asynchronous interface
|
||||
util_cdc_sync_bits_constr {*|jesd204_tx_ctrl:i_tx_ctrl|sync_bits:i_cdc_sync}
|
||||
|
||||
util_cdc_sync_event_constr {*|sync_event:dual_lmfc_mode.i_sync_lmfc}
|
||||
util_cdc_sync_bits_constr {*|sync_bits:dual_lmfc_mode.i_next_mf_ready_cdc}
|
||||
util_cdc_sync_bits_constr {*|sync_bits:dual_lmfc_mode.i_link_reset_done_cdc}
|
||||
util_cdc_sync_bits_constr {*|sync_bits:i_sync_ready}
|
||||
|
||||
set_false_path -to *|dual_lmfc_mode.i_link_reset_done_cdc|cdc_sync_stage1[0]~RTM
|
||||
|
||||
## gearbox on distributed RAM
|
||||
#set_false_path -from *|dual_lmfc_mode.i_tx_gearbox|mem* -to *|dual_lmfc_mode.i_tx_gearbox|mem_rd_data*
|
||||
|
|
|
|||
|
|
@ -57,6 +57,7 @@ ad_ip_files jesd204_tx [list \
|
|||
jesd204_tx.v \
|
||||
jesd204_tx_ctrl.v \
|
||||
jesd204_tx_lane.v \
|
||||
jesd204_tx_gearbox.v \
|
||||
jesd204_tx_constr.sdc \
|
||||
../jesd204_common/jesd204_eof_generator.v \
|
||||
../jesd204_common/jesd204_frame_align_replace.v \
|
||||
|
|
@ -65,7 +66,9 @@ ad_ip_files jesd204_tx [list \
|
|||
../jesd204_common/jesd204_scrambler.v \
|
||||
../jesd204_common/pipeline_stage.v \
|
||||
$ad_hdl_dir/library/util_cdc/sync_bits.v \
|
||||
$ad_hdl_dir/library/util_cdc/sync_event.v \
|
||||
$ad_hdl_dir/library/util_cdc/util_cdc_constr.tcl \
|
||||
$ad_hdl_dir/library/common/ad_upack.v \
|
||||
]
|
||||
|
||||
# parameters
|
||||
|
|
@ -85,23 +88,46 @@ set_parameter_property NUM_OUTPUT_PIPELINE DISPLAY_NAME "Number of output pipeli
|
|||
set_parameter_property NUM_OUTPUT_PIPELINE ALLOWED_RANGES 0:3
|
||||
set_parameter_property NUM_OUTPUT_PIPELINE HDL_PARAMETER true
|
||||
|
||||
# clock
|
||||
add_parameter ASYNC_CLK BOOLEAN false
|
||||
set_parameter_property ASYNC_CLK DISPLAY_NAME "Link and device clock asynchronous"
|
||||
set_parameter_property ASYNC_CLK HDL_PARAMETER true
|
||||
|
||||
ad_ip_parameter TPL_DATA_PATH_WIDTH INTEGER 4 true { \
|
||||
DISPLAY_NAME "Transport layer datapath width" \
|
||||
DISPLAY_UNITS "octets" \
|
||||
ALLOWED_RANGES {4 6 8 12} \
|
||||
}
|
||||
|
||||
# link clock
|
||||
|
||||
add_interface clock clock end
|
||||
add_interface_port clock clk clk Input 1
|
||||
|
||||
# reset
|
||||
# link clock reset
|
||||
|
||||
add_interface reset reset end
|
||||
set_interface_property reset associatedClock clock
|
||||
set_interface_property reset synchronousEdges DEASSERT
|
||||
add_interface_port reset reset reset Input 1
|
||||
|
||||
# device clock
|
||||
|
||||
add_interface device_clock clock end
|
||||
add_interface_port device_clock device_clk clk Input 1
|
||||
|
||||
# device clock reset
|
||||
|
||||
add_interface device_reset reset end
|
||||
set_interface_property device_reset associatedClock device_clock
|
||||
set_interface_property device_reset synchronousEdges DEASSERT
|
||||
|
||||
add_interface_port device_reset device_reset reset Input 1
|
||||
|
||||
# SYSREF~ interface
|
||||
|
||||
add_interface sysref conduit end
|
||||
set_interface_property sysref associatedClock clock
|
||||
set_interface_property sysref associatedReset reset
|
||||
set_interface_property sysref associatedClock device_clock
|
||||
set_interface_property sysref associatedReset device_reset
|
||||
add_interface_port sysref sysref export Input 1
|
||||
|
||||
# SYNC interface
|
||||
|
|
@ -123,12 +149,12 @@ add_interface_port ilas_config ilas_config_rd rd Output 1
|
|||
|
||||
# event interface
|
||||
|
||||
add_interface event conduit end
|
||||
set_interface_property event associatedClock clock
|
||||
set_interface_property event associatedReset reset
|
||||
add_interface device_event conduit end
|
||||
set_interface_property device_event associatedClock device_clock
|
||||
set_interface_property device_event associatedReset device_reset
|
||||
|
||||
add_interface_port event event_sysref_alignment_error sysref_alignment_error Output 1
|
||||
add_interface_port event event_sysref_edge sysref_edge Output 1
|
||||
add_interface_port device_event device_event_sysref_alignment_error sysref_alignment_error Output 1
|
||||
add_interface_port device_event device_event_sysref_edge sysref_edge Output 1
|
||||
|
||||
# control interface
|
||||
|
||||
|
|
@ -151,12 +177,22 @@ add_interface_port config cfg_disable_char_replacement disable_char_replacement
|
|||
add_interface_port config cfg_disable_scrambler disable_scrambler Input 1
|
||||
add_interface_port config cfg_lanes_disable lanes_disable Input NUM_LANES
|
||||
add_interface_port config cfg_links_disable links_disable Input NUM_LINKS
|
||||
add_interface_port config cfg_lmfc_offset lmfc_offset Input 8
|
||||
add_interface_port config cfg_mframes_per_ilas mframes_per_ilas Input 8
|
||||
add_interface_port config cfg_octets_per_frame octets_per_frame Input 8
|
||||
add_interface_port config cfg_skip_ilas skip_ilas Input 1
|
||||
add_interface_port config cfg_sysref_disable sysref_disable Input 1
|
||||
add_interface_port config cfg_sysref_oneshot sysref_oneshot Input 1
|
||||
|
||||
# device clock domain config interface
|
||||
|
||||
add_interface device_config conduit end
|
||||
set_interface_property device_config associatedClock device_clock
|
||||
set_interface_property device_config associatedReset device_reset
|
||||
|
||||
add_interface_port device_config device_cfg_octets_per_multiframe octets_per_multiframe Input 10
|
||||
add_interface_port device_config device_cfg_octets_per_frame octets_per_frame Input 8
|
||||
add_interface_port device_config device_cfg_beats_per_multiframe beats_per_multiframe Input 8
|
||||
add_interface_port device_config device_cfg_lmfc_offset lmfc_offset Input 8
|
||||
add_interface_port device_config device_cfg_sysref_disable sysref_disable Input 1
|
||||
add_interface_port device_config device_cfg_sysref_oneshot sysref_oneshot Input 1
|
||||
|
||||
# status interface
|
||||
|
||||
|
|
@ -166,6 +202,9 @@ set_interface_property status associatedReset reset
|
|||
|
||||
add_interface_port status status_state state Output 2
|
||||
add_interface_port status status_sync sync Output 1
|
||||
add_interface_port status status_synth_params0 synth_params0 Output 32
|
||||
add_interface_port status status_synth_params1 synth_params1 Output 32
|
||||
add_interface_port status status_synth_params2 synth_params2 Output 32
|
||||
|
||||
# lmfc_clk interface
|
||||
|
||||
|
|
@ -185,16 +224,17 @@ set_port_property lmfc_edge TERMINATION TRUE
|
|||
|
||||
proc jesd204_tx_elaboration_callback {} {
|
||||
set num_lanes [get_parameter_value "NUM_LANES"]
|
||||
set tpl_width [get_parameter_value "TPL_DATA_PATH_WIDTH"]
|
||||
|
||||
# tx_data interface
|
||||
|
||||
add_interface tx_data avalon_streaming sink
|
||||
set_interface_property tx_data associatedClock clock
|
||||
set_interface_property tx_data associatedClock device_clock
|
||||
|
||||
add_interface_port tx_data tx_data data input [expr 32*$num_lanes]
|
||||
add_interface_port tx_data tx_data data input [expr 8*$tpl_width*$num_lanes]
|
||||
add_interface_port tx_data tx_ready ready output 1
|
||||
add_interface_port tx_data tx_valid valid input 1
|
||||
set_interface_property tx_data dataBitsPerSymbol [expr 32*$num_lanes]
|
||||
set_interface_property tx_data dataBitsPerSymbol [expr 8*$tpl_width*$num_lanes]
|
||||
|
||||
# phy interfaces
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue