parent
35412c81a9
commit
dd47e30431
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@ -48,6 +48,7 @@ module ad7768_if (
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output adc_clk,
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output reg adc_valid,
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output reg [ 31:0] adc_data,
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output adc_sync,
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// control interface
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@ -136,6 +137,7 @@ module ad7768_if (
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reg [ 35:0] adc_status_clr_m1 = 'd0;
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reg [ 35:0] adc_status_clr = 'd0;
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reg [ 35:0] adc_status_clr_d = 'd0;
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reg adc_valid_d = 'd0;
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// internal signals
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@ -245,6 +247,11 @@ module ad7768_if (
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// data & status
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always @(posedge adc_clk) begin
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adc_valid_d <= adc_valid;
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end
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assign adc_sync = adc_valid & ~adc_valid_d;
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always @(posedge adc_clk) begin
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adc_valid <= adc_valid_int & adc_enable_int;
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adc_data <= {{8{adc_data_int[23]}}, adc_data_int[23:0]};
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@ -3,6 +3,7 @@
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create_bd_port -dir I adc_clk
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create_bd_port -dir I adc_valid
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create_bd_port -dir I adc_sync
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create_bd_port -dir I -from 31 -to 0 adc_data
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create_bd_port -dir I -from 31 -to 0 adc_gpio_0_i
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create_bd_port -dir O -from 31 -to 0 adc_gpio_0_o
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@ -39,6 +40,7 @@ ad_ip_parameter ad7768_gpio CONFIG.C_INTERRUPT_PRESENT 1
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ad_connect adc_clk ad7768_dma/fifo_wr_clk
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ad_connect adc_valid ad7768_dma/fifo_wr_en
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ad_connect adc_sync ad7768_dma/fifo_wr_sync
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ad_connect adc_data ad7768_dma/fifo_wr_din
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ad_connect adc_gpio_0_i ad7768_gpio/gpio_io_i
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ad_connect adc_gpio_0_o ad7768_gpio/gpio_io_o
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@ -107,6 +107,7 @@ module system_top (
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wire adc_clk;
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wire adc_valid;
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wire adc_sync;
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wire [31:0] adc_data;
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wire up_sshot;
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wire [ 1:0] up_format;
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@ -178,6 +179,7 @@ module system_top (
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.data_in (data_in),
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.adc_clk (adc_clk),
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.adc_valid (adc_valid),
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.adc_sync (adc_sync),
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.adc_data (adc_data),
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.up_sshot (up_sshot),
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.up_format (up_format),
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@ -196,6 +198,7 @@ module system_top (
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.adc_gpio_1_o (adc_gpio_o[63:32]),
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.adc_gpio_1_t (adc_gpio_t[63:32]),
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.adc_valid (adc_valid),
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.adc_sync (adc_sync),
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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