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jesd204: jesd204_rx: Don't expose internal states on the status interface 

The DEGLITCH state of the RX state machine is a workaround for misbehaving
PHYs. It is an internal state and an implementation detail and it does not
really make sense to report through the status interface.

Rework things so that DEGLITCH state is reported as part of the CGS state
on the external status interface.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-08-22 15:06:34 +02:00
parent e6aacd2f56
commit dd1b1c89f9
7 changed files with 26 additions and 12 deletions
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2
library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v
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@ -93,7 +93,7 @@ module axi_jesd204_rx #(
input core_event_sysref_alignment_error,
input core_event_sysref_edge,
input [2:0] core_status_ctrl_state,
input [1:0] core_status_ctrl_state,
input [2*NUM_LANES-1:0] core_status_lane_cgs_state,
input [NUM_LANES-1:0] core_status_lane_ifs_ready,
input [14*NUM_LANES-1:0] core_status_lane_latency

2
library/jesd204/axi_jesd204_rx/axi_jesd204_rx_hw.tcl
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@ -134,7 +134,7 @@ add_interface status conduit end
set_interface_property status associatedClock core_clock
set_interface_property status associatedReset core_reset
add_interface_port status core_status_ctrl_state ctrl_state Input 3
add_interface_port status core_status_ctrl_state ctrl_state Input 2
add_interface_port status core_status_lane_cgs_state lane_cgs_state Input 2*NUM_LANES
add_interface_port status core_status_lane_ifs_ready lane_ifs_ready Input NUM_LANES
add_interface_port status core_status_lane_latency lane_latency Input 14*NUM_LANES

10
library/jesd204/axi_jesd204_rx/jesd204_up_rx.v
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@ -63,7 +63,7 @@ module jesd204_up_rx # (
input [2*NUM_LANES-1:0] core_ilas_config_addr,
input [32*NUM_LANES-1:0] core_ilas_config_data,
input [2:0] core_status_ctrl_state,
input [1:0] core_status_ctrl_state,
input [2*NUM_LANES-1:0] core_status_lane_cgs_state,
input [NUM_LANES-1:0] core_status_lane_ifs_ready,
input [14*NUM_LANES-1:0] core_status_lane_latency,
@ -75,12 +75,12 @@ module jesd204_up_rx # (
localparam ELASTIC_BUFFER_SIZE = 256;
wire [2:0] up_status_ctrl_state;
wire [1:0] up_status_ctrl_state;
wire [2*NUM_LANES-1:0] up_status_lane_cgs_state;
wire [31:0] up_lane_rdata[0:NUM_LANES-1];
sync_data #(
.NUM_OF_BITS(3+NUM_LANES*(2))
.NUM_OF_BITS(2+NUM_LANES*(2))
) i_cdc_status (
.in_clk(core_clk),
.in_data({
@ -114,8 +114,8 @@ always @(*) begin
/* JESD RX status */
12'ha0: up_rdata <= {
/* 04-31 */ 28'h00, /* Reserved for future additions */
/* 03 */ 1'b0, /* Reserved for future extensions of ctrl_state */
/* 00-02 */ up_status_ctrl_state /* State of the internal state machine */
/* 02-03 */ 2'b00, /* Reserved for future extensions of ctrl_state */
/* 00-01 */ up_status_ctrl_state /* State of the internal state machine */
};
default: begin
if (up_raddr[11:3] >= LANE_BASE_ADDR &&

2
library/jesd204/jesd204_rx/jesd204_rx_hw.tcl
View File

@ -130,7 +130,7 @@ add_interface status conduit end
set_interface_property status associatedClock clock
set_interface_property status associatedReset reset
add_interface_port status status_ctrl_state ctrl_state Output 3
add_interface_port status status_ctrl_state ctrl_state Output 2
add_interface_port status status_lane_cgs_state lane_cgs_state Output 2*NUM_LANES
add_interface_port status status_lane_ifs_ready lane_ifs_ready Output NUM_LANES
add_interface_port status status_lane_latency lane_latency Output 14*NUM_LANES

2
library/jesd204/jesd204_rx/rx.v
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@ -84,7 +84,7 @@ module jesd204_rx #(
output [NUM_LANES*2-1:0] ilas_config_addr,
output [NUM_LANES*32-1:0] ilas_config_data,
output [2:0] status_ctrl_state,
output [1:0] status_ctrl_state,
output [2*NUM_LANES-1:0] status_lane_cgs_state,
output [NUM_LANES-1:0] status_lane_ifs_ready,
output [14*NUM_LANES-1:0] status_lane_latency

18
library/jesd204/jesd204_rx/rx_ctrl.v
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@ -64,9 +64,14 @@ module jesd204_rx_ctrl #(
output sync,
output reg latency_monitor_reset,
output [2:0] status_state
output reg [1:0] status_state
);
localparam STATUS_STATE_RESET = 2'h1;
localparam STATUS_STATE_WAIT_FOR_PHY = 2'h1;
localparam STATUS_STATE_CGS = 2'h2;
localparam STATUS_STATE_SYNCHRONIZED = 2'h3;
localparam STATE_RESET = 0;
localparam STATE_WAIT_FOR_PHY = 1;
localparam STATE_CGS = 2;
@ -90,7 +95,16 @@ assign ifs_reset = ifs_rst;
assign sync = sync_n;
assign phy_en_char_align = en_align;
assign status_state = state;
always @(posedge clk) begin
case (state)
STATE_RESET: status_state <= STATUS_STATE_RESET;
STATE_WAIT_FOR_PHY: status_state <= STATUS_STATE_WAIT_FOR_PHY;
STATE_CGS: status_state <= STATUS_STATE_CGS;
STATE_DEGLITCH: status_state <= STATUS_STATE_CGS;
STATE_SYNCHRONIZED: status_state <= STATUS_STATE_SYNCHRONIZED;
default: state <= STATUS_STATE_RESET;
endcase
end
always @(posedge clk) begin
case (state)

2
library/jesd204/tb/axi_jesd204_rx_regmap_tb.v
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@ -342,7 +342,7 @@ module axi_jesd204_rx_tb;
.core_event_sysref_alignment_error(1'b0),
.core_event_sysref_edge(1'b0),
.core_status_ctrl_state(3'b000),
.core_status_ctrl_state(2'b00),
.core_status_lane_cgs_state(4'b0000),
.core_status_lane_ifs_ready({NUM_LANES{1'b0}}),
.core_status_lane_latency({NUM_LANES{14'h00}})