Merge pull request #19 from mfornero/hdl_2016_r1
up_axi: Same cycle BVALID/READY fails on Alteramain
commit
dca7334960
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@ -129,6 +129,7 @@ module up_axi (
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reg [31:0] up_wdata = 'd0;
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reg [ 2:0] up_wcount = 'd0;
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reg up_wack_int = 'd0;
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reg up_wack_int_d = 'd0;
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reg up_axi_arready = 'd0;
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reg up_axi_rvalid = 'd0;
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reg [31:0] up_axi_rdata = 'd0;
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@ -163,7 +164,7 @@ module up_axi (
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end
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if ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) begin
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up_axi_bvalid <= 1'b0;
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end else if (up_wack_int == 1'b1) begin
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end else if (up_wack_int_d == 1'b1) begin
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up_axi_bvalid <= 1'b1;
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end
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end
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@ -198,12 +199,14 @@ module up_axi (
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack_int <= 'd0;
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up_wack_int_d <= 'd0;
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end else begin
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if ((up_wcount == 3'h7) && (up_wack == 1'b0)) begin
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up_wack_int <= 1'b1;
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end else if (up_wsel == 1'b1) begin
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up_wack_int <= up_wack;
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end
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up_wack_int_d <= up_wack_int;
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end
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end
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