diff --git a/projects/daq2/common/daq2_bd.tcl b/projects/daq2/common/daq2_bd.tcl index c2057963a..07540aca0 100644 --- a/projects/daq2/common/daq2_bd.tcl +++ b/projects/daq2/common/daq2_bd.tcl @@ -1,33 +1,32 @@ source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl +source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl + +# JESD204B interface configurations set TX_NUM_OF_LANES 4 ; # L set TX_NUM_OF_CONVERTERS 2 ; # M set TX_SAMPLES_PER_FRAME 1 ; # S set TX_SAMPLE_WIDTH 16 ; # N/NP - set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 32 / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)] -set dac_fifo_name axi_ad9144_fifo set dac_data_width [expr $TX_SAMPLE_WIDTH * $TX_NUM_OF_CONVERTERS * $TX_SAMPLES_PER_CHANNEL] set RX_NUM_OF_LANES 4 ; # L set RX_NUM_OF_CONVERTERS 2 ; # M set RX_SAMPLES_PER_FRAME 1 ; # S set RX_SAMPLE_WIDTH 16 ; # N/NP - set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 32 / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] -set adc_fifo_name axi_ad9680_fifo set adc_data_width [expr $RX_SAMPLE_WIDTH * $RX_NUM_OF_CONVERTERS * $RX_SAMPLES_PER_CHANNEL] -set adc_dma_data_width 64 # dac peripherals -ad_ip_instance axi_adxcvr axi_ad9144_xcvr -ad_ip_parameter axi_ad9144_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES -ad_ip_parameter axi_ad9144_xcvr CONFIG.QPLL_ENABLE 1 -ad_ip_parameter axi_ad9144_xcvr CONFIG.TX_OR_RX_N 1 +ad_ip_instance axi_adxcvr axi_ad9144_xcvr [list \ + NUM_OF_LANES $TX_NUM_OF_LANES \ + QPLL_ENABLE 1 \ + TX_OR_RX_N 1 \ +] adi_axi_jesd204_tx_create axi_ad9144_jesd $TX_NUM_OF_LANES @@ -37,35 +36,47 @@ adi_tpl_jesd204_tx_create axi_ad9144_tpl $TX_NUM_OF_LANES \ $TX_SAMPLE_WIDTH \ ad_ip_instance util_upack2 axi_ad9144_upack [list \ - NUM_OF_CHANNELS $TX_NUM_OF_CONVERTERS \ - SAMPLES_PER_CHANNEL $TX_SAMPLES_PER_CHANNEL \ - SAMPLE_DATA_WIDTH $TX_SAMPLE_WIDTH \ + NUM_OF_CHANNELS 2 \ + SAMPLES_PER_CHANNEL 4 \ + SAMPLE_DATA_WIDTH 16 \ ] -ad_ip_instance axi_dmac axi_ad9144_dma -ad_ip_parameter axi_ad9144_dma CONFIG.DMA_TYPE_SRC 0 -ad_ip_parameter axi_ad9144_dma CONFIG.DMA_TYPE_DEST 1 -ad_ip_parameter axi_ad9144_dma CONFIG.ID 1 -ad_ip_parameter axi_ad9144_dma CONFIG.AXI_SLICE_SRC 0 -ad_ip_parameter axi_ad9144_dma CONFIG.AXI_SLICE_DEST 0 -ad_ip_parameter axi_ad9144_dma CONFIG.DMA_LENGTH_WIDTH 24 -ad_ip_parameter axi_ad9144_dma CONFIG.DMA_2D_TRANSFER 0 -ad_ip_parameter axi_ad9144_dma CONFIG.CYCLIC 0 -ad_ip_parameter axi_ad9144_dma CONFIG.DMA_DATA_WIDTH_SRC 128 -ad_ip_parameter axi_ad9144_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_data_width +ad_ip_instance axi_dmac axi_ad9144_dma [list \ + DMA_TYPE_SRC 0 \ + DMA_TYPE_DEST 1 \ + ID 1 \ + AXI_SLICE_SRC 0 \ + AXI_SLICE_DEST 0 \ + DMA_LENGTH_WIDTH 24 \ + DMA_2D_TRANSFER 0 \ + CYCLIC 0 \ + DMA_DATA_WIDTH_SRC 128 \ + DMA_DATA_WIDTH_DEST $dac_data_width \ +] -ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_data_width $dac_fifo_address_width +ad_data_offload_create axi_ad9144_offload \ + 1 \ + $dac_offload_type \ + $dac_offload_size \ + $dac_data_width \ + $dac_data_width \ + $plddr_offload_axi_data_width \ + $plddr_offload_axi_addr_width + +# synchronization interface +ad_connect axi_ad9144_offload/init_req axi_ad9144_dma/m_axis_xfer_req +ad_connect axi_ad9144_offload/sync_ext GND # adc peripherals -ad_ip_instance axi_adxcvr axi_ad9680_xcvr -ad_ip_parameter axi_ad9680_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES -ad_ip_parameter axi_ad9680_xcvr CONFIG.QPLL_ENABLE 0 -ad_ip_parameter axi_ad9680_xcvr CONFIG.TX_OR_RX_N 0 +ad_ip_instance axi_adxcvr axi_ad9680_xcvr [list \ + NUM_OF_LANES $RX_NUM_OF_LANES \ + QPLL_ENABLE 0 \ + TX_OR_RX_N 0 \ +] adi_axi_jesd204_rx_create axi_ad9680_jesd $RX_NUM_OF_LANES - adi_tpl_jesd204_rx_create axi_ad9680_tpl $RX_NUM_OF_LANES \ $RX_NUM_OF_CONVERTERS \ $RX_SAMPLES_PER_FRAME \ @@ -77,33 +88,46 @@ ad_ip_instance util_cpack2 axi_ad9680_cpack [list \ SAMPLE_DATA_WIDTH $RX_SAMPLE_WIDTH \ ] -ad_ip_instance axi_dmac axi_ad9680_dma -ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_SRC 1 -ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_DEST 0 -ad_ip_parameter axi_ad9680_dma CONFIG.ID 0 -ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_SRC 0 -ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_DEST 0 -ad_ip_parameter axi_ad9680_dma CONFIG.SYNC_TRANSFER_START 0 -ad_ip_parameter axi_ad9680_dma CONFIG.DMA_LENGTH_WIDTH 24 -ad_ip_parameter axi_ad9680_dma CONFIG.DMA_2D_TRANSFER 0 -ad_ip_parameter axi_ad9680_dma CONFIG.CYCLIC 0 -ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_dma_data_width -ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_DEST 64 +ad_ip_instance axi_dmac axi_ad9680_dma [list \ + DMA_TYPE_SRC 1 \ + DMA_TYPE_DEST 0 \ + ID 0 \ + AXI_SLICE_SRC 0 \ + AXI_SLICE_DEST 0 \ + SYNC_TRANSFER_START 0 \ + DMA_LENGTH_WIDTH 24 \ + DMA_2D_TRANSFER 0 \ + CYCLIC 0 \ + DMA_DATA_WIDTH_SRC $adc_data_width \ + DMA_DATA_WIDTH_DEST 64 \ +] -ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_dma_data_width $adc_fifo_address_width +ad_data_offload_create axi_ad9680_offload \ + 0 \ + $adc_offload_type \ + $adc_offload_size \ + $adc_data_width \ + $adc_data_width \ + $plddr_offload_axi_data_width \ + $plddr_offload_axi_addr_width + +# synchronization interface +ad_connect axi_ad9680_offload/init_req axi_ad9680_dma/s_axis_xfer_req +ad_connect axi_ad9680_offload/sync_ext GND # shared transceiver core -ad_ip_instance util_adxcvr util_daq2_xcvr -ad_ip_parameter util_daq2_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES -ad_ip_parameter util_daq2_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES -ad_ip_parameter util_daq2_xcvr CONFIG.QPLL_REFCLK_DIV 1 -ad_ip_parameter util_daq2_xcvr CONFIG.QPLL_FBDIV_RATIO 1 -ad_ip_parameter util_daq2_xcvr CONFIG.QPLL_FBDIV 0x30; # 20 -ad_ip_parameter util_daq2_xcvr CONFIG.RX_OUT_DIV 1 -ad_ip_parameter util_daq2_xcvr CONFIG.TX_OUT_DIV 1 -ad_ip_parameter util_daq2_xcvr CONFIG.RX_DFE_LPM_CFG 0x0104 -ad_ip_parameter util_daq2_xcvr CONFIG.RX_CDR_CFG 0x0B000023FF10400020 +ad_ip_instance util_adxcvr util_daq2_xcvr [list \ + RX_NUM_OF_LANES $RX_NUM_OF_LANES \ + TX_NUM_OF_LANES $TX_NUM_OF_LANES \ + QPLL_REFCLK_DIV 1 \ + QPLL_FBDIV_RATIO 1 \ + QPLL_FBDIV 0x30 \ + RX_OUT_DIV 1 \ + TX_OUT_DIV 1 \ + RX_DFE_LPM_CFG 0x0104 \ + RX_CDR_CFG 0x0B000023FF10400020 \ +] ad_connect $sys_cpu_resetn util_daq2_xcvr/up_rstn ad_connect $sys_cpu_clk util_daq2_xcvr/up_clk @@ -133,25 +157,18 @@ for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} { ad_connect axi_ad9144_tpl/dac_data_$i axi_ad9144_upack/fifo_rd_data_$i } -ad_connect util_daq2_xcvr/tx_out_clk_0 axi_ad9144_fifo/dac_clk -ad_connect axi_ad9144_jesd_rstgen/peripheral_reset axi_ad9144_fifo/dac_rst - -# TODO: Add streaming AXI interface for DAC FIFO -ad_connect axi_ad9144_upack/s_axis_valid VCC -ad_connect axi_ad9144_upack/s_axis_ready axi_ad9144_fifo/dac_valid -ad_connect axi_ad9144_upack/s_axis_data axi_ad9144_fifo/dac_data -ad_connect axi_ad9144_tpl/dac_dunf axi_ad9144_fifo/dac_dunf - -ad_connect $sys_cpu_clk axi_ad9144_fifo/dma_clk -ad_connect $sys_cpu_reset axi_ad9144_fifo/dma_rst +ad_connect $sys_cpu_clk axi_ad9144_offload/s_axi_aclk +ad_connect util_daq2_xcvr/tx_out_clk_0 axi_ad9144_offload/m_axis_aclk +ad_connect $sys_cpu_clk axi_ad9144_offload/s_axis_aclk ad_connect $sys_cpu_clk axi_ad9144_dma/m_axis_aclk + +ad_connect $sys_cpu_resetn axi_ad9144_offload/s_axi_aresetn +ad_connect axi_ad9144_jesd_rstgen/peripheral_aresetn axi_ad9144_offload/m_axis_aresetn +ad_connect $sys_cpu_resetn axi_ad9144_offload/s_axis_aresetn ad_connect $sys_cpu_resetn axi_ad9144_dma/m_src_axi_aresetn -ad_connect axi_ad9144_fifo/dma_xfer_req axi_ad9144_dma/m_axis_xfer_req -ad_connect axi_ad9144_fifo/dma_ready axi_ad9144_dma/m_axis_ready -ad_connect axi_ad9144_fifo/dma_data axi_ad9144_dma/m_axis_data -ad_connect axi_ad9144_fifo/dma_valid axi_ad9144_dma/m_axis_valid -ad_connect axi_ad9144_fifo/dma_xfer_last axi_ad9144_dma/m_axis_last +ad_connect axi_ad9144_upack/s_axis axi_ad9144_offload/m_axis +ad_connect axi_ad9144_offload/s_axis axi_ad9144_dma/m_axis # connections (adc) @@ -171,20 +188,20 @@ for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} { } ad_connect axi_ad9680_tpl/adc_dovf axi_ad9680_cpack/fifo_wr_overflow -ad_connect util_daq2_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk -ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst - -ad_connect axi_ad9680_cpack/packed_fifo_wr_en axi_ad9680_fifo/adc_wr -ad_connect axi_ad9680_cpack/packed_fifo_wr_data axi_ad9680_fifo/adc_wdata -ad_connect axi_ad9680_cpack/packed_fifo_wr_overflow axi_ad9680_fifo/adc_wovf - -ad_connect $sys_cpu_clk axi_ad9680_fifo/dma_clk +ad_connect $sys_cpu_clk axi_ad9680_offload/s_axi_aclk +ad_connect util_daq2_xcvr/rx_out_clk_0 axi_ad9680_offload/s_axis_aclk +ad_connect $sys_cpu_clk axi_ad9680_offload/m_axis_aclk ad_connect $sys_cpu_clk axi_ad9680_dma/s_axis_aclk + +ad_connect $sys_cpu_resetn axi_ad9680_offload/s_axi_aresetn +ad_connect axi_ad9680_jesd_rstgen/peripheral_aresetn axi_ad9680_offload/s_axis_aresetn ad_connect $sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn -ad_connect axi_ad9680_fifo/dma_wr axi_ad9680_dma/s_axis_valid -ad_connect axi_ad9680_fifo/dma_wdata axi_ad9680_dma/s_axis_data -ad_connect axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready -ad_connect axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req +ad_connect $sys_cpu_resetn axi_ad9680_offload/m_axis_aresetn + +ad_connect axi_ad9680_cpack/packed_fifo_wr_en axi_ad9680_offload/i_data_offload/s_axis_valid +ad_connect axi_ad9680_cpack/packed_fifo_wr_data axi_ad9680_offload/i_data_offload/s_axis_data + +ad_connect axi_ad9680_offload/m_axis axi_ad9680_dma/s_axis # interconnect (cpu) @@ -192,10 +209,12 @@ ad_cpu_interconnect 0x44A60000 axi_ad9144_xcvr ad_cpu_interconnect 0x44A04000 axi_ad9144_tpl ad_cpu_interconnect 0x44A90000 axi_ad9144_jesd ad_cpu_interconnect 0x7c420000 axi_ad9144_dma +ad_cpu_interconnect 0x7c440000 axi_ad9144_offload ad_cpu_interconnect 0x44A50000 axi_ad9680_xcvr ad_cpu_interconnect 0x44A10000 axi_ad9680_tpl ad_cpu_interconnect 0x44AA0000 axi_ad9680_jesd ad_cpu_interconnect 0x7c400000 axi_ad9680_dma +ad_cpu_interconnect 0x7c460000 axi_ad9680_offload # gt uses hp3, and 100MHz clock for both DRP and AXI4 @@ -216,5 +235,3 @@ ad_cpu_interrupt ps-11 mb-14 axi_ad9680_jesd/irq ad_cpu_interrupt ps-12 mb-13 axi_ad9144_dma/irq ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq -ad_connect axi_ad9144_fifo/bypass GND - diff --git a/projects/daq2/zc706/Makefile b/projects/daq2/zc706/Makefile index 1a9b5fe4d..58cd689dc 100644 --- a/projects/daq2/zc706/Makefile +++ b/projects/daq2/zc706/Makefile @@ -34,5 +34,8 @@ LIB_DEPS += util_pack/util_upack2 LIB_DEPS += xilinx/axi_adcfifo LIB_DEPS += xilinx/axi_adxcvr LIB_DEPS += xilinx/util_adxcvr +LIB_DEPS += util_axis_fifo_asym +LIB_DEPS += data_offload +LIB_DEPS += util_fifo2axi_bridge include ../../scripts/project-xilinx.mk diff --git a/projects/daq2/zc706/system_bd.tcl b/projects/daq2/zc706/system_bd.tcl index 24eeaf00e..df1ef370a 100644 --- a/projects/daq2/zc706/system_bd.tcl +++ b/projects/daq2/zc706/system_bd.tcl @@ -1,21 +1,70 @@ -## FIFO depth is 1GB, PL_DDR is used -set adc_fifo_address_width 16 +## Offload attributes +set adc_offload_type 1 ; ## PL_DDR +set adc_offload_size 4294967295 ; ## 4 Gbyte -## FIFO depth is 8Mb - 500k samples -set dac_fifo_address_width 16 +set dac_offload_type 0 ; ## BRAM +set dac_offload_size 512000 ; ## 512 kbyte + +set plddr_offload_axi_data_width 512 +set plddr_offload_axi_addr_width 30 ## NOTE: With this configuration the #36Kb BRAM utilization is at ~51% -source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl -source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl -source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl -source ../common/daq2_bd.tcl source $ad_hdl_dir/projects/scripts/adi_pd.tcl +source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl +source ../common/daq2_bd.tcl + +################################################################################ +## DDR3 MIG for Data Offload IP +################################################################################ + +if {$adc_offload_type} { + set offload_name axi_ad9680_offload +} + +if {$dac_offload_type} { + set offload_name axi_ad9144_offload +} + +if {$adc_offload_type || $dac_offload_type} { + + ad_ip_instance proc_sys_reset axi_rstgen + ad_ip_instance mig_7series axi_ddr_cntrl + file copy -force $ad_hdl_dir/projects/common/zc706/zc706_plddr3_mig.prj [get_property IP_DIR \ + [get_ips [get_property CONFIG.Component_Name [get_bd_cells axi_ddr_cntrl]]]] + ad_ip_parameter axi_ddr_cntrl CONFIG.XML_INPUT_FILE zc706_plddr3_mig.prj + + # PL-DDR data offload interfaces + create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk + create_bd_port -dir I -type rst sys_rst + set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst] + create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 + + ad_connect axi_ddr_cntrl/ui_clk axi_rstgen/slowest_sync_clk + ad_connect axi_ddr_cntrl/ui_clk $offload_name/fifo2axi_bridge/axi_clk + ad_connect axi_ddr_cntrl/S_AXI $offload_name/fifo2axi_bridge/ddr_axi + ad_connect axi_rstgen/peripheral_aresetn $offload_name/fifo2axi_bridge/axi_resetn + ad_connect axi_rstgen/peripheral_aresetn axi_ddr_cntrl/aresetn + ad_connect sys_cpu_resetn axi_rstgen/ext_reset_in + + assign_bd_address [get_bd_addr_segs -of_objects [get_bd_cells axi_ddr_cntrl]] + + ad_connect sys_rst axi_ddr_cntrl/sys_rst + ad_connect sys_clk axi_ddr_cntrl/SYS_CLK + ad_connect ddr3 axi_ddr_cntrl/DDR3 + ad_connect axi_ddr_cntrl/device_temp_i GND + ad_connect $offload_name/i_data_offload/ddr_calib_done axi_ddr_cntrl/init_calib_complete + +} + +################################################################################ +# System ID +################################################################################ -#system ID ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 -sysid_gen_sys_init_file +set sys_cstring "ADC_OFFLOAD_TYPE=$adc_offload_type\nDAC_OFFLOAD_TYPE=$dac_offload_type" +sysid_gen_sys_init_file $sys_cstring diff --git a/projects/daq2/zc706/system_top.v b/projects/daq2/zc706/system_top.v index 3e2bab14c..87c0d1576 100644 --- a/projects/daq2/zc706/system_top.v +++ b/projects/daq2/zc706/system_top.v @@ -250,6 +250,9 @@ module system_top ( .ddr3_ras_n (ddr3_ras_n), .ddr3_reset_n (ddr3_reset_n), .ddr3_we_n (ddr3_we_n), + .sys_clk_clk_n (sys_clk_n), + .sys_clk_clk_p (sys_clk_p), + .sys_rst (sys_rst), .ddr_addr (ddr_addr), .ddr_ba (ddr_ba), .ddr_cas_n (ddr_cas_n), @@ -311,9 +314,9 @@ module system_top ( .spi1_sdi_i (1'b1), .spi1_sdo_i (spi1_mosi), .spi1_sdo_o (spi1_mosi), - .sys_clk_clk_n (sys_clk_n), - .sys_clk_clk_p (sys_clk_p), - .sys_rst (sys_rst), + //.sys_clk_clk_n (sys_clk_n), + //.sys_clk_clk_p (sys_clk_p), + //.sys_rst (sys_rst), .tx_data_0_n (tx_data_n[0]), .tx_data_0_p (tx_data_p[0]), .tx_data_1_n (tx_data_n[1]),