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Merge branch 'hdl_2016_r2' into dev

main
Istvan Csomortani 2016-12-16 16:21:09 +00:00
parent 905c7ccf99 8879218502
commit dc70807de2
7 changed files with 13 additions and 9 deletions
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2
library/axi_ad9122/axi_ad9122_constr.xdc
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@ -1 +1,3 @@
set_false_path -from [get_cells -hier -filter {name =~ *up_drp_locked_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dac_status_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ */axi_ad9122/*/i_core_rst_reg/rst_reg* && IS_SEQUENTIAL}]
-to [get_cells -hier -filter {name =~ */axi_ad9122/inst/i_if/i_serdes_out_clk/g_data[0].i_serdes && IS_SEQUENTIAL}]

2
library/common/ad_axi_ip_constr.xdc
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@ -16,5 +16,5 @@ set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_data* && I
set_false_path -from [get_cells -hier -filter {name =~ *d_count_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_count_toggle_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *d_count_hold* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_d_count* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_count_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_count_toggle_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_core_preset_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_*preset_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}]

7
projects/ad6676evb/common/ad6676evb_bd.tcl
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@ -33,14 +33,13 @@ set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad6676_dma
set util_ad6676_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_ad6676_xcvr]
set_property -dict [list CONFIG.QPLL_FBDIV {"0010000000"}] $util_ad6676_xcvr
set_property -dict [list CONFIG.CPLL_FBDIV {2}] $util_ad6676_xcvr
set_property -dict [list CONFIG.CPLL_FBDIV_4_5 {5}] $util_ad6676_xcvr
set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_ad6676_xcvr
set_property -dict [list CONFIG.TX_OUT_DIV {1}] $util_ad6676_xcvr
set_property -dict [list CONFIG.TX_CLK25_DIV {10}] $util_ad6676_xcvr
set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $util_ad6676_xcvr
set_property -dict [list CONFIG.RX_OUT_DIV {1}] $util_ad6676_xcvr
set_property -dict [list CONFIG.RX_CLK25_DIV {10}] $util_ad6676_xcvr
set_property -dict [list CONFIG.RX_CLK25_DIV {8}] $util_ad6676_xcvr
set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0904}] $util_ad6676_xcvr
set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff10200020}] $util_ad6676_xcvr
set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff20400020}] $util_ad6676_xcvr
# reference clocks & resets

4
projects/ad6676evb/vc707/system_constr.xdc
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@ -30,8 +30,8 @@ set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports adc_agc4]
# clocks
create_clock -name rx_ref_clk -period 3.30 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.60 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
create_clock -name rx_ref_clk -period 5.00 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 10.00 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]

1
projects/ad6676evb/vc707/system_top.v
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@ -219,6 +219,7 @@ module system_top (
.I (rx_sysref),
.O (rx_sysref_p),
.OB (rx_sysref_n));
assign rx_sysref = gpio_o[48]
OBUFDS i_obufds_rx_sync (
.I (rx_sync),

4
projects/ad6676evb/zc706/system_constr.xdc
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@ -30,8 +30,8 @@ set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports adc_agc4
# clocks
create_clock -name rx_ref_clk -period 3.30 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.60 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
create_clock -name rx_ref_clk -period 5.00 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 10.00 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]

2
projects/ad6676evb/zc706/system_top.v
View File

@ -193,6 +193,8 @@ module system_top (
.I (rx_sysref),
.O (rx_sysref_p),
.OB (rx_sysref_n));
assign rx_sysref = gpio_o[48];
OBUFDS i_obufds_rx_sync (
.I (rx_sync),