From dbcf8389b314c6be85eb16bee0615c235f7c078f Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Fri, 27 Mar 2015 15:37:50 +0200 Subject: [PATCH] fmcomms1: Updated zed project to the latest framework --- projects/fmcomms1/zed/system_bd.tcl | 17 +- projects/fmcomms1/zed/system_project.tcl | 3 +- projects/fmcomms1/zed/system_top.v | 221 ++++++++++++----------- 3 files changed, 126 insertions(+), 115 deletions(-) diff --git a/projects/fmcomms1/zed/system_bd.tcl b/projects/fmcomms1/zed/system_bd.tcl index 58b9dfc27..a59a1f001 100644 --- a/projects/fmcomms1/zed/system_bd.tcl +++ b/projects/fmcomms1/zed/system_bd.tcl @@ -1,13 +1,14 @@ source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl + source $ad_hdl_dir/projects/common/xilinx/sys_wfifo.tcl source ../common/fmcomms1_bd.tcl # Add extra register slice between ADC DMA and HP1 to meet timing - delete_bd_objs [get_bd_intf_nets axi_ad9643_dma_axi] - create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0 - set_property -dict [list CONFIG.REG_AW {0} CONFIG.REG_AR {0} CONFIG.REG_W {1} CONFIG.REG_R {0} CONFIG.REG_B {0}] [get_bd_cells axi_register_slice_0] - connect_bd_intf_net [get_bd_intf_pins axi_register_slice_0/S_AXI] [get_bd_intf_pins axi_ad9643_dma/m_dest_axi] - connect_bd_intf_net [get_bd_intf_pins sys_ps7/S_AXI_HP1] [get_bd_intf_pins axi_register_slice_0/M_AXI] - connect_bd_net -net [get_bd_nets sys_200m_clk] [get_bd_pins axi_register_slice_0/aclk] [get_bd_pins sys_ps7/FCLK_CLK1] - connect_bd_net -net [get_bd_nets sys_100m_resetn] [get_bd_pins axi_register_slice_0/aresetn] [get_bd_pins sys_rstgen/peripheral_aresetn] - assign_bd_address [get_bd_addr_segs {sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM }] + #delete_bd_objs [get_bd_intf_nets axi_ad9643_dma_axi] + #create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0 + #set_property -dict [list CONFIG.REG_AW {0} CONFIG.REG_AR {0} CONFIG.REG_W {1} CONFIG.REG_R {0} CONFIG.REG_B {0}] [get_bd_cells axi_register_slice_0] + #ad_connect [get_bd_intf_pins axi_register_slice_0/S_AXI] [get_bd_intf_pins axi_ad9643_dma/m_dest_axi] + #connect_bd_intf_net [get_bd_intf_pins sys_ps7/S_AXI_HP1] [get_bd_intf_pins axi_register_slice_0/M_AXI] + #connect_bd_net -net [get_bd_nets sys_200m_clk] [get_bd_pins axi_register_slice_0/aclk] [get_bd_pins sys_ps7/FCLK_CLK1] + #connect_bd_net -net [get_bd_nets sys_100m_resetn] [get_bd_pins axi_register_slice_0/aresetn] [get_bd_pins sys_rstgen/peripheral_aresetn] + #assign_bd_address [get_bd_addr_segs {sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM }] diff --git a/projects/fmcomms1/zed/system_project.tcl b/projects/fmcomms1/zed/system_project.tcl index 9c884de85..e9b1f9e6e 100644 --- a/projects/fmcomms1/zed/system_project.tcl +++ b/projects/fmcomms1/zed/system_project.tcl @@ -1,8 +1,7 @@ - - source ../../scripts/adi_env.tcl source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl adi_project_create fmcomms1_zed adi_project_files fmcomms1_zed [list \ diff --git a/projects/fmcomms1/zed/system_top.v b/projects/fmcomms1/zed/system_top.v index ae46ed337..d339ea5fa 100644 --- a/projects/fmcomms1/zed/system_top.v +++ b/projects/fmcomms1/zed/system_top.v @@ -41,28 +41,28 @@ module system_top ( - DDR_addr, - DDR_ba, - DDR_cas_n, - DDR_ck_n, - DDR_ck_p, - DDR_cke, - DDR_cs_n, - DDR_dm, - DDR_dq, - DDR_dqs_n, - DDR_dqs_p, - DDR_odt, - DDR_ras_n, - DDR_reset_n, - DDR_we_n, + ddr_addr, + ddr_ba, + ddr_cas_n, + ddr_ck_n, + ddr_ck_p, + ddr_cke, + ddr_cs_n, + ddr_dm, + ddr_dq, + ddr_dqs_n, + ddr_dqs_p, + ddr_odt, + ddr_ras_n, + ddr_reset_n, + ddr_we_n, - FIXED_IO_ddr_vrn, - FIXED_IO_ddr_vrp, - FIXED_IO_mio, - FIXED_IO_ps_clk, - FIXED_IO_ps_porb, - FIXED_IO_ps_srstb, + fixed_io_ddr_vrn, + fixed_io_ddr_vrp, + fixed_io_mio, + fixed_io_ps_clk, + fixed_io_ps_porb, + fixed_io_ps_srstb, gpio_bd, @@ -106,28 +106,28 @@ module system_top ( otg_vbusoc); - inout [14:0] DDR_addr; - inout [ 2:0] DDR_ba; - inout DDR_cas_n; - inout DDR_ck_n; - inout DDR_ck_p; - inout DDR_cke; - inout DDR_cs_n; - inout [ 3:0] DDR_dm; - inout [31:0] DDR_dq; - inout [ 3:0] DDR_dqs_n; - inout [ 3:0] DDR_dqs_p; - inout DDR_odt; - inout DDR_ras_n; - inout DDR_reset_n; - inout DDR_we_n; + inout [14:0] ddr_addr; + inout [ 2:0] ddr_ba; + inout ddr_cas_n; + inout ddr_ck_n; + inout ddr_ck_p; + inout ddr_cke; + inout ddr_cs_n; + inout [ 3:0] ddr_dm; + inout [31:0] ddr_dq; + inout [ 3:0] ddr_dqs_n; + inout [ 3:0] ddr_dqs_p; + inout ddr_odt; + inout ddr_ras_n; + inout ddr_reset_n; + inout ddr_we_n; - inout FIXED_IO_ddr_vrn; - inout FIXED_IO_ddr_vrp; - inout [53:0] FIXED_IO_mio; - inout FIXED_IO_ps_clk; - inout FIXED_IO_ps_porb; - inout FIXED_IO_ps_srstb; + inout fixed_io_ddr_vrn; + inout fixed_io_ddr_vrp; + inout [53:0] fixed_io_mio; + inout fixed_io_ps_clk; + inout fixed_io_ps_porb; + inout fixed_io_ps_srstb; inout [31:0] gpio_bd; @@ -182,9 +182,17 @@ module system_top ( // internal signals - wire [31:0] gpio_i; - wire [31:0] gpio_o; - wire [31:0] gpio_t; + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire [ 2:0] spi0_csn; + wire spi0_clk; + wire spi0_mosi; + wire spi0_miso; + wire [ 2:0] spi1_csn; + wire spi1_clk; + wire spi1_mosi; + wire spi1_miso; wire dac_clk; wire dac_valid_0; wire dac_enable_0; @@ -232,9 +240,9 @@ module system_top ( ad_iobuf #( .DATA_WIDTH(32)) i_gpio_bd ( - .dt(gpio_t), - .di(gpio_o), - .do(gpio_i), + .dt(gpio_t[31:0]), + .di(gpio_o[31:0]), + .do(gpio_i[31:0]), .dio(gpio_bd)); ad_iobuf #( @@ -284,30 +292,30 @@ module system_top ( end system_wrapper i_system_wrapper ( - .DDR_addr (DDR_addr), - .DDR_ba (DDR_ba), - .DDR_cas_n (DDR_cas_n), - .DDR_ck_n (DDR_ck_n), - .DDR_ck_p (DDR_ck_p), - .DDR_cke (DDR_cke), - .DDR_cs_n (DDR_cs_n), - .DDR_dm (DDR_dm), - .DDR_dq (DDR_dq), - .DDR_dqs_n (DDR_dqs_n), - .DDR_dqs_p (DDR_dqs_p), - .DDR_odt (DDR_odt), - .DDR_ras_n (DDR_ras_n), - .DDR_reset_n (DDR_reset_n), - .DDR_we_n (DDR_we_n), - .FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn), - .FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp), - .FIXED_IO_mio (FIXED_IO_mio), - .FIXED_IO_ps_clk (FIXED_IO_ps_clk), - .FIXED_IO_ps_porb (FIXED_IO_ps_porb), - .FIXED_IO_ps_srstb (FIXED_IO_ps_srstb), - .GPIO_I (gpio_i), - .GPIO_O (gpio_o), - .GPIO_T (gpio_t), + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), .adc_clk (adc_clk), .adc_clk_in_n (adc_clk_in_n), .adc_clk_in_p (adc_clk_in_p), @@ -315,7 +323,6 @@ module system_top ( .adc_data_1 (adc_data_1), .adc_data_in_n (adc_data_in_n), .adc_data_in_p (adc_data_in_p), - .adc_dma_sync (1'b1), .adc_dma_wdata (adc_dma_wdata), .adc_dma_wr (adc_dma_wr), .adc_enable_0 (adc_enable_0), @@ -331,16 +338,8 @@ module system_top ( .dac_clk_out_p (dac_clk_out_p), .dac_data_out_n (dac_data_out_n), .dac_data_out_p (dac_data_out_p), - .dac_ddata_0 (dac_ddata_0), - .dac_ddata_1 (dac_ddata_1), - .dac_dma_rd (dac_dma_rd), - .dac_dma_rdata (dac_dma_rdata), - .dac_enable_0 (dac_enable_0), - .dac_enable_1 (dac_enable_1), .dac_frame_out_n (dac_frame_out_n), .dac_frame_out_p (dac_frame_out_p), - .dac_valid_0 (dac_valid_0), - .dac_valid_1 (dac_valid_1), .hdmi_data (hdmi_data), .hdmi_data_e (hdmi_data_e), .hdmi_hsync (hdmi_hsync), @@ -353,32 +352,44 @@ module system_top ( .i2s_sdata_out (i2s_sdata_out), .iic_fmc_scl_io (iic_scl), .iic_fmc_sda_io (iic_sda), - .iic_mux_scl_I (iic_mux_scl_i_s), - .iic_mux_scl_O (iic_mux_scl_o_s), - .iic_mux_scl_T (iic_mux_scl_t_s), - .iic_mux_sda_I (iic_mux_sda_i_s), - .iic_mux_sda_O (iic_mux_sda_o_s), - .iic_mux_sda_T (iic_mux_sda_t_s), - .ps_intr_0 (ps_intrs[0]), - .ps_intr_1 (ps_intrs[1]), - .ps_intr_10 (ps_intrs[10]), - .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), - .ps_intr_2 (ps_intrs[2]), - .ps_intr_3 (ps_intrs[3]), - .ps_intr_4 (ps_intrs[4]), - .ps_intr_5 (ps_intrs[5]), - .ps_intr_6 (ps_intrs[6]), - .ps_intr_7 (ps_intrs[7]), - .ps_intr_8 (ps_intrs[8]), - .ps_intr_9 (ps_intrs[9]), - .ad9122_dma_irq (ps_intrs[12]), - .ad9643_dma_irq (ps_intrs[13]), - .iic_fmc_intr(ps_intrs[11]), + .iic_mux_scl_i (iic_mux_scl_i_s), + .iic_mux_scl_o (iic_mux_scl_o_s), + .iic_mux_scl_t (iic_mux_scl_t_s), + .iic_mux_sda_i (iic_mux_sda_i_s), + .iic_mux_sda_o (iic_mux_sda_o_s), + .iic_mux_sda_t (iic_mux_sda_t_s), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), .ref_clk (ref_clk), .otg_vbusoc (otg_vbusoc), - .spdif (spdif)); + .spdif (spdif), + .spi0_clk_i (spi0_clk), + .spi0_clk_o (spi0_clk), + .spi0_csn_0_o (spi0_csn[0]), + .spi0_csn_1_o (spi0_csn[1]), + .spi0_csn_2_o (spi0_csn[2]), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi0_miso), + .spi0_sdo_i (spi0_mosi), + .spi0_sdo_o (spi0_mosi), + .spi1_clk_i (spi1_clk), + .spi1_clk_o (spi1_clk), + .spi1_csn_0_o (spi1_csn[0]), + .spi1_csn_1_o (spi1_csn[1]), + .spi1_csn_2_o (spi1_csn[2]), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b1), + .spi1_sdo_i (spi1_mosi), + .spi1_sdo_o (spi1_mosi)); endmodule