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pzsdr2- updates

main
Rejeesh Kutty 2016-11-15 14:15:55 -05:00
parent 0897716167
commit db243df97e
14 changed files with 997 additions and 338 deletions
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26
projects/pzsdr2/README.md Normal file
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@ -0,0 +1,26 @@
# PicoZed SDR SOM (PZSDR2)
This folder contains the PZSDR2 SOM projects for each of the carrier boards.
## Board Design Files
common/pzsdr2_bd.tcl ; pzsdr2 SOM module board design file.
common/ccbrk_bd.tcl ; carrier, break out board design file.
common/ccfmc_bd.tcl ; carrier, fmc board design file.
common/ccpci_bd.tcl ; carrier, pci-e board design file.
common/ccusb_bd.tcl ; carrier, usb board design file.
## Board Constraint Files
common/pzsdr2_constr.xdc ; pzsdr2 SOM base constraints file.
common/pzsdr2_constr_cmos.xdc ; pzsdr2 SOM CMOS mode constraints file.
common/pzsdr2_constr_lvds.xdc ; pzsdr2 SOM LVDS mode constraints file.
common/ccbrk_constr.xdc ; carrier, break out board constraints file.*
common/ccfmc_constr.xdc ; carrier, fmc board constraints file.*
common/ccpci_constr.xdc ; carrier, pci-e board constraints file.
common/ccusb_constr.xdc ; carrier, usb board constraints file.
* FMC & BRK carrier designs includes loopback daughtercards for connectivity testing.

31
projects/pzsdr2/ccbrk_cmos/system_bd.tcl
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@ -1,34 +1,10 @@
source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_bd.tcl
source ../common/pzsdr2_bd.tcl
source ../common/ccbrk_bd.tcl
# CMOS Mode
## core digital interface -- cmos (1) or lvds (0)
delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_clk_out_p]]]
delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_clk_out_n]]]
delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_frame_out_p]]]
delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_frame_out_n]]]
delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_data_out_p]]]
delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports tx_data_out_n]]]
delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_clk_in_p]]]
delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_clk_in_n]]]
delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_frame_in_p]]]
delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_frame_in_n]]]
delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_data_in_p]]]
delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports rx_data_in_n]]]
delete_bd_objs [get_bd_ports tx_clk_out_p]
delete_bd_objs [get_bd_ports tx_clk_out_n]
delete_bd_objs [get_bd_ports tx_frame_out_p]
delete_bd_objs [get_bd_ports tx_frame_out_n]
delete_bd_objs [get_bd_ports tx_data_out_p]
delete_bd_objs [get_bd_ports tx_data_out_n]
delete_bd_objs [get_bd_ports rx_clk_in_p]
delete_bd_objs [get_bd_ports rx_clk_in_n]
delete_bd_objs [get_bd_ports rx_frame_in_p]
delete_bd_objs [get_bd_ports rx_frame_in_n]
delete_bd_objs [get_bd_ports rx_data_in_p]
delete_bd_objs [get_bd_ports rx_data_in_n]
set_property CONFIG.CMOS_OR_LVDS_N 1 [get_bd_cells axi_ad9361]
create_bd_port -dir I rx_clk_in
create_bd_port -dir I rx_frame_in
@ -37,7 +13,6 @@ create_bd_port -dir O tx_clk_out
create_bd_port -dir O tx_frame_out
create_bd_port -dir O -from 11 -to 0 tx_data_out
set_property CONFIG.CMOS_OR_LVDS_N 1 [get_bd_cells axi_ad9361]
ad_connect rx_clk_in axi_ad9361/rx_clk_in
ad_connect rx_frame_in axi_ad9361/rx_frame_in

16
projects/pzsdr2/ccbrk_cmos/system_project.tcl
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@ -3,16 +3,16 @@ source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_create ccbrk_cmos_pzsdr
adi_project_files ccbrk_cmos_pzsdr [list \
"system_top.v" \
"../ccbrk_lvds/system_constr.xdc"\
set p_device "xc7z035ifbg676-2L"
adi_project_create pzsdr2_ccbrk_cmos
adi_project_files pzsdr2_ccbrk_cmos [list \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \
"$ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc" \
"$ad_hdl_dir/projects/common/pzsdr/pzsdr_cmos_system_constr.xdc" ]
"../common/pzsdr2_constr.xdc" \
"../common/pzsdr2_constr_cmos.xdc" \
"../common/ccbrk_constr.xdc" \
"system_top.v" ]
set_property is_enabled false [get_files *axi_gpreg_constr.xdc]
adi_project_run ccbrk_cmos_pzsdr
adi_project_run pzsdr2_ccbrk_cmos

40
projects/pzsdr2/ccbrk_cmos/system_top.v
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@ -65,7 +65,7 @@ module system_top (
inout iic_scl,
inout iic_sda,
inout [11:0] gpio_bd,
inout [19:0] gpio_bd,
input rx_clk_in,
input rx_frame_in,
@ -77,7 +77,8 @@ module system_top (
output enable,
output txnrx,
input clk_out,
input clkout_in,
output clkout_out,
inout gpio_clksel,
inout gpio_resetb,
@ -91,10 +92,8 @@ module system_top (
output spi_mosi,
input spi_miso,
output [87:0] gp_out,
input [87:0] gp_in,
input [ 3:0] gp_in_mio,
input gp_in_1,
output [85:0] gp_out,
input [85:0] gp_in,
input gt_ref_clk_p,
input gt_ref_clk_n,
@ -106,7 +105,6 @@ module system_top (
// internal signals
wire gt_ref_clk;
wire [31:0] gp_misc_s;
wire [95:0] gp_out_s;
wire [95:0] gp_in_s;
wire [63:0] gpio_i;
@ -116,20 +114,10 @@ module system_top (
// assignments
assign tx_gnd = 2'd0;
assign gp_out[87:43] = gp_out_s[87:43];
assign gp_out[42:42] = (gpio_o[61] == 1'b1) ? clk_out : gp_out_s[42:42];
assign gp_out[41: 0] = gp_out_s[41: 0];
assign gp_in_s[95:88] = gp_out_s[95:88];
assign gp_in_s[87:66] = gp_in[87:66];
assign gp_in_s[65:65] = gp_out_s[65];
assign gp_in_s[64: 0] = gp_in[64:0];
assign gp_misc_s[31: 9] = 23'd0;
assign gp_misc_s[ 8: 8] = gp_in_1;
assign gp_misc_s[ 7: 4] = 4'd0;
assign gp_misc_s[ 3: 0] = gp_in_mio;
assign clkout_out = clkout_in;
assign gp_out[85:0] = gp_out_s[85:0];
assign gp_in_s[95:86] = gp_out_s[95:86];
assign gp_in_s[85: 0] = gp_in[85:0];
// instantiations
@ -151,10 +139,10 @@ module system_top (
gpio_ctl, // 43:40
gpio_status})); // 39:32
ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd (
.dio_t (gpio_t[11:0]),
.dio_i (gpio_o[11:0]),
.dio_o (gpio_i[11:0]),
ad_iobuf #(.DATA_WIDTH(20)) i_iobuf_bd (
.dio_t (gpio_t[19:0]),
.dio_i (gpio_o[19:0]),
.dio_o (gpio_i[19:0]),
.dio_p (gpio_bd));
system_wrapper i_system_wrapper (
@ -183,7 +171,7 @@ module system_top (
.gp_in_0 (gp_in_s[31:0]),
.gp_in_1 (gp_in_s[63:32]),
.gp_in_2 (gp_in_s[95:64]),
.gp_in_3 (gp_misc_s),
.gp_in_3 (32'd0),
.gp_out_0 (gp_out_s[31:0]),
.gp_out_1 (gp_out_s[63:32]),
.gp_out_2 (gp_out_s[95:64]),

33
projects/pzsdr2/ccbrk_lvds/system_bd.tcl
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@ -1,4 +1,35 @@
source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_bd.tcl
source ../common/pzsdr2_bd.tcl
source ../common/ccbrk_bd.tcl
## core digital interface -- cmos (1) or lvds (0)
set_property CONFIG.CMOS_OR_LVDS_N 0 [get_bd_cells axi_ad9361]
create_bd_port -dir I rx_clk_in_p
create_bd_port -dir I rx_clk_in_n
create_bd_port -dir I rx_frame_in_p
create_bd_port -dir I rx_frame_in_n
create_bd_port -dir I -from 5 -to 0 rx_data_in_p
create_bd_port -dir I -from 5 -to 0 rx_data_in_n
create_bd_port -dir O tx_clk_out_p
create_bd_port -dir O tx_clk_out_n
create_bd_port -dir O tx_frame_out_p
create_bd_port -dir O tx_frame_out_n
create_bd_port -dir O -from 5 -to 0 tx_data_out_p
create_bd_port -dir O -from 5 -to 0 tx_data_out_n
ad_connect rx_clk_in_p axi_ad9361/rx_clk_in_p
ad_connect rx_clk_in_n axi_ad9361/rx_clk_in_n
ad_connect rx_frame_in_p axi_ad9361/rx_frame_in_p
ad_connect rx_frame_in_n axi_ad9361/rx_frame_in_n
ad_connect rx_data_in_p axi_ad9361/rx_data_in_p
ad_connect rx_data_in_n axi_ad9361/rx_data_in_n
ad_connect tx_clk_out_p axi_ad9361/tx_clk_out_p
ad_connect tx_clk_out_n axi_ad9361/tx_clk_out_n
ad_connect tx_frame_out_p axi_ad9361/tx_frame_out_p
ad_connect tx_frame_out_n axi_ad9361/tx_frame_out_n
ad_connect tx_data_out_p axi_ad9361/tx_data_out_p
ad_connect tx_data_out_n axi_ad9361/tx_data_out_n

238
projects/pzsdr2/ccbrk_lvds/system_constr.xdc
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@ -1,238 +0,0 @@
## constraints
## loopback (P2/P13 are pin swapped on board - so skip gp_*[65])
## p4
set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS18} [get_ports gp_out[0]] ; ## IO_L2P_T0_33
set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS18} [get_ports gp_in[0]] ; ## IO_L1P_T0_33
set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS18} [get_ports gp_out[1]] ; ## IO_L2N_T0_33
set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS18} [get_ports gp_in[1]] ; ## IO_L1N_T0_33
set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS18} [get_ports gp_out[2]] ; ## IO_L4P_T0_33
set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS18} [get_ports gp_in[2]] ; ## IO_L3P_T0_DQS_33
set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS18} [get_ports gp_out[3]] ; ## IO_L4N_T0_33
set_property -dict {PACKAGE_PIN F2 IOSTANDARD LVCMOS18} [get_ports gp_in[3]] ; ## IO_L3N_T0_DQS_33
set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS18} [get_ports gp_out[4]] ; ## IO_L6P_T0_33
set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS18} [get_ports gp_in[4]] ; ## IO_L5P_T0_33
set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS18} [get_ports gp_out[5]] ; ## IO_L6N_T0_VREF_33
set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS18} [get_ports gp_in[5]] ; ## IO_L5N_T0_33
set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS18} [get_ports gp_out[6]] ; ## IO_L8P_T1_33
set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS18} [get_ports gp_in[6]] ; ## IO_L7P_T1_33
set_property -dict {PACKAGE_PIN H3 IOSTANDARD LVCMOS18} [get_ports gp_out[7]] ; ## IO_L8N_T1_33
set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS18} [get_ports gp_in[7]] ; ## IO_L7N_T1_33
set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS18} [get_ports gp_out[8]] ; ## IO_L10P_T1_33
set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS18} [get_ports gp_in[8]] ; ## IO_L9P_T1_DQS_33
set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS18} [get_ports gp_out[9]] ; ## IO_L10N_T1_33
set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS18} [get_ports gp_in[9]] ; ## IO_L9N_T1_DQS_33
set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS18} [get_ports gp_out[10]] ; ## IO_L12P_T1_MRCC_33
set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS18} [get_ports gp_in[10]] ; ## IO_L11P_T1_SRCC_33
## p5
set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS18} [get_ports gp_out[11]] ; ## IO_L17P_T2_33
set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS18} [get_ports gp_in[11]] ; ## IO_L16P_T2_33
set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS18} [get_ports gp_out[12]] ; ## IO_L17N_T2_33
set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVCMOS18} [get_ports gp_in[12]] ; ## IO_L16N_T2_33
set_property -dict {PACKAGE_PIN M7 IOSTANDARD LVCMOS18} [get_ports gp_out[13]] ; ## IO_L19P_T3_33
set_property -dict {PACKAGE_PIN N1 IOSTANDARD LVCMOS18} [get_ports gp_in[13]] ; ## IO_L18P_T2_33
set_property -dict {PACKAGE_PIN L7 IOSTANDARD LVCMOS18} [get_ports gp_out[14]] ; ## IO_L19N_T3_VREF_33
set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS18} [get_ports gp_in[14]] ; ## IO_L18N_T2_33
set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS18} [get_ports gp_out[15]] ; ## IO_L20P_T3_33
set_property -dict {PACKAGE_PIN M8 IOSTANDARD LVCMOS18} [get_ports gp_in[15]] ; ## IO_L21P_T3_DQS_33
set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS18} [get_ports gp_out[16]] ; ## IO_L20N_T3_33
set_property -dict {PACKAGE_PIN L8 IOSTANDARD LVCMOS18} [get_ports gp_in[16]] ; ## IO_L21N_T3_DQS_33
set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS18} [get_ports gp_out[17]] ; ## IO_L22P_T3_33
set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS18} [get_ports gp_in[17]] ; ## IO_L23P_T3_33
set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS18} [get_ports gp_out[18]] ; ## IO_L22N_T3_33
set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS18} [get_ports gp_in[18]] ; ## IO_L23N_T3_33
set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVCMOS18} [get_ports gp_out[19]] ; ## IO_25_VRP_34
set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS18} [get_ports gp_in[19]] ; ## IO_L10N_T1_34
set_property -dict {PACKAGE_PIN L5 IOSTANDARD LVCMOS18} [get_ports gp_out[20]] ; ## IO_L14P_T2_SRCC_33
set_property -dict {PACKAGE_PIN K8 IOSTANDARD LVCMOS18} [get_ports gp_in[20]] ; ## IO_L24P_T3_33
set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS18} [get_ports gp_out[21]] ; ## IO_L14N_T2_SRCC_33
set_property -dict {PACKAGE_PIN K7 IOSTANDARD LVCMOS18} [get_ports gp_in[21]] ; ## IO_L24N_T3_33
set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS18} [get_ports gp_out[22]] ; ## IO_L13P_T2_MRCC_33
set_property -dict {PACKAGE_PIN N3 IOSTANDARD LVCMOS18} [get_ports gp_in[22]] ; ## IO_L15P_T2_DQS_33
set_property -dict {PACKAGE_PIN M5 IOSTANDARD LVCMOS18} [get_ports gp_out[23]] ; ## IO_L13N_T2_MRCC_33
set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS18} [get_ports gp_in[23]] ; ## IO_L15N_T2_DQS_33
## p6
set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS18} [get_ports gp_out[24]] ; ## IO_L2P_T0_34
set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports gp_in[24]] ; ## IO_L1P_T0_34
set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS18} [get_ports gp_out[25]] ; ## IO_L2N_T0_34
set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports gp_in[25]] ; ## IO_L1N_T0_34
set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS18} [get_ports gp_out[26]] ; ## IO_L4P_T0_34
set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS18} [get_ports gp_in[26]] ; ## IO_L3P_T0_DQS_PUDC_B_34
set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS18} [get_ports gp_out[27]] ; ## IO_L4N_T0_34
set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVCMOS18} [get_ports gp_in[27]] ; ## IO_L3N_T0_DQS_34
set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18} [get_ports gp_out[28]] ; ## IO_L6P_T0_34
set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS18} [get_ports gp_in[28]] ; ## IO_L5P_T0_34
set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS18} [get_ports gp_out[29]] ; ## IO_L6N_T0_VREF_34
set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports gp_in[29]] ; ## IO_L5N_T0_34
set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS18} [get_ports gp_out[30]] ; ## IO_L8P_T1_34
set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS18} [get_ports gp_in[30]] ; ## IO_L7P_T1_34
set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS18} [get_ports gp_out[31]] ; ## IO_L12P_T1_MRCC_34
set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS18} [get_ports gp_in[31]] ; ## IO_L11P_T1_SRCC_34
set_property -dict {PACKAGE_PIN F7 IOSTANDARD LVCMOS18} [get_ports gp_out[32]] ; ## IO_L12N_T1_MRCC_34
set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18} [get_ports gp_in[32]] ; ## IO_L11N_T1_SRCC_34
## p7
set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS18} [get_ports gp_out[33]] ; ## IO_L14P_T2_SRCC_34
set_property -dict {PACKAGE_PIN C8 IOSTANDARD LVCMOS18} [get_ports gp_in[33]] ; ## IO_L13P_T2_MRCC_34
set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS18} [get_ports gp_out[34]] ; ## IO_L14N_T2_SRCC_34
set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS18} [get_ports gp_in[34]] ; ## IO_L13N_T2_MRCC_34
set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS18} [get_ports gp_out[35]] ; ## IO_L16P_T2_34
set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports gp_in[35]] ; ## IO_L15P_T2_DQS_34
set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS18} [get_ports gp_out[36]] ; ## IO_L16N_T2_34
set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports gp_in[36]] ; ## IO_L15N_T2_DQS_34
set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports gp_out[37]] ; ## IO_L20P_T3_34
set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports gp_in[37]] ; ## IO_L19P_T3_34
set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports gp_out[38]] ; ## IO_L20N_T3_34
set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports gp_in[38]] ; ## IO_L19N_T3_VREF_34
set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS18} [get_ports gp_out[39]] ; ## IO_L22P_T3_34
set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports gp_in[39]] ; ## IO_L21P_T3_DQS_34
set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS18} [get_ports gp_out[40]] ; ## IO_L22N_T3_34
set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports gp_in[40]] ; ## IO_L21N_T3_DQS_34
set_property -dict {PACKAGE_PIN L9 IOSTANDARD LVCMOS18} [get_ports gp_out[41]] ; ## IO_0_VRN_33
set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS18} [get_ports gp_in[41]] ; ## IO_L18P_T2_34
set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18} [get_ports gp_out[42]] ; ## IO_L18N_T2_34
set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports gp_in[42]] ; ## IO_25_VRP_33
## p13
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports gp_out[43]] ; ## IO_L16P_T2_12
set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVCMOS25} [get_ports gp_in[43]] ; ## IO_L15P_T2_DQS_12
set_property -dict {PACKAGE_PIN AF14 IOSTANDARD LVCMOS25} [get_ports gp_out[44]] ; ## IO_L16N_T2_12
set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVCMOS25} [get_ports gp_in[44]] ; ## IO_L15N_T2_DQS_12
set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS25} [get_ports gp_out[45]] ; ## IO_L14P_T2_SRCC_12
set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVCMOS25} [get_ports gp_in[45]] ; ## IO_L13P_T2_MRCC_12
set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVCMOS25} [get_ports gp_out[46]] ; ## IO_L14N_T2_SRCC_12
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS25} [get_ports gp_in[46]] ; ## IO_L13N_T2_MRCC_12
set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS25} [get_ports gp_out[47]] ; ## IO_L12P_T1_MRCC_12
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS25} [get_ports gp_in[47]] ; ## IO_L11P_T1_SRCC_12
set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS25} [get_ports gp_out[48]] ; ## IO_L12N_T1_MRCC_12
set_property -dict {PACKAGE_PIN AD11 IOSTANDARD LVCMOS25} [get_ports gp_in[48]] ; ## IO_L11N_T1_SRCC_12
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports gp_out[49]] ; ## IO_L10P_T1_12
set_property -dict {PACKAGE_PIN AE11 IOSTANDARD LVCMOS25} [get_ports gp_in[49]] ; ## IO_L9P_T1_DQS_12
set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS25} [get_ports gp_out[50]] ; ## IO_L10N_T1_12
set_property -dict {PACKAGE_PIN AF10 IOSTANDARD LVCMOS25} [get_ports gp_in[50]] ; ## IO_L9N_T1_DQS_12
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS25} [get_ports gp_out[51]] ; ## IO_L8P_T1_12
set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS25} [get_ports gp_in[51]] ; ## IO_L7P_T1_12
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports gp_out[52]] ; ## IO_L8N_T1_12
set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVCMOS25} [get_ports gp_in[52]] ; ## IO_L7N_T1_12
set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVCMOS25} [get_ports gp_out[53]] ; ## IO_L6P_T0_12
set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS25} [get_ports gp_in[53]] ; ## IO_L5P_T0_12
set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS25} [get_ports gp_out[54]] ; ## IO_L6N_T0_VREF_12
set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS25} [get_ports gp_in[54]] ; ## IO_L5N_T0_12
set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS25} [get_ports gp_out[55]] ; ## IO_L4P_T0_12
set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS25} [get_ports gp_in[55]] ; ## IO_L3P_T0_DQS_12
set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS25} [get_ports gp_out[56]] ; ## IO_L4N_T0_12
set_property -dict {PACKAGE_PIN AA10 IOSTANDARD LVCMOS25} [get_ports gp_in[56]] ; ## IO_L3N_T0_DQS_12
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports gp_out[57]] ; ## IO_L2P_T0_12
set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS25} [get_ports gp_in[57]] ; ## IO_L1P_T0_12
set_property -dict {PACKAGE_PIN AC11 IOSTANDARD LVCMOS25} [get_ports gp_out[58]] ; ## IO_L2N_T0_12
set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS25} [get_ports gp_in[58]] ; ## IO_L1N_T0_12
set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports gp_out[59]] ; ## IO_L18P_T2_12
set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVCMOS25} [get_ports gp_in[59]] ; ## IO_L17P_T2_12
set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVCMOS25} [get_ports gp_out[60]] ; ## IO_L18N_T2_12
set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS25} [get_ports gp_in[60]] ; ## IO_L17N_T2_12
set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS25} [get_ports gp_out[61]] ; ## IO_L20P_T3_12
set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS25} [get_ports gp_in[61]] ; ## IO_L19P_T3_12
set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS25} [get_ports gp_out[62]] ; ## IO_L20N_T3_12
set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVCMOS25} [get_ports gp_in[62]] ; ## IO_L19N_T3_VREF_12
set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS25} [get_ports gp_out[63]] ; ## IO_L22P_T3_12
set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVCMOS25} [get_ports gp_in[63]] ; ## IO_L21P_T3_DQS_12
set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS25} [get_ports gp_out[64]] ; ## IO_L22N_T3_12
set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVCMOS25} [get_ports gp_in[64]] ; ## IO_L21N_T3_DQS_12
## p2
set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS25} [get_ports gp_out[65]] ; ## IO_25_13
set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports gp_in[65]] ; ## IO_L6P_T0_13
set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS25} [get_ports gp_out[66]] ; ## IO_L2P_T0_13
set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS25} [get_ports gp_in[66]] ; ## IO_L1P_T0_13
set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS25} [get_ports gp_out[67]] ; ## IO_L2N_T0_13
set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS25} [get_ports gp_in[67]] ; ## IO_L1N_T0_13
set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS25} [get_ports gp_out[68]] ; ## IO_L4P_T0_13
set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS25} [get_ports gp_in[68]] ; ## IO_L3P_T0_DQS_13
set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS25} [get_ports gp_out[69]] ; ## IO_L4N_T0_13
set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS25} [get_ports gp_in[69]] ; ## IO_L3N_T0_DQS_13
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports gp_out[70]] ; ## IO_L8P_T1_13
set_property -dict {PACKAGE_PIN AE22 IOSTANDARD LVCMOS25} [get_ports gp_in[70]] ; ## IO_L7P_T1_13
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports gp_out[71]] ; ## IO_L8N_T1_13
set_property -dict {PACKAGE_PIN AF22 IOSTANDARD LVCMOS25} [get_ports gp_in[71]] ; ## IO_L7N_T1_13
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports gp_out[72]] ; ## IO_L10P_T1_13
set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS25} [get_ports gp_in[72]] ; ## IO_L9P_T1_DQS_13
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports gp_out[73]] ; ## IO_L10N_T1_13
set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS25} [get_ports gp_in[73]] ; ## IO_L9N_T1_DQS_13
set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS25} [get_ports gp_out[74]] ; ## IO_L12P_T1_MRCC_13
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports gp_in[74]] ; ## IO_L11P_T1_SRCC_13
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports gp_out[75]] ; ## IO_L12N_T1_MRCC_13
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports gp_in[75]] ; ## IO_L11N_T1_SRCC_13
set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS25} [get_ports gp_out[76]] ; ## IO_L14P_T2_SRCC_13
set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVCMOS25} [get_ports gp_in[76]] ; ## IO_L13P_T2_MRCC_13
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS25} [get_ports gp_out[77]] ; ## IO_L14N_T2_SRCC_13
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports gp_in[77]] ; ## IO_L13N_T2_MRCC_13
set_property -dict {PACKAGE_PIN AE20 IOSTANDARD LVCMOS25} [get_ports gp_out[78]] ; ## IO_L16P_T2_13
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports gp_in[78]] ; ## IO_L15P_T2_DQS_13
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports gp_out[79]] ; ## IO_L16N_T2_13
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports gp_in[79]] ; ## IO_L15N_T2_DQS_13
set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports gp_out[80]] ; ## IO_L18P_T2_13
set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS25} [get_ports gp_in[80]] ; ## IO_L17P_T2_13
set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVCMOS25} [get_ports gp_out[81]] ; ## IO_L18N_T2_13
set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS25} [get_ports gp_in[81]] ; ## IO_L17N_T2_13
set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS25} [get_ports gp_out[82]] ; ## IO_L20P_T3_13
set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports gp_in[82]] ; ## IO_L19P_T3_13
set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS25} [get_ports gp_out[83]] ; ## IO_L20N_T3_13
set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS25} [get_ports gp_in[83]] ; ## IO_L19N_T3_VREF_13
set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS25} [get_ports gp_out[84]] ; ## IO_L22P_T3_13
set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS25} [get_ports gp_in[84]] ; ## IO_L21P_T3_DQS_13
set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS25} [get_ports gp_out[85]] ; ## IO_L22N_T3_13
set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports gp_in[85]] ; ## IO_L21N_T3_DQS_13
set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS25} [get_ports gp_out[86]] ; ## IO_L24P_T3_13
set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS25} [get_ports gp_in[86]] ; ## IO_L23P_T3_13
set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS25} [get_ports gp_out[87]] ; ## IO_L24N_T3_13
set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports gp_in[87]] ; ## IO_L23N_T3_13
## vcc
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports gp_in_1] ; ## IO_L6N_T0_VREF_13
## on board
set_property -dict {PACKAGE_PIN W6} [get_ports gt_ref_clk_p] ; ## MGTREFCLK0P_111
set_property -dict {PACKAGE_PIN W5} [get_ports gt_ref_clk_n] ; ## MGTREFCLK0N_111
set_property -dict {PACKAGE_PIN AD8} [get_ports gt_rx_p[0]] ; ## MGTXRXP0_111
set_property -dict {PACKAGE_PIN AD7} [get_ports gt_rx_n[0]] ; ## MGTXRXN0_111
set_property -dict {PACKAGE_PIN AE6} [get_ports gt_rx_p[1]] ; ## MGTXRXP1_111
set_property -dict {PACKAGE_PIN AE5} [get_ports gt_rx_n[1]] ; ## MGTXRXN1_111
set_property -dict {PACKAGE_PIN AC6} [get_ports gt_rx_p[2]] ; ## MGTXRXP2_111
set_property -dict {PACKAGE_PIN AC5} [get_ports gt_rx_n[2]] ; ## MGTXRXN2_111
set_property -dict {PACKAGE_PIN AD4} [get_ports gt_rx_p[3]] ; ## MGTXRXP3_111
set_property -dict {PACKAGE_PIN AD3} [get_ports gt_rx_n[3]] ; ## MGTXRXN3_111
set_property -dict {PACKAGE_PIN AF8} [get_ports gt_tx_p[0]] ; ## MGTXTXP0_111
set_property -dict {PACKAGE_PIN AF7} [get_ports gt_tx_n[0]] ; ## MGTXTXN0_111
set_property -dict {PACKAGE_PIN AF4} [get_ports gt_tx_p[1]] ; ## MGTXTXP1_111
set_property -dict {PACKAGE_PIN AF3} [get_ports gt_tx_n[1]] ; ## MGTXTXN1_111
set_property -dict {PACKAGE_PIN AE2} [get_ports gt_tx_p[2]] ; ## MGTXTXP2_111
set_property -dict {PACKAGE_PIN AE1} [get_ports gt_tx_n[2]] ; ## MGTXTXN2_111
set_property -dict {PACKAGE_PIN AC2} [get_ports gt_tx_p[3]] ; ## MGTXTXP3_111
set_property -dict {PACKAGE_PIN AC1} [get_ports gt_tx_n[3]] ; ## MGTXTXN3_111
## mio
set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS18} [get_ports gp_in_mio[0]] ; ## IO_L11N_T1_SRCC_33
set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS18} [get_ports gp_in_mio[1]] ; ## IO_L17P_T2_34
set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS18} [get_ports gp_in_mio[2]] ; ## IO_L7N_T1_34
set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports gp_in_mio[3]] ; ## IO_L10P_T1_34
## clocks
create_clock -name ref_clk -period 4.00 [get_ports gt_ref_clk_p]
create_clock -name xcvr_clk_0 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[0].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
create_clock -name xcvr_clk_1 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[1].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
create_clock -name xcvr_clk_2 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[2].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
create_clock -name xcvr_clk_3 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[3].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]

16
projects/pzsdr2/ccbrk_lvds/system_project.tcl
View File

@ -3,16 +3,16 @@ source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_create ccbrk_lvds_pzsdr
adi_project_files ccbrk_lvds_pzsdr [list \
"system_top.v" \
"system_constr.xdc"\
set p_device "xc7z035ifbg676-2L"
adi_project_create pzsdr2_ccbrk_lvds
adi_project_files pzsdr2_ccbrk_lvds [list \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \
"$ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc" \
"$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
"../common/pzsdr2_constr.xdc" \
"../common/pzsdr2_constr_lvds.xdc" \
"../common/ccbrk_constr.xdc" \
"system_top.v" ]
set_property is_enabled false [get_files *axi_gpreg_constr.xdc]
adi_project_run ccbrk_lvds_pzsdr
adi_project_run pzsdr2_ccbrk_lvds

39
projects/pzsdr2/ccbrk_lvds/system_top.v
View File

@ -65,7 +65,7 @@ module system_top (
inout iic_scl,
inout iic_sda,
inout [11:0] gpio_bd,
inout [19:0] gpio_bd,
input rx_clk_in_p,
input rx_clk_in_n,
@ -82,7 +82,8 @@ module system_top (
output enable,
output txnrx,
input clk_out,
input clkout_in,
output clkout_out,
inout gpio_clksel,
inout gpio_resetb,
@ -96,10 +97,8 @@ module system_top (
output spi_mosi,
input spi_miso,
output [87:0] gp_out,
input [87:0] gp_in,
input [ 3:0] gp_in_mio,
input gp_in_1,
output [85:0] gp_out,
input [85:0] gp_in,
input gt_ref_clk_p,
input gt_ref_clk_n,
@ -111,7 +110,6 @@ module system_top (
// internal signals
wire gt_ref_clk;
wire [31:0] gp_misc_s;
wire [95:0] gp_out_s;
wire [95:0] gp_in_s;
wire [63:0] gpio_i;
@ -120,19 +118,10 @@ module system_top (
// assignments
assign gp_out[87:43] = gp_out_s[87:43];
assign gp_out[42:42] = (gpio_o[61] == 1'b1) ? clk_out : gp_out_s[42:42];
assign gp_out[41: 0] = gp_out_s[41: 0];
assign gp_in_s[95:88] = gp_out_s[95:88];
assign gp_in_s[87:66] = gp_in[87:66];
assign gp_in_s[65:65] = gp_out_s[65];
assign gp_in_s[64: 0] = gp_in[64:0];
assign gp_misc_s[31: 9] = 23'd0;
assign gp_misc_s[ 8: 8] = gp_in_1;
assign gp_misc_s[ 7: 4] = 4'd0;
assign gp_misc_s[ 3: 0] = gp_in_mio;
assign clkout_out = clkout_in;
assign gp_out[85:0] = gp_out_s[85:0];
assign gp_in_s[95:86] = gp_out_s[95:86];
assign gp_in_s[85: 0] = gp_in[85:0];
// instantiations
@ -154,10 +143,10 @@ module system_top (
gpio_ctl, // 43:40
gpio_status})); // 39:32
ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd (
.dio_t (gpio_t[11:0]),
.dio_i (gpio_o[11:0]),
.dio_o (gpio_i[11:0]),
ad_iobuf #(.DATA_WIDTH(20)) i_iobuf_bd (
.dio_t (gpio_t[19:0]),
.dio_i (gpio_o[19:0]),
.dio_o (gpio_i[19:0]),
.dio_p (gpio_bd));
system_wrapper i_system_wrapper (
@ -186,7 +175,7 @@ module system_top (
.gp_in_0 (gp_in_s[31:0]),
.gp_in_1 (gp_in_s[63:32]),
.gp_in_2 (gp_in_s[95:64]),
.gp_in_3 (gp_misc_s),
.gp_in_3 (32'd0),
.gp_out_0 (gp_out_s[31:0]),
.gp_out_1 (gp_out_s[63:32]),
.gp_out_2 (gp_out_s[95:64]),

4
projects/pzsdr2/common/ccbrk_bd.tcl
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@ -47,7 +47,3 @@ ad_connect gp_out_2 axi_gpreg/up_gp_out_2
ad_connect gp_out_3 axi_gpreg/up_gp_out_3
ad_cpu_interconnect 0x41200000 axi_gpreg
## temporary (remove ila indirectly)
delete_bd_objs [get_bd_cells ila_adc]

248
projects/pzsdr2/common/ccbrk_constr.xdc Normal file
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@ -0,0 +1,248 @@
## constraints (ccbrk.c + ccbrk_lb.a)
## ad9361 clkout forward
set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18} [get_ports clkout_out] ; ## (lb: gpio_bd[15]) U1,A7,IO_L18_34_JX4_N,JX4,70,IO_L18_34_JX4_N,P7,32
## push-buttons- led- dip-switches- loopbacks- (ps7 gpio)
set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]] ; ## (lb: gpio_bd[4]) U1,J3,IO_L12_MRCC_33_JX1_N,JX1,83,PB_GPIO_0,P4,31
set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]] ; ## (lb: gpio_bd[5]) U1,D8,IO_L08_34_JX4_N,JX4,38,PB_GPIO_1,P6,19
set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]] ; ## (lb: gpio_bd[6]) U1,F9,IO_L09_34_JX4_P,JX4,41,PB_GPIO_2,P6,26
set_property -dict {PACKAGE_PIN E8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]] ; ## (lb: gpio_bd[12]) U1,E8,IO_L09_34_JX4_N,JX4,43,PB_GPIO_3,P6,28
set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[4]] ; ## (lb: gpio_bd[0]) U1,A8,IO_L17_34_JX4_N,JX4,69,LED_GPIO_0,P7,16
set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS18} [get_ports gpio_bd[5]] ; ## (lb: gpio_bd[1]) U1,W17,IO_25_12_JX4,JX4,16,LED_GPIO_2,P13,3
set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS18} [get_ports gpio_bd[6]] ; ## (lb: gpio_bd[2]) U1,W14,IO_00_12_JX4,JX4,14,LED_GPIO_1,P13,4
set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS18} [get_ports gpio_bd[7]] ; ## (lb: i2c_scl) U1,Y16,IO_L23_12_JX2_P,JX2,97,LED_GPIO_3,P2,4 (U1,AF24,SCL,JX2,17,I2C_SCL,P2,14)
set_property -dict {PACKAGE_PIN Y15 IOSTANDARD LVCMOS18} [get_ports gpio_bd[8]] ; ## (lb: none) U1,Y15,IO_L23_12_JX2_N,JX2,99,DIP_GPIO_0
set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS18} [get_ports gpio_bd[9]] ; ## (lb: none) U1,W16,IO_L24_12_JX4_P,JX4,13,DIP_GPIO_1
set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS18} [get_ports gpio_bd[10]] ; ## (lb: none) U1,W15,IO_L24_12_JX4_N,JX4,15,DIP_GPIO_2
set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS18} [get_ports gpio_bd[11]] ; ## (lb: none) U1,V19,IO_00_13_JX2,JX2,13,DIP_GPIO_3
## orphans- io- (ps7 gpio)
set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS18} [get_ports gpio_bd[12]] ; ## (lb: gpio_bd[3]) U1,V18,IO_25_13_JX2,JX2,14,IO_25_13_JX2,P2,3
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS18} [get_ports gpio_bd[13]] ; ## (lb: i2c_sda) U1,AB24,IO_L06_13_JX2_N,JX2,20,IO_L06_13_JX2_N,P2,15 (U1,AF25,SDA,JX2,19,I2C_SDA,P2,16)
set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS18} [get_ports gpio_bd[14]] ; ## (lb: none) U1,AA24,IO_L06_13_JX2_P,JX2,18,IO_L06_13_JX2_P
set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[15]] ; ## (lb: clkout_out) U1,N8,IO_25_33_JX1,JX1,10,IO_25_33_JX1,P7,31
## ps7- fixed io- to- fpga regular io (ps7 gpio)
set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS18} [get_ports gpio_bd[16]] ; ## U1,K3,IO_L11_SRCC_33_JX1_N,JX1,76,IO_L11_SRCC_33_JX1_N,P4,32 (U1,E26,PS_MIO00_500_JX4,JX4,97,PS_MIO00_500_JX4,P5,21)
set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS18} [get_ports gpio_bd[17]] ; ## U1,A9,IO_L17_34_JX4_P,JX4,67,IO_L17_34_JX4_P,P6,9 (U1,B20,PS_MIO51_501_JX4,JX4,100,PS_MIO51_501_JX4,P6,11)
set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS18} [get_ports gpio_bd[18]] ; ## U1,E5,IO_L07_34_JX4_N,JX4,37,IO_L07_34_JX4_N,P6,20 (U1,C24,PS_MIO15_500_JX4,JX4,85,PS_MIO15_500_JX4,P6,21)
set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports gpio_bd[19]] ; ## U1,E6,IO_L10_34_JX4_P,JX4,42,IO_L10_34_JX4_P,P6,25 (U1,A25,PS_MIO10_500_JX4,JX4,87,PS_MIO10_500_JX4,P6,23)
## ps7- fixed io- to- ps7- fixed io (reference only)
## U1,B19,PS_MIO47_501_JX4,JX4,94,PS_MIO47_501_JX4,P7,24 == U1,E17,PS_MIO46_501_JX4,JX4,92,PS_MIO46_501_JX4,P7,22
## ps7- fixed io- orphans (reference only)
## U1,B25,PS_MIO13_500_JX4,JX4,91,PS_MIO13_500_JX4,P5,9
## U1,D23,PS_MIO14_500_JX4,JX4,93,PS_MIO14_500_JX4,P5,11
## U1,B26,PS_MIO11_500_JX4,JX4,88,PS_MIO11_500_JX4,P7,12
## fpga- regular io
set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS18} [get_ports gp_out[0]] ; ## U1,AA25,IO_L01_13_JX2_P,JX2,1,IO_L01_13_JX2_P,P2,6
set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS18} [get_ports gp_in[0]] ; ## U1,AB26,IO_L02_13_JX2_P,JX2,2,IO_L02_13_JX2_P,P2,5
set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS18} [get_ports gp_out[1]] ; ## U1,AB25,IO_L01_13_JX2_N,JX2,3,IO_L01_13_JX2_N,P2,8
set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS18} [get_ports gp_in[1]] ; ## U1,AC26,IO_L02_13_JX2_N,JX2,4,IO_L02_13_JX2_N,P2,7
set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS18} [get_ports gp_out[2]] ; ## U1,AE25,IO_L03_13_JX2_P,JX2,5,IO_L03_13_JX2_P,P2,10
set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS18} [get_ports gp_in[2]] ; ## U1,AD25,IO_L04_13_JX2_P,JX2,6,IO_L04_13_JX2_P,P2,9
set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS18} [get_ports gp_out[3]] ; ## U1,AE26,IO_L03_13_JX2_N,JX2,7,IO_L03_13_JX2_N,P2,12
set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS18} [get_ports gp_in[3]] ; ## U1,AD26,IO_L04_13_JX2_N,JX2,8,IO_L04_13_JX2_N,P2,11
set_property -dict {PACKAGE_PIN AE22 IOSTANDARD LVCMOS18} [get_ports gp_out[4]] ; ## U1,AE22,IO_L07_13_JX2_P,JX2,23,IO_L07_13_JX2_P,P2,20
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS18} [get_ports gp_in[4]] ; ## U1,AE23,IO_L08_13_JX2_P,JX2,24,IO_L08_13_JX2_P,P2,19
set_property -dict {PACKAGE_PIN AF22 IOSTANDARD LVCMOS18} [get_ports gp_out[5]] ; ## U1,AF22,IO_L07_13_JX2_N,JX2,25,IO_L07_13_JX2_N,P2,22
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS18} [get_ports gp_in[5]] ; ## U1,AF23,IO_L08_13_JX2_N,JX2,26,IO_L08_13_JX2_N,P2,21
set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS18} [get_ports gp_out[6]] ; ## U1,AB21,IO_L09_13_JX2_P,JX2,29,IO_L09_13_JX2_P,P2,24
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS18} [get_ports gp_in[6]] ; ## U1,AA22,IO_L10_13_JX2_P,JX2,30,IO_L10_13_JX2_P,P2,23
set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS18} [get_ports gp_out[7]] ; ## U1,AB22,IO_L09_13_JX2_N,JX2,31,IO_L09_13_JX2_N,P2,26
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS18} [get_ports gp_in[7]] ; ## U1,AA23,IO_L10_13_JX2_N,JX2,32,IO_L10_13_JX2_N,P2,25
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS18} [get_ports gp_out[8]] ; ## U1,AD23,IO_L11_SRCC_13_JX2_P,JX2,35,IO_L11_SRCC_13_JX2_P,P2,28
set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS18} [get_ports gp_in[8]] ; ## U1,AC23,IO_L12_MRCC_13_JX2_P,JX2,36,IO_L12_MRCC_13_JX2_P,P2,27
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS18} [get_ports gp_out[9]] ; ## U1,AD24,IO_L11_SRCC_13_JX2_N,JX2,37,IO_L11_SRCC_13_JX2_N,P2,30
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS18} [get_ports gp_in[9]] ; ## U1,AC24,IO_L12_MRCC_13_JX2_N,JX2,38,IO_L12_MRCC_13_JX2_N,P2,29
set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVCMOS18} [get_ports gp_out[10]] ; ## U1,AD20,IO_L13_MRCC_13_JX2_P,JX2,41,IO_L13_MRCC_13_JX2_P,P2,32
set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS18} [get_ports gp_in[10]] ; ## U1,AC21,IO_L14_SRCC_13_JX2_P,JX2,42,IO_L14_SRCC_13_JX2_P,P2,31
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS18} [get_ports gp_out[11]] ; ## U1,AD21,IO_L13_MRCC_13_JX2_N,JX2,43,IO_L13_MRCC_13_JX2_N,P2,34
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS18} [get_ports gp_in[11]] ; ## U1,AC22,IO_L14_SRCC_13_JX2_N,JX2,44,IO_L14_SRCC_13_JX2_N,P2,33
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS18} [get_ports gp_out[12]] ; ## U1,AF19,IO_L15_13_JX2_P,JX2,47,IO_L15_13_JX2_P,P2,38
set_property -dict {PACKAGE_PIN AE20 IOSTANDARD LVCMOS18} [get_ports gp_in[12]] ; ## U1,AE20,IO_L16_13_JX2_P,JX2,48,IO_L16_13_JX2_P,P2,37
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS18} [get_ports gp_out[13]] ; ## U1,AF20,IO_L15_13_JX2_N,JX2,49,IO_L15_13_JX2_N,P2,40
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS18} [get_ports gp_in[13]] ; ## U1,AE21,IO_L16_13_JX2_N,JX2,50,IO_L16_13_JX2_N,P2,39
set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS18} [get_ports gp_out[14]] ; ## U1,AD18,IO_L17_13_JX2_P,JX2,53,IO_L17_13_JX2_P,P2,42
set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS18} [get_ports gp_in[14]] ; ## U1,AE18,IO_L18_13_JX2_P,JX2,54,IO_L18_13_JX2_P,P2,41
set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS18} [get_ports gp_out[15]] ; ## U1,AD19,IO_L17_13_JX2_N,JX2,55,IO_L17_13_JX2_N,P2,44
set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVCMOS18} [get_ports gp_in[15]] ; ## U1,AF18,IO_L18_13_JX2_N,JX2,56,IO_L18_13_JX2_N,P2,43
set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS18} [get_ports gp_out[16]] ; ## U1,W20,IO_L19_13_JX2_P,JX2,61,IO_L19_13_JX2_P,P2,46
set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS18} [get_ports gp_in[16]] ; ## U1,AA20,IO_L20_13_JX2_P,JX2,62,IO_L20_13_JX2_P,P2,45
set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS18} [get_ports gp_out[17]] ; ## U1,Y20,IO_L19_13_JX2_N,JX2,63,IO_L19_13_JX2_N,P2,48
set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS18} [get_ports gp_in[17]] ; ## U1,AB20,IO_L20_13_JX2_N,JX2,64,IO_L20_13_JX2_N,P2,47
set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS18} [get_ports gp_out[18]] ; ## U1,AC18,IO_L21_13_JX2_P,JX2,67,IO_L21_13_JX2_P,P2,52
set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS18} [get_ports gp_in[18]] ; ## U1,AA19,IO_L22_13_JX2_P,JX2,68,IO_L22_13_JX2_P,P2,51
set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS18} [get_ports gp_out[19]] ; ## U1,AC19,IO_L21_13_JX2_N,JX2,69,IO_L21_13_JX2_N,P2,54
set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS18} [get_ports gp_in[19]] ; ## U1,AB19,IO_L22_13_JX2_N,JX2,70,IO_L22_13_JX2_N,P2,53
set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS18} [get_ports gp_out[20]] ; ## U1,W18,IO_L23_13_JX2_P,JX2,73,IO_L23_13_JX2_P,P2,56
set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS18} [get_ports gp_in[20]] ; ## U1,Y18,IO_L24_13_JX2_P,JX2,74,IO_L24_13_JX2_P,P2,55
set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS18} [get_ports gp_out[21]] ; ## U1,W19,IO_L23_13_JX2_N,JX2,75,IO_L23_13_JX2_N,P2,58
set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS18} [get_ports gp_in[21]] ; ## U1,AA18,IO_L24_13_JX2_N,JX2,76,IO_L24_13_JX2_N,P2,57
set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS18} [get_ports gp_out[22]] ; ## U1,G4,IO_L01_33_JX1_P,JX1,35,IO_L01_33_JX1_P,P4,2
set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS18} [get_ports gp_in[22]] ; ## U1,D4,IO_L02_33_JX1_P,JX1,41,IO_L02_33_JX1_P,P4,1
set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS18} [get_ports gp_out[23]] ; ## U1,F4,IO_L01_33_JX1_N,JX1,37,IO_L01_33_JX1_N,P4,4
set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS18} [get_ports gp_in[23]] ; ## U1,D3,IO_L02_33_JX1_N,JX1,43,IO_L02_33_JX1_N,P4,3
set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS18} [get_ports gp_out[24]] ; ## U1,G2,IO_L03_33_JX1_P,JX1,42,IO_L03_33_JX1_P,P4,6
set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS18} [get_ports gp_in[24]] ; ## U1,D1,IO_L04_33_JX1_P,JX1,47,IO_L04_33_JX1_P,P4,5
set_property -dict {PACKAGE_PIN F2 IOSTANDARD LVCMOS18} [get_ports gp_out[25]] ; ## U1,F2,IO_L03_33_JX1_N,JX1,44,IO_L03_33_JX1_N,P4,8
set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS18} [get_ports gp_in[25]] ; ## U1,C1,IO_L04_33_JX1_N,JX1,49,IO_L04_33_JX1_N,P4,7
set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS18} [get_ports gp_out[26]] ; ## U1,E2,IO_L05_33_JX1_P,JX1,54,IO_L05_33_JX1_P,P4,14
set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS18} [get_ports gp_in[26]] ; ## U1,F3,IO_L06_33_JX1_P,JX1,61,IO_L06_33_JX1_P,P4,13
set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS18} [get_ports gp_out[27]] ; ## U1,E1,IO_L05_33_JX1_N,JX1,56,IO_L05_33_JX1_N,P4,16
set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS18} [get_ports gp_in[27]] ; ## U1,E3,IO_L06_33_JX1_N,JX1,63,IO_L06_33_JX1_N,P4,15
set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS18} [get_ports gp_out[28]] ; ## U1,J1,IO_L07_33_JX1_P,JX1,62,IO_L07_33_JX1_P,P4,18
set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS18} [get_ports gp_in[28]] ; ## U1,H4,IO_L08_33_JX1_P,JX1,67,IO_L08_33_JX1_P,P4,17
set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS18} [get_ports gp_out[29]] ; ## U1,H1,IO_L07_33_JX1_N,JX1,64,IO_L07_33_JX1_N,P4,20
set_property -dict {PACKAGE_PIN H3 IOSTANDARD LVCMOS18} [get_ports gp_in[29]] ; ## U1,H3,IO_L08_33_JX1_N,JX1,69,IO_L08_33_JX1_N,P4,19
set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS18} [get_ports gp_out[30]] ; ## U1,K2,IO_L09_33_JX1_P,JX1,68,IO_L09_33_JX1_P,P4,26
set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS18} [get_ports gp_in[30]] ; ## U1,H2,IO_L10_33_JX1_P,JX1,73,IO_L10_33_JX1_P,P4,25
set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS18} [get_ports gp_out[31]] ; ## U1,K1,IO_L09_33_JX1_N,JX1,70,IO_L09_33_JX1_N,P4,28
set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS18} [get_ports gp_in[31]] ; ## U1,G1,IO_L10_33_JX1_N,JX1,75,IO_L10_33_JX1_N,P4,27
set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS18} [get_ports gp_out[32]] ; ## U1,L3,IO_L11_SRCC_33_JX1_P,JX1,74,IO_L11_SRCC_33_JX1_P,P4,30
set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS18} [get_ports gp_in[32]] ; ## U1,J4,IO_L12_MRCC_33_JX1_P,JX1,81,IO_L12_MRCC_33_JX1_P,P4,29
set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS18} [get_ports gp_out[33]] ; ## U1,M2,IO_L16_33_JX1_P,JX1,11,IO_L16_33_JX1_P,P5,2
set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS18} [get_ports gp_in[33]] ; ## U1,N4,IO_L17_33_JX1_P,JX1,12,IO_L17_33_JX1_P,P5,1
set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVCMOS18} [get_ports gp_out[34]] ; ## U1,L2,IO_L16_33_JX1_N,JX1,13,IO_L16_33_JX1_N,P5,4
set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS18} [get_ports gp_in[34]] ; ## U1,M4,IO_L17_33_JX1_N,JX1,14,IO_L17_33_JX1_N,P5,3
set_property -dict {PACKAGE_PIN N1 IOSTANDARD LVCMOS18} [get_ports gp_out[35]] ; ## U1,N1,IO_L18_33_JX1_P,JX1,17,IO_L18_33_JX1_P,P5,6
set_property -dict {PACKAGE_PIN M7 IOSTANDARD LVCMOS18} [get_ports gp_in[35]] ; ## U1,M7,IO_L19_33_JX1_P,JX1,18,IO_L19_33_JX1_P,P5,5
set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS18} [get_ports gp_out[36]] ; ## U1,M1,IO_L18_33_JX1_N,JX1,19,IO_L18_33_JX1_N,P5,8
set_property -dict {PACKAGE_PIN L7 IOSTANDARD LVCMOS18} [get_ports gp_in[36]] ; ## U1,L7,IO_L19_33_JX1_N,JX1,20,IO_L19_33_JX1_N,P5,7
set_property -dict {PACKAGE_PIN M8 IOSTANDARD LVCMOS18} [get_ports gp_out[37]] ; ## U1,M8,IO_L21_33_JX1_P,JX1,24,IO_L21_33_JX1_P,P5,14
set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS18} [get_ports gp_in[37]] ; ## U1,K5,IO_L20_33_JX1_P,JX1,23,IO_L20_33_JX1_P,P5,13
set_property -dict {PACKAGE_PIN L8 IOSTANDARD LVCMOS18} [get_ports gp_out[38]] ; ## U1,L8,IO_L21_33_JX1_N,JX1,26,IO_L21_33_JX1_N,P5,16
set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS18} [get_ports gp_in[38]] ; ## U1,J5,IO_L20_33_JX1_N,JX1,25,IO_L20_33_JX1_N,P5,15
set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS18} [get_ports gp_out[39]] ; ## U1,N7,IO_L23_33_JX1_P,JX1,30,IO_L23_33_JX1_P,P5,18
set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS18} [get_ports gp_in[39]] ; ## U1,K6,IO_L22_33_JX1_P,JX1,29,IO_L22_33_JX1_P,P5,17
set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS18} [get_ports gp_out[40]] ; ## U1,N6,IO_L23_33_JX1_N,JX1,32,IO_L23_33_JX1_N,P5,20
set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS18} [get_ports gp_in[40]] ; ## U1,J6,IO_L22_33_JX1_N,JX1,31,IO_L22_33_JX1_N,P5,19
set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS18} [get_ports gp_out[41]] ; ## U1,D5,IO_L10_34_JX4_N,JX4,44,IO_L10_34_JX4_N,P6,27
set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVCMOS18} [get_ports gp_in[41]] ; ## U1,K10,IO_25_34_JX4,JX4,64,IO_25_34_JX4,P5,23
set_property -dict {PACKAGE_PIN K8 IOSTANDARD LVCMOS18} [get_ports gp_out[42]] ; ## U1,K8,IO_L24_33_JX1_P,JX1,36,IO_L24_33_JX1_P,P5,26
set_property -dict {PACKAGE_PIN L5 IOSTANDARD LVCMOS18} [get_ports gp_in[42]] ; ## U1,L5,IO_L14_SRCC_33_JX1_P,JX1,48,IO_L14_SRCC_33_JX1_P,P5,25
set_property -dict {PACKAGE_PIN K7 IOSTANDARD LVCMOS18} [get_ports gp_out[43]] ; ## U1,K7,IO_L24_33_JX1_N,JX1,38,IO_L24_33_JX1_N,P5,28
set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS18} [get_ports gp_in[43]] ; ## U1,L4,IO_L14_SRCC_33_JX1_N,JX1,50,IO_L14_SRCC_33_JX1_N,P5,27
set_property -dict {PACKAGE_PIN N3 IOSTANDARD LVCMOS18} [get_ports gp_out[44]] ; ## U1,N3,IO_L15_33_JX1_P,JX1,53,IO_L15_33_JX1_P,P5,30
set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS18} [get_ports gp_in[44]] ; ## U1,M6,IO_L13_MRCC_33_JX1_P,JX1,82,IO_L13_MRCC_33_JX1_P,P5,29
set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS18} [get_ports gp_out[45]] ; ## U1,N2,IO_L15_33_JX1_N,JX1,55,IO_L15_33_JX1_N,P5,32
set_property -dict {PACKAGE_PIN M5 IOSTANDARD LVCMOS18} [get_ports gp_in[45]] ; ## U1,M5,IO_L13_MRCC_33_JX1_N,JX1,84,IO_L13_MRCC_33_JX1_N,P5,31
set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports gp_out[46]] ; ## U1,J11,IO_L01_34_JX4_P,JX4,19,IO_L01_34_JX4_P,P6,2
set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS18} [get_ports gp_in[46]] ; ## U1,G6,IO_L02_34_JX4_P,JX4,20,IO_L02_34_JX4_P,P6,1
set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports gp_out[47]] ; ## U1,H11,IO_L01_34_JX4_N,JX4,21,IO_L01_34_JX4_N,P6,4
set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS18} [get_ports gp_in[47]] ; ## U1,G5,IO_L02_34_JX4_N,JX4,22,IO_L02_34_JX4_N,P6,3
set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS18} [get_ports gp_out[48]] ; ## U1,H9,IO_L03_34_JX4_P,JX4,25,IO_L03_34_JX4_P,P6,6
set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS18} [get_ports gp_in[48]] ; ## U1,H7,IO_L04_34_JX4_P,JX4,26,IO_L04_34_JX4_P,P6,5
set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVCMOS18} [get_ports gp_out[49]] ; ## U1,G9,IO_L03_34_JX4_N,JX4,27,IO_L03_34_JX4_N,P6,8
set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS18} [get_ports gp_in[49]] ; ## U1,H6,IO_L04_34_JX4_N,JX4,28,IO_L04_34_JX4_N,P6,7
set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS18} [get_ports gp_out[50]] ; ## U1,J10,IO_L05_34_JX4_P,JX4,31,IO_L05_34_JX4_P,P6,14
set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18} [get_ports gp_in[50]] ; ## U1,J8,IO_L06_34_JX4_P,JX4,32,IO_L06_34_JX4_P,P6,13
set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports gp_out[51]] ; ## U1,J9,IO_L05_34_JX4_N,JX4,33,IO_L05_34_JX4_N,P6,16
set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS18} [get_ports gp_in[51]] ; ## U1,H8,IO_L06_34_JX4_N,JX4,34,IO_L06_34_JX4_N,P6,15
set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS18} [get_ports gp_out[52]] ; ## U1,F5,IO_L07_34_JX4_P,JX4,35,IO_L07_34_JX4_P,P6,18
set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS18} [get_ports gp_in[52]] ; ## U1,D9,IO_L08_34_JX4_P,JX4,36,IO_L08_34_JX4_P,P6,17
set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS18} [get_ports gp_out[53]] ; ## U1,F8,IO_L11_SRCC_34_JX4_P,JX4,45,IO_L11_SRCC_34_JX4_P,P6,30
set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS18} [get_ports gp_in[53]] ; ## U1,G7,IO_L12_MRCC_34_JX4_P,JX4,46,IO_L12_MRCC_34_JX4_P,P6,29
set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18} [get_ports gp_out[54]] ; ## U1,E7,IO_L11_SRCC_34_JX4_N,JX4,47,IO_L11_SRCC_34_JX4_N,P6,32
set_property -dict {PACKAGE_PIN F7 IOSTANDARD LVCMOS18} [get_ports gp_in[54]] ; ## U1,F7,IO_L12_MRCC_34_JX4_N,JX4,48,IO_L12_MRCC_34_JX4_N,P6,31
set_property -dict {PACKAGE_PIN C8 IOSTANDARD LVCMOS18} [get_ports gp_out[55]] ; ## U1,C8,IO_L13_MRCC_34_JX4_P,JX4,51,IO_L13_MRCC_34_JX4_P,P7,2
set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS18} [get_ports gp_in[55]] ; ## U1,D6,IO_L14_SRCC_34_JX4_P,JX4,52,IO_L14_SRCC_34_JX4_P,P7,1
set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS18} [get_ports gp_out[56]] ; ## U1,C7,IO_L13_MRCC_34_JX4_N,JX4,53,IO_L13_MRCC_34_JX4_N,P7,4
set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS18} [get_ports gp_in[56]] ; ## U1,C6,IO_L14_SRCC_34_JX4_N,JX4,54,IO_L14_SRCC_34_JX4_N,P7,3
set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports gp_out[57]] ; ## U1,C9,IO_L15_34_JX4_P,JX4,57,IO_L15_34_JX4_P,P7,6
set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS18} [get_ports gp_in[57]] ; ## U1,B10,IO_L16_34_JX4_P,JX4,58,IO_L16_34_JX4_P,P7,5
set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports gp_out[58]] ; ## U1,B9,IO_L15_34_JX4_N,JX4,59,IO_L15_34_JX4_N,P7,8
set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS18} [get_ports gp_in[58]] ; ## U1,A10,IO_L16_34_JX4_N,JX4,60,IO_L16_34_JX4_N,P7,7
set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports gp_out[59]] ; ## U1,C4,IO_L19_34_JX4_P,JX4,73,IO_L19_34_JX4_P,P7,18
set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports gp_in[59]] ; ## U1,B5,IO_L20_34_JX4_P,JX4,74,IO_L20_34_JX4_P,P7,17
set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports gp_out[60]] ; ## U1,C3,IO_L19_34_JX4_N,JX4,75,IO_L19_34_JX4_N,P7,20
set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports gp_in[60]] ; ## U1,B4,IO_L20_34_JX4_N,JX4,76,IO_L20_34_JX4_N,P7,19
set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports gp_out[61]] ; ## U1,B6,IO_L21_34_JX4_P,JX4,77,IO_L21_34_JX4_P,P7,26
set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS18} [get_ports gp_in[61]] ; ## U1,A4,IO_L22_34_JX4_P,JX4,78,IO_L22_34_JX4_P,P7,25
set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports gp_out[62]] ; ## U1,A5,IO_L21_34_JX4_N,JX4,79,IO_L21_34_JX4_N,P7,28
set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS18} [get_ports gp_in[62]] ; ## U1,A3,IO_L22_34_JX4_N,JX4,80,IO_L22_34_JX4_N,P7,27
set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS18} [get_ports gp_out[63]] ; ## U1,B7,IO_L18_34_JX4_P,JX4,68,IO_L18_34_JX4_P,P7,30
set_property -dict {PACKAGE_PIN L9 IOSTANDARD LVCMOS18} [get_ports gp_in[63]] ; ## U1,L9,IO_00_33_JX1,JX1,9,IO_00_33_JX1,P7,29
set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVCMOS18} [get_ports gp_out[64]] ; ## U1,AD15,IO_L15_12_JX3_N,JX3,99,IO_L15_12_JX3_N,P13,6
set_property -dict {PACKAGE_PIN AF14 IOSTANDARD LVCMOS18} [get_ports gp_in[64]] ; ## U1,AF14,IO_L16_12_JX3_N,JX3,100,IO_L16_12_JX3_N,P13,5
set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVCMOS18} [get_ports gp_out[65]] ; ## U1,AD16,IO_L15_12_JX3_P,JX3,97,IO_L15_12_JX3_P,P13,8
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS18} [get_ports gp_in[65]] ; ## U1,AF15,IO_L16_12_JX3_P,JX3,98,IO_L16_12_JX3_P,P13,7
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS18} [get_ports gp_out[66]] ; ## U1,AD14,IO_L13_MRCC_12_JX3_N,JX3,93,IO_L13_MRCC_12_JX3_N,P13,10
set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVCMOS18} [get_ports gp_in[66]] ; ## U1,AB14,IO_L14_SRCC_12_JX3_N,JX3,94,IO_L14_SRCC_12_JX3_N,P13,9
set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVCMOS18} [get_ports gp_out[67]] ; ## U1,AC14,IO_L13_MRCC_12_JX3_P,JX3,91,IO_L13_MRCC_12_JX3_P,P13,12
set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS18} [get_ports gp_in[67]] ; ## U1,AB15,IO_L14_SRCC_12_JX3_P,JX3,92,IO_L14_SRCC_12_JX3_P,P13,11
set_property -dict {PACKAGE_PIN AD11 IOSTANDARD LVCMOS18} [get_ports gp_out[68]] ; ## U1,AD11,IO_L11_SRCC_12_JX3_N,JX3,87,IO_L11_SRCC_12_JX3_N,P13,14
set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS18} [get_ports gp_in[68]] ; ## U1,AD13,IO_L12_MRCC_12_JX3_N,JX3,88,IO_L12_MRCC_12_JX3_N,P13,13
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS18} [get_ports gp_out[69]] ; ## U1,AC12,IO_L11_SRCC_12_JX3_P,JX3,85,IO_L11_SRCC_12_JX3_P,P13,16
set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS18} [get_ports gp_in[69]] ; ## U1,AC13,IO_L12_MRCC_12_JX3_P,JX3,86,IO_L12_MRCC_12_JX3_P,P13,15
set_property -dict {PACKAGE_PIN AF10 IOSTANDARD LVCMOS18} [get_ports gp_out[70]] ; ## U1,AF10,IO_L09_12_JX3_N,JX3,81,IO_L09_12_JX3_N,P13,20
set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS18} [get_ports gp_in[70]] ; ## U1,AF13,IO_L10_12_JX3_N,JX3,82,IO_L10_12_JX3_N,P13,19
set_property -dict {PACKAGE_PIN AE11 IOSTANDARD LVCMOS18} [get_ports gp_out[71]] ; ## U1,AE11,IO_L09_12_JX3_P,JX3,79,IO_L09_12_JX3_P,P13,22
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS18} [get_ports gp_in[71]] ; ## U1,AE13,IO_L10_12_JX3_P,JX3,80,IO_L10_12_JX3_P,P13,21
set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVCMOS18} [get_ports gp_out[72]] ; ## U1,AD10,IO_L07_12_JX3_N,JX3,75,IO_L07_12_JX3_N,P13,24
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS18} [get_ports gp_in[72]] ; ## U1,AF12,IO_L08_12_JX3_N,JX3,76,IO_L08_12_JX3_N,P13,23
set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS18} [get_ports gp_out[73]] ; ## U1,AE10,IO_L07_12_JX3_P,JX3,73,IO_L07_12_JX3_P,P13,26
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS18} [get_ports gp_in[73]] ; ## U1,AE12,IO_L08_12_JX3_P,JX3,74,IO_L08_12_JX3_P,P13,25
set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS18} [get_ports gp_out[74]] ; ## U1,Y13,IO_L05_12_JX3_N,JX3,44,IO_L05_12_JX3_N,P13,28
set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS18} [get_ports gp_in[74]] ; ## U1,AA12,IO_L06_12_JX3_N,JX3,66,IO_L06_12_JX3_N,P13,27
set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS18} [get_ports gp_out[75]] ; ## U1,W13,IO_L05_12_JX3_P,JX3,42,IO_L05_12_JX3_P,P13,30
set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVCMOS18} [get_ports gp_in[75]] ; ## U1,AA13,IO_L06_12_JX3_P,JX3,64,IO_L06_12_JX3_P,P13,29
set_property -dict {PACKAGE_PIN AA10 IOSTANDARD LVCMOS18} [get_ports gp_out[76]] ; ## U1,AA10,IO_L03_12_JX3_N,JX3,28,IO_L03_12_JX3_N,P13,32
set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS18} [get_ports gp_in[76]] ; ## U1,AB10,IO_L04_12_JX3_N,JX3,33,IO_L04_12_JX3_N,P13,31
set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS18} [get_ports gp_out[77]] ; ## U1,Y10,IO_L03_12_JX3_P,JX3,26,IO_L03_12_JX3_P,P13,34
set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS18} [get_ports gp_in[77]] ; ## U1,AB11,IO_L04_12_JX3_P,JX3,31,IO_L04_12_JX3_P,P13,33
set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS18} [get_ports gp_out[78]] ; ## U1,Y11,IO_L01_12_JX3_N,JX3,22,IO_L01_12_JX3_N,P13,36
set_property -dict {PACKAGE_PIN AC11 IOSTANDARD LVCMOS18} [get_ports gp_in[78]] ; ## U1,AC11,IO_L02_12_JX3_N,JX3,27,IO_L02_12_JX3_N,P13,35
set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS18} [get_ports gp_out[79]] ; ## U1,Y12,IO_L01_12_JX3_P,JX3,20,IO_L01_12_JX3_P,P13,38
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS18} [get_ports gp_in[79]] ; ## U1,AB12,IO_L02_12_JX3_P,JX3,25,IO_L02_12_JX3_P,P13,37
set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVCMOS18} [get_ports gp_out[80]] ; ## U1,AE16,IO_L17_12_JX2_P,JX2,82,IO_L17_12_JX2_P,P13,42
set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS18} [get_ports gp_in[80]] ; ## U1,AE17,IO_L18_12_JX2_P,JX2,81,IO_L18_12_JX2_P,P13,41
set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS18} [get_ports gp_out[81]] ; ## U1,AE15,IO_L17_12_JX2_N,JX2,84,IO_L17_12_JX2_N,P13,44
set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVCMOS18} [get_ports gp_in[81]] ; ## U1,AF17,IO_L18_12_JX2_N,JX2,83,IO_L18_12_JX2_N,P13,43
set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS18} [get_ports gp_out[82]] ; ## U1,Y17,IO_L19_12_JX2_P,JX2,88,IO_L19_12_JX2_P,P13,46
set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS18} [get_ports gp_in[82]] ; ## U1,AB17,IO_L20_12_JX2_P,JX2,87,IO_L20_12_JX2_P,P13,45
set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVCMOS18} [get_ports gp_out[83]] ; ## U1,AA17,IO_L19_12_JX2_N,JX2,90,IO_L19_12_JX2_N,P13,48
set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS18} [get_ports gp_in[83]] ; ## U1,AB16,IO_L20_12_JX2_N,JX2,89,IO_L20_12_JX2_N,P13,47
set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVCMOS18} [get_ports gp_out[84]] ; ## U1,AC17,IO_L21_12_JX2_P,JX2,93,IO_L21_12_JX2_P,P13,50
set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS18} [get_ports gp_in[84]] ; ## U1,AA15,IO_L22_12_JX2_P,JX2,94,IO_L22_12_JX2_P,P13,49
set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVCMOS18} [get_ports gp_out[85]] ; ## U1,AC16,IO_L21_12_JX2_N,JX2,95,IO_L21_12_JX2_N,P13,52
set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS18} [get_ports gp_in[85]] ; ## U1,AA14,IO_L22_12_JX2_N,JX2,96,IO_L22_12_JX2_N,P13,51
## transceiver loop-backs (on-ccbrk)
set_property -dict {PACKAGE_PIN R6} [get_ports gt_ref_clk_p] ; ## U1,R6,MGTREFCLK0_112_JX1_P (JX1,87)
set_property -dict {PACKAGE_PIN R5} [get_ports gt_ref_clk_n] ; ## U1,R5,MGTREFCLK0_112_JX1_N (JX1,89)
set_property -dict {PACKAGE_PIN AB4} [get_ports gt_rx_p[0]] ; ## U1,AB4,MGTXRX0_112_JX1_P (JX1,88)
set_property -dict {PACKAGE_PIN AB3} [get_ports gt_rx_n[0]] ; ## U1,AB3,MGTXRX0_112_JX1_N (JX1,90)
set_property -dict {PACKAGE_PIN Y4} [get_ports gt_rx_p[1]] ; ## U1,Y4,MGTXRX1_112_JX1_P (JX1,91)
set_property -dict {PACKAGE_PIN Y3} [get_ports gt_rx_n[1]] ; ## U1,Y3,MGTXRX1_112_JX1_N (JX1,93)
set_property -dict {PACKAGE_PIN V4} [get_ports gt_rx_p[2]] ; ## U1,V4,MGTXRX2_112_JX1_P (JX1,92)
set_property -dict {PACKAGE_PIN V3} [get_ports gt_rx_n[2]] ; ## U1,V3,MGTXRX2_112_JX1_N (JX1,94)
set_property -dict {PACKAGE_PIN T4} [get_ports gt_rx_p[3]] ; ## U1,T4,MGTXRX3_112_JX1_P (JX1,97)
set_property -dict {PACKAGE_PIN T3} [get_ports gt_rx_n[3]] ; ## U1,T3,MGTXRX3_112_JX1_N (JX1,99)
set_property -dict {PACKAGE_PIN AA2} [get_ports gt_tx_p[0]] ; ## U1,AA2,MGTXTX0_112_JX3_P (JX3,8)
set_property -dict {PACKAGE_PIN AA1} [get_ports gt_tx_n[0]] ; ## U1,AA1,MGTXTX0_112_JX3_N (JX3,10)
set_property -dict {PACKAGE_PIN W2} [get_ports gt_tx_p[1]] ; ## U1,W2,MGTXTX1_112_JX3_P (JX3,13)
set_property -dict {PACKAGE_PIN W1} [get_ports gt_tx_n[1]] ; ## U1,W1,MGTXTX1_112_JX3_N (JX3,15)
set_property -dict {PACKAGE_PIN U2} [get_ports gt_tx_p[2]] ; ## U1,U2,MGTXTX2_112_JX3_P (JX3,14)
set_property -dict {PACKAGE_PIN U1} [get_ports gt_tx_n[2]] ; ## U1,U1,MGTXTX2_112_JX3_N (JX3,16)
set_property -dict {PACKAGE_PIN R2} [get_ports gt_tx_p[3]] ; ## U1,R2,MGTXTX3_112_JX3_P (JX3,19)
set_property -dict {PACKAGE_PIN R1} [get_ports gt_tx_n[3]] ; ## U1,R1,MGTXTX3_112_JX3_N (JX3,21)
## clocks
create_clock -name ref_clk -period 4.00 [get_ports gt_ref_clk_p]
create_clock -name xcvr_clk_0 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[0].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
create_clock -name xcvr_clk_1 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[1].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
create_clock -name xcvr_clk_2 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[2].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
create_clock -name xcvr_clk_3 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[3].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]

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projects/pzsdr2/common/pzsdr2_bd.tcl Normal file
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# create board design
# default ports
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main
create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
create_bd_port -dir O spi0_csn_2_o
create_bd_port -dir O spi0_csn_1_o
create_bd_port -dir O spi0_csn_0_o
create_bd_port -dir I spi0_csn_i
create_bd_port -dir I spi0_clk_i
create_bd_port -dir O spi0_clk_o
create_bd_port -dir I spi0_sdo_i
create_bd_port -dir O spi0_sdo_o
create_bd_port -dir I spi0_sdi_i
create_bd_port -dir O spi1_csn_2_o
create_bd_port -dir O spi1_csn_1_o
create_bd_port -dir O spi1_csn_0_o
create_bd_port -dir I spi1_csn_i
create_bd_port -dir I spi1_clk_i
create_bd_port -dir O spi1_clk_o
create_bd_port -dir I spi1_sdo_i
create_bd_port -dir O spi1_sdo_o
create_bd_port -dir I spi1_sdi_i
create_bd_port -dir I -from 63 -to 0 gpio_i
create_bd_port -dir O -from 63 -to 0 gpio_o
create_bd_port -dir O -from 63 -to 0 gpio_t
# otg
set otg_vbusoc [create_bd_port -dir I otg_vbusoc]
# interrupts
create_bd_port -dir I -type intr ps_intr_00
create_bd_port -dir I -type intr ps_intr_01
create_bd_port -dir I -type intr ps_intr_02
create_bd_port -dir I -type intr ps_intr_03
create_bd_port -dir I -type intr ps_intr_04
create_bd_port -dir I -type intr ps_intr_05
create_bd_port -dir I -type intr ps_intr_06
create_bd_port -dir I -type intr ps_intr_07
create_bd_port -dir I -type intr ps_intr_08
create_bd_port -dir I -type intr ps_intr_09
create_bd_port -dir I -type intr ps_intr_10
create_bd_port -dir I -type intr ps_intr_11
create_bd_port -dir I -type intr ps_intr_12
create_bd_port -dir I -type intr ps_intr_13
create_bd_port -dir I -type intr ps_intr_15
# instance: sys_ps7
set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
set_property -dict [list CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V}] $sys_ps7
set_property -dict [list CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V}] $sys_ps7
set_property -dict [list CONFIG.PCW_PACKAGE_NAME {fbg676}] $sys_ps7
set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27}] $sys_ps7
set_property -dict [list CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_ENET_RESET_SELECT {Separate reset pins}] $sys_ps7
set_property -dict [list CONFIG.PCW_ENET0_RESET_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_ENET0_RESET_IO {MIO 8}] $sys_ps7
set_property -dict [list CONFIG.PCW_ENET1_RESET_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_ENET1_RESET_IO {MIO 51}] $sys_ps7
set_property -dict [list CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_SD0_GRP_CD_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_SD0_GRP_CD_IO {MIO 50}] $sys_ps7
set_property -dict [list CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50}] $sys_ps7
set_property -dict [list CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_USB0_RESET_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_USB0_RESET_IO {MIO 7}] $sys_ps7
set_property -dict [list CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125}] $sys_ps7
set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit}] $sys_ps7
set_property -dict [list CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0}] $sys_ps7
set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {-0.053}] $sys_ps7
set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {-0.059}] $sys_ps7
set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.065}] $sys_ps7
set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.066}] $sys_ps7
set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.264}] $sys_ps7
set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.265}] $sys_ps7
set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.330}] $sys_ps7
set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.330}] $sys_ps7
set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7
set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7
set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_iic_main
set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_main
set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
set sys_logic_inv [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 sys_logic_inv]
set_property -dict [list CONFIG.C_SIZE {1}] $sys_logic_inv
set_property -dict [list CONFIG.C_OPERATION {not}] $sys_logic_inv
# system reset/clock definitions
ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0
ad_connect sys_200m_clk sys_ps7/FCLK_CLK1
ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
# interface connections
ad_connect ddr sys_ps7/DDR
ad_connect gpio_i sys_ps7/GPIO_I
ad_connect gpio_o sys_ps7/GPIO_O
ad_connect gpio_t sys_ps7/GPIO_T
ad_connect fixed_io sys_ps7/FIXED_IO
ad_connect iic_main axi_iic_main/iic
ad_connect sys_logic_inv/Res sys_ps7/USB0_VBUS_PWRFAULT
ad_connect sys_logic_inv/Op1 otg_vbusoc
# spi connections
ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O
ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O
ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O
ad_connect spi0_csn_i sys_ps7/SPI0_SS_I
ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I
ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O
ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I
ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O
ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I
ad_connect spi1_csn_2_o sys_ps7/SPI1_SS2_O
ad_connect spi1_csn_1_o sys_ps7/SPI1_SS1_O
ad_connect spi1_csn_0_o sys_ps7/SPI1_SS_O
ad_connect spi1_csn_i sys_ps7/SPI1_SS_I
ad_connect spi1_clk_i sys_ps7/SPI1_SCLK_I
ad_connect spi1_clk_o sys_ps7/SPI1_SCLK_O
ad_connect spi1_sdo_i sys_ps7/SPI1_MOSI_I
ad_connect spi1_sdo_o sys_ps7/SPI1_MOSI_O
ad_connect spi1_sdi_i sys_ps7/SPI1_MISO_I
# interrupts
ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P
ad_connect sys_concat_intc/In15 ps_intr_15
ad_connect sys_concat_intc/In14 axi_iic_main/iic2intc_irpt
ad_connect sys_concat_intc/In13 ps_intr_13
ad_connect sys_concat_intc/In12 ps_intr_12
ad_connect sys_concat_intc/In11 ps_intr_11
ad_connect sys_concat_intc/In10 ps_intr_10
ad_connect sys_concat_intc/In9 ps_intr_09
ad_connect sys_concat_intc/In8 ps_intr_08
ad_connect sys_concat_intc/In7 ps_intr_07
ad_connect sys_concat_intc/In6 ps_intr_06
ad_connect sys_concat_intc/In5 ps_intr_05
ad_connect sys_concat_intc/In4 ps_intr_04
ad_connect sys_concat_intc/In3 ps_intr_03
ad_connect sys_concat_intc/In2 ps_intr_02
ad_connect sys_concat_intc/In1 ps_intr_01
ad_connect sys_concat_intc/In0 ps_intr_00
# interconnects
ad_cpu_interconnect 0x41600000 axi_iic_main
# ad9361
create_bd_port -dir O enable
create_bd_port -dir O txnrx
create_bd_port -dir I up_enable
create_bd_port -dir I up_txnrx
create_bd_port -dir O tdd_sync_o
create_bd_port -dir I tdd_sync_i
create_bd_port -dir O tdd_sync_t
# ad9361 core
set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361]
set_property -dict [list CONFIG.ID {0}] $axi_ad9361
set_property -dict [list CONFIG.DAC_IODELAY_ENABLE {1}] $axi_ad9361
set axi_ad9361_dac_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_dac_dma]
set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9361_dac_dma
set util_ad9361_dac_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_ad9361_dac_upack]
set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9361_dac_upack
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9361_dac_upack
set axi_ad9361_adc_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_adc_dma]
set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9361_adc_dma
set util_ad9361_adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9361_adc_pack]
set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9361_adc_pack
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9361_adc_pack
set util_ad9361_adc_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_wfifo:1.0 util_ad9361_adc_fifo]
set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9361_adc_fifo
set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $util_ad9361_adc_fifo
set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $util_ad9361_adc_fifo
set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $util_ad9361_adc_fifo
set util_ad9361_tdd_sync [create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync]
set_property -dict [list CONFIG.TDD_SYNC_PERIOD {10000000}] $util_ad9361_tdd_sync
# connections
ad_connect sys_200m_clk axi_ad9361/delay_clk
ad_connect axi_ad9361_clk axi_ad9361/l_clk
ad_connect axi_ad9361_clk axi_ad9361/clk
ad_connect enable axi_ad9361/enable
ad_connect txnrx axi_ad9361/txnrx
ad_connect up_enable axi_ad9361/up_enable
ad_connect up_txnrx axi_ad9361/up_txnrx
ad_connect axi_ad9361_clk util_ad9361_adc_fifo/din_clk
ad_connect axi_ad9361/rst util_ad9361_adc_fifo/din_rst
ad_connect sys_cpu_clk util_ad9361_adc_fifo/dout_clk
ad_connect sys_cpu_resetn util_ad9361_adc_fifo/dout_rstn
ad_connect sys_cpu_clk util_ad9361_adc_pack/adc_clk
ad_connect sys_cpu_reset util_ad9361_adc_pack/adc_rst
ad_connect sys_cpu_clk axi_ad9361_adc_dma/fifo_wr_clk
ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0
ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0
ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0
ad_connect axi_ad9361/adc_enable_q0 util_ad9361_adc_fifo/din_enable_1
ad_connect axi_ad9361/adc_valid_q0 util_ad9361_adc_fifo/din_valid_1
ad_connect axi_ad9361/adc_data_q0 util_ad9361_adc_fifo/din_data_1
ad_connect axi_ad9361/adc_enable_i1 util_ad9361_adc_fifo/din_enable_2
ad_connect axi_ad9361/adc_valid_i1 util_ad9361_adc_fifo/din_valid_2
ad_connect axi_ad9361/adc_data_i1 util_ad9361_adc_fifo/din_data_2
ad_connect axi_ad9361/adc_enable_q1 util_ad9361_adc_fifo/din_enable_3
ad_connect axi_ad9361/adc_valid_q1 util_ad9361_adc_fifo/din_valid_3
ad_connect axi_ad9361/adc_data_q1 util_ad9361_adc_fifo/din_data_3
ad_connect util_ad9361_adc_fifo/dout_enable_0 util_ad9361_adc_pack/adc_enable_0
ad_connect util_ad9361_adc_fifo/dout_valid_0 util_ad9361_adc_pack/adc_valid_0
ad_connect util_ad9361_adc_fifo/dout_data_0 util_ad9361_adc_pack/adc_data_0
ad_connect util_ad9361_adc_fifo/dout_enable_1 util_ad9361_adc_pack/adc_enable_1
ad_connect util_ad9361_adc_fifo/dout_valid_1 util_ad9361_adc_pack/adc_valid_1
ad_connect util_ad9361_adc_fifo/dout_data_1 util_ad9361_adc_pack/adc_data_1
ad_connect util_ad9361_adc_fifo/dout_enable_2 util_ad9361_adc_pack/adc_enable_2
ad_connect util_ad9361_adc_fifo/dout_valid_2 util_ad9361_adc_pack/adc_valid_2
ad_connect util_ad9361_adc_fifo/dout_data_2 util_ad9361_adc_pack/adc_data_2
ad_connect util_ad9361_adc_fifo/dout_enable_3 util_ad9361_adc_pack/adc_enable_3
ad_connect util_ad9361_adc_fifo/dout_valid_3 util_ad9361_adc_pack/adc_valid_3
ad_connect util_ad9361_adc_fifo/dout_data_3 util_ad9361_adc_pack/adc_data_3
ad_connect util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en
ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync
ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din
ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf
ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf
ad_connect axi_ad9361_clk util_ad9361_dac_upack/dac_clk
ad_connect axi_ad9361_clk axi_ad9361_dac_dma/fifo_rd_clk
ad_connect util_ad9361_dac_upack/dac_enable_0 axi_ad9361/dac_enable_i0
ad_connect util_ad9361_dac_upack/dac_valid_0 axi_ad9361/dac_valid_i0
ad_connect util_ad9361_dac_upack/dac_data_0 axi_ad9361/dac_data_i0
ad_connect util_ad9361_dac_upack/dac_enable_1 axi_ad9361/dac_enable_q0
ad_connect util_ad9361_dac_upack/dac_valid_1 axi_ad9361/dac_valid_q0
ad_connect util_ad9361_dac_upack/dac_data_1 axi_ad9361/dac_data_q0
ad_connect util_ad9361_dac_upack/dac_enable_2 axi_ad9361/dac_enable_i1
ad_connect util_ad9361_dac_upack/dac_valid_2 axi_ad9361/dac_valid_i1
ad_connect util_ad9361_dac_upack/dac_data_2 axi_ad9361/dac_data_i1
ad_connect util_ad9361_dac_upack/dac_enable_3 axi_ad9361/dac_enable_q1
ad_connect util_ad9361_dac_upack/dac_valid_3 axi_ad9361/dac_valid_q1
ad_connect util_ad9361_dac_upack/dac_data_3 axi_ad9361/dac_data_q1
ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout
ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf
ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk
ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn
ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync
ad_connect util_ad9361_tdd_sync/sync_mode axi_ad9361/tdd_sync_cntr
ad_connect tdd_sync_t axi_ad9361/tdd_sync_cntr
ad_connect tdd_sync_o util_ad9361_tdd_sync/sync_out
ad_connect tdd_sync_i util_ad9361_tdd_sync/sync_in
# interconnects
ad_cpu_interconnect 0x79020000 axi_ad9361
ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma
ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma
ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi
ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi
ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn
ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn
# interrupts
ad_cpu_interrupt ps-13 mb-13 axi_ad9361_adc_dma/irq
ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq
## customization of core to disable data path logic (less resources)
## interface type - 1R1T (1) or 2R2T (0) (default is 2R2T)
## 2R2T supports 1R1T as a run time option.
## 1R1T allows core to run at a lower rate (1/2 of 2R2T)
set_property CONFIG.MODE_1R1T 0 [get_bd_cells axi_ad9361]
## interface type - CMOS (1) or LVDS (0) (default is LVDS)
## CMOS allows core to run at a lower rate (1/2 of LVDS)
set_property CONFIG.CMOS_OR_LVDS_N 0 [get_bd_cells axi_ad9361]
## data-path disable (global control)- allows removal of DSP functions within the core.
## also removes the corresponding AXI control interface registers
set_property CONFIG.ADC_DATAPATH_DISABLE 0 [get_bd_cells axi_ad9361]
set_property CONFIG.DAC_DATAPATH_DISABLE 0 [get_bd_cells axi_ad9361]
## data-path disable (individual control)- effective ONLY if DATAPATH_DISABLE is 0x0.
set_property CONFIG.ADC_DATAFORMAT_DISABLE 0 [get_bd_cells axi_ad9361]
set_property CONFIG.ADC_DCFILTER_DISABLE 0 [get_bd_cells axi_ad9361]
set_property CONFIG.ADC_IQCORRECTION_DISABLE 0 [get_bd_cells axi_ad9361]
set_property CONFIG.ADC_USERPORTS_DISABLE 0 [get_bd_cells axi_ad9361]
set_property CONFIG.DAC_DDS_DISABLE 0 [get_bd_cells axi_ad9361]
set_property CONFIG.DAC_IQCORRECTION_DISABLE 0 [get_bd_cells axi_ad9361]
set_property CONFIG.DAC_USERPORTS_DISABLE 0 [get_bd_cells axi_ad9361]
## tdd-disable (control is moved exclusively to GPIO)
set_property CONFIG.TDD_DISABLE 0 [get_bd_cells axi_ad9361]

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# constraints (pzsdr2.e)
# ad9361
set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18} [get_ports enable] ; ## IO_L11P_T1_SRCC_35 U1,G14,IO_L11_35_ENABLE
set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS18} [get_ports txnrx] ; ## IO_L11N_T1_SRCC_35 U1,F14,IO_L11_35_TXNRX
set_property -dict {PACKAGE_PIN D13 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]] ; ## IO_L19P_T3_35 U1,D13,IO_L19_35_CTRL_OUT0
set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]] ; ## IO_L19N_T3_VREF_35 U1,C13,IO_L19_35_CTRL_OUT1
set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS18} [get_ports gpio_status[2]] ; ## IO_L20P_T3_AD6P_35 U1,C14,IO_L20_35_CTRL_OUT2
set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS18} [get_ports gpio_status[3]] ; ## IO_L20N_T3_AD6N_35 U1,B14,IO_L20_35_CTRL_OUT3
set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS18} [get_ports gpio_status[4]] ; ## IO_L21P_T3_DQS_AD14P_35 U1,A15,IO_L21_35_CTRL_OUT4
set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS18} [get_ports gpio_status[5]] ; ## IO_L21N_T3_DQS_AD14N_35 U1,A14,IO_L21_35_CTRL_OUT5
set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports gpio_status[6]] ; ## IO_L22P_T3_AD7P_35 U1,C12,IO_L22_35_CTRL_OUT6
set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS18} [get_ports gpio_status[7]] ; ## IO_L22N_T3_AD7N_35 U1,B12,IO_L22_35_CTRL_OUT7
set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]] ; ## IO_L23P_T3_34 U1,C2,IO_L23_34_CTRL_IN0
set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]] ; ## IO_L23N_T3_34 U1,B1,IO_L23_34_CTRL_IN1
set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]] ; ## IO_L24P_T3_34 U1,B2,IO_L24_34_CTRL_IN2
set_property -dict {PACKAGE_PIN A2 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]] ; ## IO_L24N_T3_34 U1,A2,IO_L24_34_CTRL_IN3
set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc] ; ## IO_L10P_T1_AD11P_35 U1,G16,IO_L10_35_EN_AGC
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports gpio_sync] ; ## IO_L10N_T1_AD11N_35 U1,G15,IO_L10_35_SYNC_IN
set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS18} [get_ports gpio_resetb] ; ## IO_0_VRN_35 U1,H16,IO_00_35_AD9361_RST
set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports gpio_clksel] ; ## IO_0_VRN_34 U1,K11,IO_00_34_AD9361_CLKSEL
set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn] ; ## IO_L23P_T3_35 U1,C11,IO_L23_35_SPI_ENB
set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## IO_L23N_T3_35 U1,B11,IO_L23_35_SPI_CLK
set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ; ## IO_L24P_T3_AD15P_35 U1,A13,IO_L24_35_SPI_DI
set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS18} [get_ports spi_miso] ; ## IO_L24N_T3_AD15N_35 U1,A12,IO_L24_35_SPI_DO
set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18} [get_ports clkout_in] ; ## IO_25_VRP_35 U1,K12,IO_25_35_AD9361_CLKOUT
# iic (ccbrk with loopback drives i2c back to the FPGA)
set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_scl] ; ## IO_L5P_T0_13 U1,AF24,SCL,JX2,17,I2C_SCL,P2,14,P2,4,U1,Y16,IO_L23_12_JX2_P,JX2,97,LED_GPIO_3,P2,4
set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_sda] ; ## IO_L5N_T0_13 U1,AF25,SDA,JX2,19,I2C_SDA,P2,16,P2,15,U1,AB24,IO_L06_13_JX2_N,JX2,20,IO_L06_13_JX2_N,P2,15
## reference-only
## --------------
## ad9361 (optional rf-card)
## --------------------------
## JX4,1,GPO0
## JX4,2,GPO1
## JX4,3,GPO2
## JX4,4,GPO3
## JX4,7,AUXADC
## JX4,8,AUXDAC1
## JX4,10,AUXDAC2
## JX4,63,AD9361_CLK
## fixed-io (ps7) (som only, others are carrier specific)
## ------------------------------------------------------
## U1,D26,PS_MIO01_500_QSPI0_SS_B
## U1,F23,PS_MIO06_500_QSPI0_SCLK
## U1,E25,PS_MIO02_500_QSPI0_IO0
## U1,D25,PS_MIO03_500_QSPI0_IO1
## U1,F24,PS_MIO04_500_QSPI0_IO2
## U1,C26,PS_MIO05_500_QSPI0_IO3
## U1,A24,PS_MIO08_500_ETH0_RESETN (magnetics-RJ45- JX3,47,ETH_PHY_LED0)
## U1,A19,PS_MIO53_501_ETH0_MDIO (magnetics-RJ45- JX3,48,ETH_PHY_LED1)
## U1,A20,PS_MIO52_501_ETH0_MDC (magnetics-RJ45- JX3,51,ETH_MD1_P)
## U1,G22,PS_MIO22_501_ETH0_RX_CLK (magnetics-RJ45- JX3,53,ETH_MD1_N)
## U1,F18,PS_MIO27_501_ETH0_RX_CTL (magnetics-RJ45- JX3,52,ETH_MD2_P)
## U1,F20,PS_MIO23_501_ETH0_RX_D0 (magnetics-RJ45- JX3,54,ETH_MD2_N)
## U1,J19,PS_MIO24_501_ETH0_RX_D1 (magnetics-RJ45- JX3,57,ETH_MD3_P)
## U1,F19,PS_MIO25_501_ETH0_RX_D2 (magnetics-RJ45- JX3,59,ETH_MD3_N)
## U1,H17,PS_MIO26_501_ETH0_RX_D3 (magnetics-RJ45- JX3,58,ETH_MD4_P)
## U1,G21,PS_MIO16_501_ETH0_TX_CLK (magnetics-RJ45- JX3,60,ETH_MD4_N)
## U1,F22,PS_MIO21_501_ETH0_TX_CTL
## U1,G17,PS_MIO17_501_ETH0_TX_D0
## U1,G20,PS_MIO18_501_ETH0_TX_D1
## U1,G19,PS_MIO19_501_ETH0_TX_D2
## U1,H19,PS_MIO20_501_ETH0_TX_D3
## U1,B21,PS_MIO48_501_JX4,JX4,99,USB_UART_RXD
## U1,A18,PS_MIO49_501_JX4,JX4,98,USB_UART_TXD
## U1,C22,PS_MIO40_501_SD0_CLK (off-board- JX3,43,SDIO_CLKB1)
## U1,C19,PS_MIO41_501_SD0_CMD (off-board- JX3,34,SDIO_CMDB1)
## U1,F17,PS_MIO42_501_SD0_DATA0 (off-board- JX3,37,SDIO_DAT0B1)
## U1,D18,PS_MIO43_501_SD0_DATA1 (off-board- JX3,36,SDIO_DAT1B1)
## U1,E18,PS_MIO44_501_SD0_DATA2 (off-board- JX3,39,SDIO_DAT2B1)
## U1,C18,PS_MIO45_501_SD0_DATA3 (off-board- JX3,38,SDIO_DAT3B1)
## U1,B22,PS_MIO50_501_SD0_CD (off-board- JX3,41,JX3_SD1_CDN)
## U1,E23,PS_MIO07_500_USB_RESET_B (usb- JX3,63,USB_ID)
## U1,D24,PS_MIO09_500_USB_CLK_PD (usb- JX3,67,USB_OTG_P)
## U1,E20,PS_MIO29_501_USB0_DIR (usb- JX3,69,USB_OTG_N)
## U1,K19,PS_MIO30_501_USB0_STP (usb- JX3,68,USB_VBUS_OTG)
## U1,E21,PS_MIO31_501_USB0_NXT (usb- JX3,70,USB_OTG_CPEN)
## U1,K16,PS_MIO36_501_USB0_CLK
## U1,K17,PS_MIO32_501_USB0_D0
## U1,E22,PS_MIO33_501_USB0_D1
## U1,J16,PS_MIO34_501_USB0_D2
## U1,D19,PS_MIO35_501_USB0_D3
## U1,J18,PS_MIO28_501_USB0_D4
## U1,D20,PS_MIO37_501_USB0_D5
## U1,D21,PS_MIO38_501_USB0_D6
## U1,C21,PS_MIO39_501_USB0_D7
## U1,A23,UNNAMED_3_ICXC7Z035_I94_PSMIO12 (JX4,86,PS_MIO12_500_JX4)
## ddr (fixed-io)
## --------------
## U1,H24,DDR3_DQS0_P
## U1,G25,DDR3_DQS0_N
## U1,L24,DDR3_DQS1_P
## U1,L25,DDR3_DQS1_N
## U1,P25,DDR3_DQS2_P
## U1,R25,DDR3_DQS2_N
## U1,W24,DDR3_DQS3_P
## U1,W25,DDR3_DQS3_N
## U1,J26,DDR3_DQ0
## U1,F25,DDR3_DQ1
## U1,J25,DDR3_DQ2
## U1,G26,DDR3_DQ3
## U1,H26,DDR3_DQ4
## U1,H23,DDR3_DQ5
## U1,J24,DDR3_DQ6
## U1,J23,DDR3_DQ7
## U1,K26,DDR3_DQ8
## U1,L23,DDR3_DQ9
## U1,M26,DDR3_DQ10
## U1,K23,DDR3_DQ11
## U1,M25,DDR3_DQ12
## U1,N24,DDR3_DQ13
## U1,M24,DDR3_DQ14
## U1,N23,DDR3_DQ15
## U1,R26,DDR3_DQ16
## U1,P24,DDR3_DQ17
## U1,N26,DDR3_DQ18
## U1,P23,DDR3_DQ19
## U1,T24,DDR3_DQ20
## U1,T25,DDR3_DQ21
## U1,T23,DDR3_DQ22
## U1,R23,DDR3_DQ23
## U1,V24,DDR3_DQ24
## U1,U26,DDR3_DQ25
## U1,U24,DDR3_DQ26
## U1,U25,DDR3_DQ27
## U1,W26,DDR3_DQ28
## U1,Y25,DDR3_DQ29
## U1,Y26,DDR3_DQ30
## U1,W23,DDR3_DQ31
## U1,G24,DDR3_DM0
## U1,K25,DDR3_DM1
## U1,P26,DDR3_DM2
## U1,V26,DDR3_DM3
## U1,K22,DDR3_A0
## U1,K20,DDR3_A1
## U1,N21,DDR3_A2
## U1,L22,DDR3_A3
## U1,M20,DDR3_A4
## U1,N22,DDR3_A5
## U1,L20,DDR3_A6
## U1,J21,DDR3_A7
## U1,T20,DDR3_A8
## U1,U20,DDR3_A9
## U1,M22,DDR3_A10
## U1,H21,DDR3_A11
## U1,P20,DDR3_A12
## U1,J20,DDR3_A13
## U1,R20,DDR3_A14
## U1,U22,DDR3_BA0
## U1,T22,DDR3_BA1
## U1,R22,DDR3_BA2
## U1,R21,DDR3_CK_P
## U1,P21,DDR3_CK_N
## U1,U21,DDR3_CKE
## U1,H22,DDR3_RST#
## U1,Y21,DDR3_CS#
## U1,V22,DDR3_WE#
## U1,V23,DDR3_RAS#
## U1,Y23,DDR3_CAS#
## U1,Y22,DDR3_ODT
## resets, clock and power controls
## --------------------------------
## U1,B24,UNNAMED_3_ICXC7Z035_I94_PSCLK50,33.33MEGHZ
## U1,A22,PS-SRST#
## U1,C23,PWR_GD_1.35V
## JX2,10,PG_1P8V
## JX2,11,PG_MODULE
## JX1,5,PWR_ENABLE
## JX1,6,CARRIER_RESET
## JTAG
## ----
## U1,W11,JTAG_TMS,JX1,2,JTAG_TMS
## U1,W12,JTAG_TCK,JX1,1,JTAG_TCK
## U1,V11,JTAG_TDI,JX1,4,FPGA_TDI,JTAG_TDI
## U1,W9,FPGA_DONE,JX1,8,CFG_DONE
## GBT I/O (clocks)
## ----------------
## U1,R5,UNNAMED_7_CAP_I125_N2 (JX1,87,MGTREFCLK0_112_JX1_P)
## U1,R6,UNNAMED_7_CAP_I123_N2 (JX1,89,MGTREFCLK0_112_JX1_N)
## U1,U6,UNNAMED_7_CAP_I126_N2 (JX3,2,MGTREFCLK1_112_JX3_P)
## U1,U5,UNNAMED_7_CAP_I124_N2 (JX3,4,MGTREFCLK1_112_JX3_N)

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# constraints (pzsdr2.e)
# ad9361 (SWAP == 0x1)
set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18} [get_ports rx_clk_in] ; ## IO_L12P_T1_MRCC_35 U1,J14,IO_L12_MRCC_35_DATA_CLK_P
set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS18} [get_ports rx_frame_in] ; ## IO_L7P_T1_AD2P_35 U1,H13,IO_L07_35_RX_FRAME_P
set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS18} [get_ports rx_data_in[0]] ; ## IO_L1N_T0_AD0N_35 U1,E12,IO_L01_35_RX_D0_N
set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports rx_data_in[1]] ; ## IO_L1P_T0_AD0P_35 U1,F12,IO_L01_35_RX_D0_P
set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS18} [get_ports rx_data_in[2]] ; ## IO_L2N_T0_AD8N_35 U1,D10,IO_L02_35_RX_D1_N
set_property -dict {PACKAGE_PIN E10 IOSTANDARD LVCMOS18} [get_ports rx_data_in[3]] ; ## IO_L2P_T0_AD8P_35 U1,E10,IO_L02_35_RX_D1_P
set_property -dict {PACKAGE_PIN F10 IOSTANDARD LVCMOS18} [get_ports rx_data_in[4]] ; ## IO_L3N_T0_DQS_AD1N_35 U1,F10,IO_L03_35_RX_D2_N
set_property -dict {PACKAGE_PIN G10 IOSTANDARD LVCMOS18} [get_ports rx_data_in[5]] ; ## IO_L3P_T0_DQS_AD1P_35 U1,G10,IO_L03_35_RX_D2_P
set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVCMOS18} [get_ports rx_data_in[6]] ; ## IO_L4N_T0_35 U1,D11,IO_L04_35_RX_D3_N
set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS18} [get_ports rx_data_in[7]] ; ## IO_L4P_T0_35 U1,E11,IO_L04_35_RX_D3_P
set_property -dict {PACKAGE_PIN G11 IOSTANDARD LVCMOS18} [get_ports rx_data_in[8]] ; ## IO_L5N_T0_AD9N_35 U1,G11,IO_L05_35_RX_D4_N
set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVCMOS18} [get_ports rx_data_in[9]] ; ## IO_L5P_T0_AD9P_35 U1,G12,IO_L05_35_RX_D4_P
set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS18} [get_ports rx_data_in[10]] ; ## IO_L6N_T0_VREF_35 U1,E13,IO_L06_35_RX_D5_N
set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS18} [get_ports rx_data_in[11]] ; ## IO_L6P_T0_35 U1,F13,IO_L06_35_RX_D5_P
set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports tx_clk_out] ; ## IO_L8P_T1_AD10P_35 U1,K13,IO_L08_35_FB_CLK_P
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports tx_frame_out] ; ## IO_L9P_T1_DQS_AD3P_35 U1,K15,IO_L09_35_TX_FRAME_P
set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]] ; ## IO_L13N_T2_MRCC_35 U1,D14,IO_L13_35_TX_D0_N
set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]] ; ## IO_L13P_T2_MRCC_35 U1,D15,IO_L13_35_TX_D0_P
set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]] ; ## IO_L14N_T2_AD4N_SRCC_35 U1,E15,IO_L14_35_TX_D1_N
set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]] ; ## IO_L14P_T2_AD4P_SRCC_35 U1,F15,IO_L14_35_TX_D1_P
set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]] ; ## IO_L15N_T2_DQS_AD12N_35 U1,C16,IO_L15_35_TX_D2_N
set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]] ; ## IO_L15P_T2_DQS_AD12P_35 U1,C17,IO_L15_35_TX_D2_P
set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]] ; ## IO_L16N_T2_35 U1,D16,IO_L16_35_TX_D3_N
set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]] ; ## IO_L16P_T2_35 U1,E16,IO_L16_35_TX_D3_P
set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]] ; ## IO_L17N_T2_AD5N_35 U1,B15,IO_L17_35_TX_D4_N
set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]] ; ## IO_L17P_T2_AD5P_35 U1,B16,IO_L17_35_TX_D4_P
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]] ; ## IO_L18N_T2_AD13N_35 U1,A17,IO_L18_35_TX_D5_N
set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]] ; ## IO_L18P_T2_AD13P_35 U1,B17,IO_L18_35_TX_D5_P
set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18} [get_ports tx_gnd[0]] ; ## IO_L8N_T1_AD10N_35 U1,J13,IO_L08_35_FB_CLK_N
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18} [get_ports tx_gnd[1]] ; ## IO_L9N_T1_DQS_AD3N_35 U1,J15,IO_L09_35_TX_FRAME_N
# clocks
create_clock -name rx_clk -period 8 [get_ports rx_clk_in]
create_clock -name ad9361_clk -period 8 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]

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# constraints (pzsdr2.e)
# ad9361
set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## IO_L12P_T1_MRCC_35 U1,J14,IO_L12_MRCC_35_DATA_CLK_P
set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## IO_L12N_T1_MRCC_35 U1,H14,IO_L12_MRCC_35_DATA_CLK_N
set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## IO_L7P_T1_AD2P_35 U1,H13,IO_L07_35_RX_FRAME_P
set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## IO_L7N_T1_AD2N_35 U1,H12,IO_L07_35_RX_FRAME_N
set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## IO_L1P_T0_AD0P_35 U1,F12,IO_L01_35_RX_D0_P
set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## IO_L1N_T0_AD0N_35 U1,E12,IO_L01_35_RX_D0_N
set_property -dict {PACKAGE_PIN E10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## IO_L2P_T0_AD8P_35 U1,E10,IO_L02_35_RX_D1_P
set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## IO_L2N_T0_AD8N_35 U1,D10,IO_L02_35_RX_D1_N
set_property -dict {PACKAGE_PIN G10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## IO_L3P_T0_DQS_AD1P_35 U1,G10,IO_L03_35_RX_D2_P
set_property -dict {PACKAGE_PIN F10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## IO_L3N_T0_DQS_AD1N_35 U1,F10,IO_L03_35_RX_D2_N
set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## IO_L4P_T0_35 U1,E11,IO_L04_35_RX_D3_P
set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## IO_L4N_T0_35 U1,D11,IO_L04_35_RX_D3_N
set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## IO_L5P_T0_AD9P_35 U1,G12,IO_L05_35_RX_D4_P
set_property -dict {PACKAGE_PIN G11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## IO_L5N_T0_AD9N_35 U1,G11,IO_L05_35_RX_D4_N
set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## IO_L6P_T0_35 U1,F13,IO_L06_35_RX_D5_P
set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## IO_L6N_T0_VREF_35 U1,E13,IO_L06_35_RX_D5_N
set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVDS} [get_ports tx_clk_out_p] ; ## IO_L8P_T1_AD10P_35 U1,K13,IO_L08_35_FB_CLK_P
set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVDS} [get_ports tx_clk_out_n] ; ## IO_L8N_T1_AD10N_35 U1,J13,IO_L08_35_FB_CLK_N
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVDS} [get_ports tx_frame_out_p] ; ## IO_L9P_T1_DQS_AD3P_35 U1,K15,IO_L09_35_TX_FRAME_P
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVDS} [get_ports tx_frame_out_n] ; ## IO_L9N_T1_DQS_AD3N_35 U1,J15,IO_L09_35_TX_FRAME_N
set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVDS} [get_ports tx_data_out_p[0]] ; ## IO_L13P_T2_MRCC_35 U1,D15,IO_L13_35_TX_D0_P
set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVDS} [get_ports tx_data_out_n[0]] ; ## IO_L13N_T2_MRCC_35 U1,D14,IO_L13_35_TX_D0_N
set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVDS} [get_ports tx_data_out_p[1]] ; ## IO_L14P_T2_AD4P_SRCC_35 U1,F15,IO_L14_35_TX_D1_P
set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVDS} [get_ports tx_data_out_n[1]] ; ## IO_L14N_T2_AD4N_SRCC_35 U1,E15,IO_L14_35_TX_D1_N
set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVDS} [get_ports tx_data_out_p[2]] ; ## IO_L15P_T2_DQS_AD12P_35 U1,C17,IO_L15_35_TX_D2_P
set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVDS} [get_ports tx_data_out_n[2]] ; ## IO_L15N_T2_DQS_AD12N_35 U1,C16,IO_L15_35_TX_D2_N
set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVDS} [get_ports tx_data_out_p[3]] ; ## IO_L16P_T2_35 U1,E16,IO_L16_35_TX_D3_P
set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVDS} [get_ports tx_data_out_n[3]] ; ## IO_L16N_T2_35 U1,D16,IO_L16_35_TX_D3_N
set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVDS} [get_ports tx_data_out_p[4]] ; ## IO_L17P_T2_AD5P_35 U1,B16,IO_L17_35_TX_D4_P
set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVDS} [get_ports tx_data_out_n[4]] ; ## IO_L17N_T2_AD5N_35 U1,B15,IO_L17_35_TX_D4_N
set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVDS} [get_ports tx_data_out_p[5]] ; ## IO_L18P_T2_AD13P_35 U1,B17,IO_L18_35_TX_D5_P
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVDS} [get_ports tx_data_out_n[5]] ; ## IO_L18N_T2_AD13N_35 U1,A17,IO_L18_35_TX_D5_N
# clocks
create_clock -name rx_clk -period 4 [get_ports rx_clk_in_p]
create_clock -name ad9361_clk -period 4 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]