daq2/kcu105: latest mig updates
Rejeesh Kutty
parent
db1c931736
commit
db2386a351
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@ -25,13 +25,6 @@ set iic_main [create_bd_intf_port -mode Master -vlnv xilinx.com:interface
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set uart_sin [create_bd_port -dir I uart_sin]
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set uart_sout [create_bd_port -dir O uart_sout]
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set mdm_reset [create_bd_port -dir O mdm_reset]
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set mig_reset [create_bd_port -dir O mig_reset]
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set mig_ready [create_bd_port -dir O mig_ready]
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set sys_cpu_clk [create_bd_port -dir O sys_cpu_clk]
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set sys_cpu_rst [create_bd_port -dir I -type rst sys_cpu_rst]
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set sys_cpu_rstn [create_bd_port -dir I -type rst sys_cpu_rstn]
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set unc_int2 [create_bd_port -dir I unc_int2]
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set unc_int3 [create_bd_port -dir I unc_int3]
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set unc_int4 [create_bd_port -dir I unc_int4]
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@ -47,8 +40,6 @@ set hdmi_data [create_bd_port -dir O -from 15 -to 0 hdmi_data]
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set spdif [create_bd_port -dir O spdif]
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set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] $sys_rst
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set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] $sys_cpu_rst
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set_property -dict [list CONFIG.POLARITY {ACTIVE_LOW}] $sys_cpu_rstn
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# instance: microblaze - processor
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@ -86,6 +77,10 @@ set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram
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set sys_mb_debug [create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.1 sys_mb_debug]
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set_property -dict [list CONFIG.C_USE_UART {1}] $sys_mb_debug
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# instance: system reset/clocks
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set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
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# instance: ddr (mig)
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set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig:5.0 axi_ddr_cntrl]
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@ -175,31 +170,19 @@ set axi_spdif_tx_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 ax
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set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_spdif_tx_dma
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set_property -dict [list CONFIG.c_sg_include_stscntrl_strm {0}] $axi_spdif_tx_dma
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# connections (reset and clocks)
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# connections
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connect_bd_net -net mdm_reset [get_bd_pins sys_mb_debug/Debug_SYS_Rst] [get_bd_ports mdm_reset]
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connect_bd_net -net mig_reset [get_bd_pins axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst] [get_bd_ports mig_reset]
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connect_bd_net -net mig_ready [get_bd_pins axi_ddr_cntrl/c0_init_calib_complete] [get_bd_ports mig_ready]
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connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins sys_mb_debug/Debug_SYS_Rst]
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connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins sys_rstgen/mb_debug_sys_rst]
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set sys_reset_source [get_bd_ports sys_cpu_rst]
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set sys_resetn_source [get_bd_ports sys_cpu_rstn]
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set sys_cpu_clk_source [get_bd_pins axi_ddr_cntrl/addn_ui_clkout1]
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set sys_mem_clk_source [get_bd_pins axi_ddr_cntrl/c0_ddr4_ui_clk]
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set sys_200m_clk_source [get_bd_pins axi_ddr_cntrl/addn_ui_clkout2]
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connect_bd_net -net sys_rstgen_mb_reset [get_bd_pins sys_rstgen/mb_reset]
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connect_bd_net -net sys_rstgen_mb_reset [get_bd_pins sys_mb/Reset]
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connect_bd_net -net sys_cpu_rst $sys_reset_source
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connect_bd_net -net sys_cpu_rstn $sys_resetn_source
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connect_bd_net -net sys_cpu_clk $sys_cpu_clk_source
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connect_bd_net -net sys_mem_clk $sys_mem_clk_source
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connect_bd_net -net sys_200m_clk $sys_200m_clk_source
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connect_bd_net -net sys_cpu_rst [get_bd_pins sys_mb/Reset]
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connect_bd_net -net sys_cpu_rst [get_bd_pins sys_dlmb/SYS_Rst]
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connect_bd_net -net sys_cpu_rst [get_bd_pins sys_ilmb/SYS_Rst]
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connect_bd_net -net sys_cpu_rst [get_bd_pins sys_dlmb_cntlr/LMB_Rst]
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connect_bd_net -net sys_cpu_rst [get_bd_pins sys_ilmb_cntlr/LMB_Rst]
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connect_bd_net -net sys_cpu_clk [get_bd_ports sys_cpu_clk]
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connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_rstgen/bus_struct_reset]
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connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_dlmb/SYS_Rst]
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connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_ilmb/SYS_Rst]
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connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_dlmb_cntlr/LMB_Rst]
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connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_ilmb_cntlr/LMB_Rst]
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# microblaze local memory
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@ -219,6 +202,18 @@ connect_bd_net -net sys_concat_intc_intr [get_bd_pins sys_concat_intc/dout] [get
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# defaults (peripherals)
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set sys_reset_source [get_bd_pins sys_rstgen/peripheral_reset]
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set sys_resetn_source [get_bd_pins sys_rstgen/peripheral_aresetn]
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set sys_mem_clk_source [get_bd_pins axi_ddr_cntrl/c0_ddr4_ui_clk]
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set sys_cpu_clk_source [get_bd_pins axi_ddr_cntrl/addn_ui_clkout1]
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set sys_200m_clk_source [get_bd_pins axi_ddr_cntrl/addn_ui_clkout2]
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connect_bd_net -net sys_cpu_rst $sys_reset_source
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connect_bd_net -net sys_cpu_rstn $sys_resetn_source
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connect_bd_net -net sys_cpu_clk $sys_cpu_clk_source
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connect_bd_net -net sys_mem_clk $sys_mem_clk_source
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connect_bd_net -net sys_200m_clk $sys_200m_clk_source
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connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M06_ARESETN] $sys_resetn_source
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connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/ARESETN] $sys_resetn_source
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connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/ARESETN] $sys_resetn_source
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@ -239,6 +234,7 @@ connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_gpio_sw_led/s_axi_aresetn]
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connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_iic_main/s_axi_aresetn]
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connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ethernet_dma/axi_resetn]
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connect_bd_net -net sys_cpu_clk [get_bd_pins sys_rstgen/slowest_sync_clk]
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connect_bd_net -net sys_cpu_clk [get_bd_pins sys_mb/Clk]
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connect_bd_net -net sys_cpu_clk [get_bd_pins sys_mb_debug/S_AXI_ACLK]
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connect_bd_net -net sys_cpu_clk [get_bd_pins sys_dlmb/LMB_Clk]
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@ -258,7 +254,6 @@ connect_bd_net -net sys_cpu_clk [get_bd_pins axi_gpio_lcd/s_axi_aclk]
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connect_bd_net -net sys_cpu_clk [get_bd_pins axi_gpio_sw_led/s_axi_aclk]
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connect_bd_net -net sys_cpu_clk [get_bd_pins axi_iic_main/s_axi_aclk]
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# defaults (interconnect - processor)
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connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_s00 [get_bd_intf_pins axi_cpu_aux_interconnect/S00_AXI] [get_bd_intf_pins axi_cpu_interconnect/M06_AXI]
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@ -347,11 +342,12 @@ connect_bd_net -net sys_concat_intc_din_4 [get_bd_pins sys_concat_intc/In4] [get
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# defaults (external interface)
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connect_bd_net -net phy_sd [get_bd_ports phy_sd] [get_bd_pins axi_ethernet/signal_detect]
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connect_bd_net -net sys_rst [get_bd_ports sys_rst] [get_bd_pins axi_ddr_cntrl/sys_rst]
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connect_bd_net [get_bd_ports phy_sd] [get_bd_pins axi_ethernet/signal_detect]
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connect_bd_net [get_bd_ports sys_rst] [get_bd_pins axi_ddr_cntrl/sys_rst]
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connect_bd_net [get_bd_pins axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst] [get_bd_pins sys_rstgen/ext_reset_in]
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connect_bd_net -net sys_clk_p [get_bd_ports sys_clk_p] [get_bd_pins axi_ddr_cntrl/c0_sys_clk_p]
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connect_bd_net -net sys_clk_n [get_bd_ports sys_clk_n] [get_bd_pins axi_ddr_cntrl/c0_sys_clk_n]
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connect_bd_net -net sys_clk_p_s [get_bd_ports sys_clk_p] [get_bd_pins axi_ddr_cntrl/c0_sys_clk_p]
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connect_bd_net -net sys_clk_n_s [get_bd_ports sys_clk_n] [get_bd_pins axi_ddr_cntrl/c0_sys_clk_n]
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connect_bd_intf_net -intf_net axi_ddr_cntrl_c0_ddr4 [get_bd_intf_ports c0_ddr4] [get_bd_intf_pins axi_ddr_cntrl/C0_DDR4]
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@ -474,13 +470,13 @@ create_bd_addr_seg -range 0x00010000 -offset 0x41E00000 $sys_addr_cntrl_space [g
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create_bd_addr_seg -range 0x00020000 -offset 0x00000000 [get_bd_addr_spaces sys_mb/Instruction] [get_bd_addr_segs sys_ilmb_cntlr/SLMB/Mem] SEG_instr_ilmb_cntlr
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create_bd_addr_seg -range 0x00010000 -offset 0x00000000 [get_bd_addr_spaces axi_ethernet/eth_buf/S_AXI_2TEMAC] [get_bd_addr_segs axi_ethernet/eth_mac/s_axi/Reg] SEG_ethernet_mac
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create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
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create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces sys_mb/Instruction] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
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create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces axi_ethernet_dma/Data_SG] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
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create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces axi_ethernet_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
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create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces axi_ethernet_dma/Data_S2MM] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
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create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
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create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_SG] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
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create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
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create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
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create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces sys_mb/Instruction] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
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create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_dma/Data_SG] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
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create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
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create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_dma/Data_S2MM] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
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create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
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create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_SG] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
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create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
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@ -5,9 +5,12 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM}] [get_bd_cells ax
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set_property -dict [list CONFIG.C0.DDR4_TimePeriod {833}] [get_bd_cells axi_ddr_cntrl]
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set_property -dict [list CONFIG.C0.DDR4_InputClockPeriod {3333}] [get_bd_cells axi_ddr_cntrl]
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set_property -dict [list CONFIG.C0.DDR4_MemoryPart {MT40A256M16HA-083}] [get_bd_cells axi_ddr_cntrl]
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set_property -dict [list CONFIG.C0.DDR4_MemoryVoltage {1.2V}] [get_bd_cells axi_ddr_cntrl]
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set_property -dict [list CONFIG.C0.Internal_Vref {true}] [get_bd_cells axi_ddr_cntrl]
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set_property -dict [list CONFIG.C0.DDR4_DataWidth {64}] [get_bd_cells axi_ddr_cntrl]
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set_property -dict [list CONFIG.C0.DDR4_Mem_Add_Map {ROW_BANK_COLUMN}] [get_bd_cells axi_ddr_cntrl]
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set_property -dict [list CONFIG.C0.DDR4_CasWriteLatency {12}] [get_bd_cells axi_ddr_cntrl]
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set_property -dict [list CONFIG.C0.Debug_Signal {Enable}] [get_bd_cells axi_ddr_cntrl]
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set_property -dict [list CONFIG.C0.DDR4_AxiDataWidth {512}] [get_bd_cells axi_ddr_cntrl]
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set_property -dict [list CONFIG.C0.DDR4_AxiNarrowBurst {true}] [get_bd_cells axi_ddr_cntrl]
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@ -141,18 +144,9 @@ set_property -dict [list CONFIG.c0_act_n {bank45.byte2.pin12}] [ge
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set_property -dict [list CONFIG.c0_ck_t {bank45.byte3.pin6}] [get_bd_cells axi_ddr_cntrl]
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set_property -dict [list CONFIG.c0_ck_c {bank45.byte3.pin7}] [get_bd_cells axi_ddr_cntrl]
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# This loc of sys_clk should be removed from MIG once DRC is fixed - CR782609
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set_property -dict [list CONFIG.c0_sys_clk_p {bank45.byte1.pin10}] [get_bd_cells axi_ddr_cntrl]
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set_property -dict [list CONFIG.c0_sys_clk_n {bank45.byte1.pin11}] [get_bd_cells axi_ddr_cntrl]
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# Currently, it is required to manually unassign the pins in MIG IO Placer
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#set_property -dict [list CONFIG.sys_rst {bank45.byte0.pin5}] [get_bd_cells axi_ddr_cntrl]
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#set_property -dict [list CONFIG.c0_data_compare_error {bank65.byte3.pin2}] [get_bd_cells axi_ddr_cntrl]
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#set_property -dict [list CONFIG.c0_init_calib_complete {bank65.byte3.pin3}] [get_bd_cells axi_ddr_cntrl]
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set_property -dict [list CONFIG.sys_rst {Unassigned}] [get_bd_cells axi_ddr_cntrl]
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set_property -dict [list CONFIG.c0_data_compare_error {Unassigned}] [get_bd_cells axi_ddr_cntrl]
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set_property -dict [list CONFIG.c0_init_calib_complete {Unassigned}] [get_bd_cells axi_ddr_cntrl]
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set_property -dict [list CONFIG.sys_rst {bank64.byte2.pin2}] [get_bd_cells axi_ddr_cntrl]
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set_property -dict [list CONFIG.c0_data_compare_error {bank65.byte3.pin2}] [get_bd_cells axi_ddr_cntrl]
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set_property -dict [list CONFIG.c0_init_calib_complete {bank65.byte3.pin3}] [get_bd_cells axi_ddr_cntrl]
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@ -490,8 +490,8 @@ if {$sys_zynq == 0} {
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create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_core/s_axi/axi_lite] SEG_data_ad9144_core
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create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_core/s_axi/axi_lite] SEG_data_ad9680_core
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create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_gt/s_axi/axi_lite] SEG_data_daq2_gt
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create_bd_addr_seg -range 0x00001000 -offset 0x44A90000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_jesd/s_axi/Reg] SEG_data_ad9144_jesd
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create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_jesd/s_axi/Reg] SEG_data_ad9680_jesd
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create_bd_addr_seg -range 0x00010000 -offset 0x44A90000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_jesd/s_axi/Reg] SEG_data_ad9144_jesd
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create_bd_addr_seg -range 0x00010000 -offset 0x44A80000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_jesd/s_axi/Reg] SEG_data_ad9680_jesd
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create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_dma/s_axi/axi_lite] SEG_data_ad9680_dma
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create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_dma/s_axi/axi_lite] SEG_data_ad9144_dma
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@ -503,9 +503,9 @@ if {$sys_zynq == 0} {
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if {$sys_zynq == 0} {
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create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9144_dma/m_src_axi] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_axi_ddr_cntrl
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create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_axi_ddr_cntrl
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_daq2_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_axi_ddr_cntrl
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9144_dma/m_src_axi] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_daq2_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
|
||||
|
||||
} else {
|
||||
|
||||
|
|
@ -514,3 +514,6 @@ if {$sys_zynq == 0} {
|
|||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_daq2_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -223,16 +223,9 @@ module system_top (
|
|||
reg adc_dsync = 'd0;
|
||||
reg adc_dwr = 'd0;
|
||||
reg [127:0] adc_ddata = 'd0;
|
||||
reg [31:0] sys_reset_m = 'd0;
|
||||
reg sys_cpu_rst = 'd0;
|
||||
reg sys_cpu_rstn = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire mdm_reset;
|
||||
wire mig_reset;
|
||||
wire mig_ready;
|
||||
wire sys_cpu_clk;
|
||||
wire rx_ref_clk;
|
||||
wire rx_sysref;
|
||||
wire rx_sync;
|
||||
|
|
@ -383,20 +376,6 @@ module system_top (
|
|||
|
||||
assign fan_pwm = 1'b1;
|
||||
|
||||
// assign sys_reset_req = mdm_reset | mig_reset | ~mig_ready;
|
||||
// assign sys_reset_req = mdm_reset;
|
||||
assign sys_reset_req = 1'b0;
|
||||
|
||||
always @(posedge sys_cpu_clk) begin
|
||||
if (sys_reset_req == 1'b1) begin
|
||||
sys_reset_m <= {32{1'b1}};
|
||||
end else begin
|
||||
sys_reset_m <= {sys_reset_m[30:0], 1'b0};
|
||||
end
|
||||
sys_cpu_rst <= sys_reset_m[31];
|
||||
sys_cpu_rstn <= ~sys_reset_m[31];
|
||||
end
|
||||
|
||||
// instantiations
|
||||
|
||||
IBUFDS_GTE3 i_ibufds_rx_ref_clk (
|
||||
|
|
@ -566,9 +545,6 @@ module system_top (
|
|||
.iic_rstn (iic_rstn),
|
||||
.mdio_mdc (mdio_mdc),
|
||||
.mdio_mdio_io (mdio_mdio),
|
||||
.mdm_reset (mdm_reset),
|
||||
.mig_ready (mig_ready),
|
||||
.mig_reset (mig_reset),
|
||||
.phy_rst_n (phy_rst_n),
|
||||
.phy_sd (1'b1),
|
||||
.sgmii_rxn (phy_rx_n),
|
||||
|
|
@ -592,9 +568,6 @@ module system_top (
|
|||
.spi_sdo_o (spi_mosi),
|
||||
.sys_clk_n (sys_clk_n),
|
||||
.sys_clk_p (sys_clk_p),
|
||||
.sys_cpu_clk (sys_cpu_clk),
|
||||
.sys_cpu_rst (sys_cpu_rst),
|
||||
.sys_cpu_rstn (sys_cpu_rstn),
|
||||
.sys_rst (sys_rst),
|
||||
.tx_data_n (tx_data_n),
|
||||
.tx_data_p (tx_data_p),
|
||||
|
|
|
|||
Loading…
Reference in New Issue