diff --git a/projects/daq2/common/daq2_bd.tcl b/projects/daq2/common/daq2_bd.tcl index af1ecddcd..0d6e6627d 100644 --- a/projects/daq2/common/daq2_bd.tcl +++ b/projects/daq2/common/daq2_bd.tcl @@ -73,17 +73,10 @@ ad_connect sys_cpu_clk util_daq2_xcvr/up_clk create_bd_port -dir I tx_ref_clk_0 create_bd_port -dir I rx_ref_clk_0 -ad_connect tx_ref_clk_0 util_daq2_xcvr/qpll_ref_clk_0 -ad_connect axi_ad9144_xcvr/up_pll_rst util_daq2_xcvr/up_qpll_rst_0 - -ad_connect rx_ref_clk_0 util_daq2_xcvr/cpll_ref_clk_0 -ad_connect rx_ref_clk_0 util_daq2_xcvr/cpll_ref_clk_1 -ad_connect rx_ref_clk_0 util_daq2_xcvr/cpll_ref_clk_2 -ad_connect rx_ref_clk_0 util_daq2_xcvr/cpll_ref_clk_3 -ad_connect axi_ad9680_xcvr/up_pll_rst util_daq2_xcvr/up_cpll_rst_0 -ad_connect axi_ad9680_xcvr/up_pll_rst util_daq2_xcvr/up_cpll_rst_1 -ad_connect axi_ad9680_xcvr/up_pll_rst util_daq2_xcvr/up_cpll_rst_2 -ad_connect axi_ad9680_xcvr/up_pll_rst util_daq2_xcvr/up_cpll_rst_3 +ad_xcvrpll tx_ref_clk_0 util_daq2_xcvr/qpll_ref_clk_* +ad_xcvrpll rx_ref_clk_0 util_daq2_xcvr/cpll_ref_clk_* +ad_xcvrpll axi_ad9144_xcvr/up_pll_rst util_daq2_xcvr/up_qpll_rst_* +ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_daq2_xcvr/up_cpll_rst_* # connections (dac) diff --git a/projects/fmcadc2/common/fmcadc2_bd.tcl b/projects/fmcadc2/common/fmcadc2_bd.tcl index aa41370e8..fa6a7b7b1 100644 --- a/projects/fmcadc2/common/fmcadc2_bd.tcl +++ b/projects/fmcadc2/common/fmcadc2_bd.tcl @@ -25,33 +25,46 @@ set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma set util_fmcadc2_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcadc2_xcvr] -set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc2_xcvr +set_property -dict [list CONFIG.QPLL_FBDIV {"0010000000"}] $util_fmcadc2_xcvr +set_property -dict [list CONFIG.CPLL_FBDIV {2}] $util_fmcadc2_xcvr set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_fmcadc2_xcvr -set_property -dict [list CONFIG.CPLL_TX_OR_RX_N {0}] $util_fmcadc2_xcvr +set_property -dict [list CONFIG.TX_OUT_DIV {2}] $util_fmcadc2_xcvr +set_property -dict [list CONFIG.TX_CLK25_DIV {10}] $util_fmcadc2_xcvr +set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc2_xcvr +set_property -dict [list CONFIG.RX_OUT_DIV {1}] $util_fmcadc2_xcvr +set_property -dict [list CONFIG.RX_CLK25_DIV {10}] $util_fmcadc2_xcvr +set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0904}] $util_fmcadc2_xcvr +set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff10200020}] $util_fmcadc2_xcvr -# connections (gt) +# reference clocks & resets -ad_xcvrcon util_fmcadc2_xcvr axi_ad9625_xcvr axi_ad9625_jesd -ad_connect sys_cpu_resetn util_fmcadc2_xcvr/up_rstn -ad_connect sys_cpu_clk util_fmcadc2_xcvr/up_clk -ad_connect util_fmcadc2_xcvr/rx_out_clk_0 axi_ad9625_core/rx_clk -ad_connect axi_ad9625_jesd/rx_tdata axi_ad9625_core/rx_data -ad_connect axi_ad9625_jesd/rx_start_of_frame axi_ad9625_core/rx_sof +create_bd_port -dir I rx_ref_clk_0 + +ad_xcvrpll rx_ref_clk_0 util_fmcadc2_xcvr/qpll_ref_clk_* +ad_xcvrpll rx_ref_clk_0 util_fmcadc2_xcvr/cpll_ref_clk_* +ad_xcvrpll axi_ad9625_xcvr/up_pll_rst util_fmcadc2_xcvr/up_qpll_rst_* +ad_xcvrpll axi_ad9625_xcvr/up_pll_rst util_fmcadc2_xcvr/up_cpll_rst_* +ad_connect sys_cpu_resetn util_fmcadc2_xcvr/up_rstn +ad_connect sys_cpu_clk util_fmcadc2_xcvr/up_clk # connections (adc) -ad_connect sys_cpu_clk axi_ad9625_fifo/dma_clk -ad_connect sys_cpu_clk axi_ad9625_dma/s_axis_aclk -ad_connect sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn -ad_connect axi_ad9625_core/adc_clk axi_ad9625_fifo/adc_clk -ad_connect axi_ad9625_fifo/adc_rst axi_ad9625_core/adc_rst -ad_connect axi_ad9625_core/adc_enable axi_ad9625_fifo/adc_wr -ad_connect axi_ad9625_core/adc_data axi_ad9625_fifo/adc_wdata -ad_connect axi_ad9625_core/adc_dovf axi_ad9625_fifo/adc_wovf -ad_connect axi_ad9625_fifo/dma_wr axi_ad9625_dma/s_axis_valid -ad_connect axi_ad9625_fifo/dma_wdata axi_ad9625_dma/s_axis_data -ad_connect axi_ad9625_fifo/dma_wready axi_ad9625_dma/s_axis_ready -ad_connect axi_ad9625_fifo/dma_xfer_req axi_ad9625_dma/s_axis_xfer_req +ad_xcvrcon util_fmcadc2_xcvr axi_ad9625_xcvr axi_ad9625_jesd +ad_connect util_fmcadc2_xcvr/rx_out_clk_0 axi_ad9625_core/rx_clk +ad_connect axi_ad9625_jesd/rx_tdata axi_ad9625_core/rx_data +ad_connect axi_ad9625_jesd/rx_start_of_frame axi_ad9625_core/rx_sof +ad_connect sys_cpu_clk axi_ad9625_fifo/dma_clk +ad_connect sys_cpu_clk axi_ad9625_dma/s_axis_aclk +ad_connect sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn +ad_connect axi_ad9625_core/adc_clk axi_ad9625_fifo/adc_clk +ad_connect axi_ad9625_fifo/adc_rst axi_ad9625_core/adc_rst +ad_connect axi_ad9625_core/adc_enable axi_ad9625_fifo/adc_wr +ad_connect axi_ad9625_core/adc_data axi_ad9625_fifo/adc_wdata +ad_connect axi_ad9625_core/adc_dovf axi_ad9625_fifo/adc_wovf +ad_connect axi_ad9625_fifo/dma_wr axi_ad9625_dma/s_axis_valid +ad_connect axi_ad9625_fifo/dma_wdata axi_ad9625_dma/s_axis_data +ad_connect axi_ad9625_fifo/dma_wready axi_ad9625_dma/s_axis_ready +ad_connect axi_ad9625_fifo/dma_xfer_req axi_ad9625_dma/s_axis_xfer_req # interconnect (cpu) diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl index fd10f8ec0..8b94fbace 100644 --- a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl +++ b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl @@ -51,52 +51,68 @@ set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9250_1_dma # transceiver core set util_fmcjesdadc1_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcjesdadc1_xcvr] -set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_fmcjesdadc1_xcvr +set_property -dict [list CONFIG.QPLL_FBDIV {"0010000000"}] $util_fmcjesdadc1_xcvr +set_property -dict [list CONFIG.CPLL_FBDIV {2}] $util_fmcjesdadc1_xcvr set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_fmcjesdadc1_xcvr +set_property -dict [list CONFIG.TX_OUT_DIV {1}] $util_fmcjesdadc1_xcvr +set_property -dict [list CONFIG.TX_CLK25_DIV {10}] $util_fmcjesdadc1_xcvr +set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_fmcjesdadc1_xcvr +set_property -dict [list CONFIG.RX_OUT_DIV {1}] $util_fmcjesdadc1_xcvr +set_property -dict [list CONFIG.RX_CLK25_DIV {10}] $util_fmcjesdadc1_xcvr +set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0904}] $util_fmcjesdadc1_xcvr +set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff10200020}] $util_fmcjesdadc1_xcvr +# reference clocks & resets + +create_bd_port -dir I rx_ref_clk_0 + +ad_xcvrpll rx_ref_clk_0 util_fmcjesdadc1_xcvr/qpll_ref_clk_* +ad_xcvrpll rx_ref_clk_0 util_fmcjesdadc1_xcvr/cpll_ref_clk_* +ad_xcvrpll axi_ad9250_xcvr/up_pll_rst util_fmcjesdadc1_xcvr/up_qpll_rst_* +ad_xcvrpll axi_ad9250_xcvr/up_pll_rst util_fmcjesdadc1_xcvr/up_cpll_rst_* ad_connect sys_cpu_resetn util_fmcjesdadc1_xcvr/up_rstn ad_connect sys_cpu_clk util_fmcjesdadc1_xcvr/up_clk # connections (adc) -ad_xcvrcon util_fmcjesdadc1_xcvr axi_ad9250_xcvr axi_ad9250_jesd -ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_0_core/rx_clk -ad_connect axi_ad9250_jesd/rx_start_of_frame axi_ad9250_0_core/rx_sof -ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_1_core/rx_clk -ad_connect axi_ad9250_jesd/rx_start_of_frame axi_ad9250_1_core/rx_sof +ad_xcvrcon util_fmcjesdadc1_xcvr axi_ad9250_xcvr axi_ad9250_jesd +ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_0_core/rx_clk +ad_connect axi_ad9250_jesd/rx_start_of_frame axi_ad9250_0_core/rx_sof +ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_1_core/rx_clk +ad_connect axi_ad9250_jesd/rx_start_of_frame axi_ad9250_1_core/rx_sof -ad_connect axi_ad9250_jesd/rx_tdata data_bsplit/data -ad_connect axi_ad9250_0_core/rx_data data_bsplit/split_data_0 -ad_connect axi_ad9250_1_core/rx_data data_bsplit/split_data_1 +ad_connect axi_ad9250_jesd/rx_tdata data_bsplit/data +ad_connect axi_ad9250_0_core/rx_data data_bsplit/split_data_0 +ad_connect axi_ad9250_1_core/rx_data data_bsplit/split_data_1 -ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_0_cpack/adc_clk -ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_1_cpack/adc_clk -ad_connect axi_ad9250_jesd_rstgen/peripheral_reset axi_ad9250_0_cpack/adc_rst -ad_connect axi_ad9250_jesd_rstgen/peripheral_reset axi_ad9250_1_cpack/adc_rst +ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_0_cpack/adc_clk +ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_1_cpack/adc_clk +ad_connect axi_ad9250_jesd_rstgen/peripheral_reset axi_ad9250_0_cpack/adc_rst +ad_connect axi_ad9250_jesd_rstgen/peripheral_reset axi_ad9250_1_cpack/adc_rst -ad_connect axi_ad9250_0_core/adc_enable_a axi_ad9250_0_cpack/adc_enable_0 -ad_connect axi_ad9250_0_core/adc_valid_a axi_ad9250_0_cpack/adc_valid_0 -ad_connect axi_ad9250_0_core/adc_data_a axi_ad9250_0_cpack/adc_data_0 -ad_connect axi_ad9250_0_core/adc_enable_b axi_ad9250_0_cpack/adc_enable_1 -ad_connect axi_ad9250_0_core/adc_valid_b axi_ad9250_0_cpack/adc_valid_1 -ad_connect axi_ad9250_0_core/adc_data_b axi_ad9250_0_cpack/adc_data_1 -ad_connect axi_ad9250_1_core/adc_enable_a axi_ad9250_1_cpack/adc_enable_0 -ad_connect axi_ad9250_1_core/adc_valid_a axi_ad9250_1_cpack/adc_valid_0 -ad_connect axi_ad9250_1_core/adc_data_a axi_ad9250_1_cpack/adc_data_0 -ad_connect axi_ad9250_1_core/adc_enable_b axi_ad9250_1_cpack/adc_enable_1 -ad_connect axi_ad9250_1_core/adc_valid_b axi_ad9250_1_cpack/adc_valid_1 -ad_connect axi_ad9250_1_core/adc_data_b axi_ad9250_1_cpack/adc_data_1 +ad_connect axi_ad9250_0_core/adc_enable_a axi_ad9250_0_cpack/adc_enable_0 +ad_connect axi_ad9250_0_core/adc_valid_a axi_ad9250_0_cpack/adc_valid_0 +ad_connect axi_ad9250_0_core/adc_data_a axi_ad9250_0_cpack/adc_data_0 +ad_connect axi_ad9250_0_core/adc_enable_b axi_ad9250_0_cpack/adc_enable_1 +ad_connect axi_ad9250_0_core/adc_valid_b axi_ad9250_0_cpack/adc_valid_1 +ad_connect axi_ad9250_0_core/adc_data_b axi_ad9250_0_cpack/adc_data_1 +ad_connect axi_ad9250_1_core/adc_enable_a axi_ad9250_1_cpack/adc_enable_0 +ad_connect axi_ad9250_1_core/adc_valid_a axi_ad9250_1_cpack/adc_valid_0 +ad_connect axi_ad9250_1_core/adc_data_a axi_ad9250_1_cpack/adc_data_0 +ad_connect axi_ad9250_1_core/adc_enable_b axi_ad9250_1_cpack/adc_enable_1 +ad_connect axi_ad9250_1_core/adc_valid_b axi_ad9250_1_cpack/adc_valid_1 +ad_connect axi_ad9250_1_core/adc_data_b axi_ad9250_1_cpack/adc_data_1 -ad_connect axi_ad9250_0_core/adc_clk axi_ad9250_0_dma/fifo_wr_clk -ad_connect axi_ad9250_0_dma/fifo_wr_en axi_ad9250_0_cpack/adc_valid -ad_connect axi_ad9250_0_dma/fifo_wr_sync axi_ad9250_0_cpack/adc_sync -ad_connect axi_ad9250_0_dma/fifo_wr_din axi_ad9250_0_cpack/adc_data -ad_connect axi_ad9250_0_core/adc_dovf axi_ad9250_0_dma/fifo_wr_overflow -ad_connect axi_ad9250_1_core/adc_clk axi_ad9250_1_dma/fifo_wr_clk -ad_connect axi_ad9250_1_dma/fifo_wr_en axi_ad9250_1_cpack/adc_valid -ad_connect axi_ad9250_1_dma/fifo_wr_sync axi_ad9250_1_cpack/adc_sync -ad_connect axi_ad9250_1_dma/fifo_wr_din axi_ad9250_1_cpack/adc_data -ad_connect axi_ad9250_1_core/adc_dovf axi_ad9250_1_dma/fifo_wr_overflow +ad_connect axi_ad9250_0_core/adc_clk axi_ad9250_0_dma/fifo_wr_clk +ad_connect axi_ad9250_0_dma/fifo_wr_en axi_ad9250_0_cpack/adc_valid +ad_connect axi_ad9250_0_dma/fifo_wr_sync axi_ad9250_0_cpack/adc_sync +ad_connect axi_ad9250_0_dma/fifo_wr_din axi_ad9250_0_cpack/adc_data +ad_connect axi_ad9250_0_core/adc_dovf axi_ad9250_0_dma/fifo_wr_overflow +ad_connect axi_ad9250_1_core/adc_clk axi_ad9250_1_dma/fifo_wr_clk +ad_connect axi_ad9250_1_dma/fifo_wr_en axi_ad9250_1_cpack/adc_valid +ad_connect axi_ad9250_1_dma/fifo_wr_sync axi_ad9250_1_cpack/adc_sync +ad_connect axi_ad9250_1_dma/fifo_wr_din axi_ad9250_1_cpack/adc_data +ad_connect axi_ad9250_1_core/adc_dovf axi_ad9250_1_dma/fifo_wr_overflow # interconnect (cpu) diff --git a/projects/fmcomms11/common/fmcomms11_bd.tcl b/projects/fmcomms11/common/fmcomms11_bd.tcl index 09f47d2a1..11c1ee9ea 100644 --- a/projects/fmcomms11/common/fmcomms11_bd.tcl +++ b/projects/fmcomms11/common/fmcomms11_bd.tcl @@ -53,15 +53,24 @@ set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma # shared transceiver core set util_fmcomms11_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcomms11_xcvr] -set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcomms11_xcvr -set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $util_fmcomms11_xcvr +set_property -dict [list CONFIG.QPLL_FBDIV {"0100100000"}] $util_fmcomms11_xcvr set_property -dict [list CONFIG.CPLL_FBDIV {4}] $util_fmcomms11_xcvr -set_property -dict [list CONFIG.RX_CLK25_DIV {7}] $util_fmcomms11_xcvr +set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $util_fmcomms11_xcvr set_property -dict [list CONFIG.TX_CLK25_DIV {7}] $util_fmcomms11_xcvr +set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcomms11_xcvr +set_property -dict [list CONFIG.RX_CLK25_DIV {7}] $util_fmcomms11_xcvr set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0904}] $util_fmcomms11_xcvr set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff10400020}] $util_fmcomms11_xcvr -set_property -dict [list CONFIG.QPLL_FBDIV {"0100100000"}] $util_fmcomms11_xcvr +# reference clocks & resets + +create_bd_port -dir I tx_ref_clk_0 +create_bd_port -dir I rx_ref_clk_0 + +ad_xcvrpll tx_ref_clk_0 util_fmcomms11_xcvr/qpll_ref_clk_* +ad_xcvrpll rx_ref_clk_0 util_fmcomms11_xcvr/cpll_ref_clk_* +ad_xcvrpll axi_ad9162_xcvr/up_pll_rst util_fmcomms11_xcvr/up_qpll_rst_* +ad_xcvrpll axi_ad9625_xcvr/up_pll_rst util_fmcomms11_xcvr/up_cpll_rst_* ad_connect sys_cpu_resetn util_fmcomms11_xcvr/up_rstn ad_connect sys_cpu_clk util_fmcomms11_xcvr/up_clk diff --git a/projects/fmcomms7/common/fmcomms7_bd.tcl b/projects/fmcomms7/common/fmcomms7_bd.tcl index 7db4d8c02..9f82d1522 100644 --- a/projects/fmcomms7/common/fmcomms7_bd.tcl +++ b/projects/fmcomms7/common/fmcomms7_bd.tcl @@ -1,4 +1,13 @@ +# spi2 + +set axi_fmcomms7_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_fmcomms7_spi] +set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_fmcomms7_spi +set_property -dict [list CONFIG.C_NUM_SS_BITS {12}] $axi_fmcomms7_spi +set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_fmcomms7_spi + +# connections (spi2) + create_bd_port -dir O -from 11 -to 0 spi2_csn_o create_bd_port -dir I -from 11 -to 0 spi2_csn_i create_bd_port -dir I spi2_clk_i @@ -7,6 +16,15 @@ create_bd_port -dir I spi2_sdo_i create_bd_port -dir O spi2_sdo_o create_bd_port -dir I spi2_sdi_i +ad_connect spi2_csn_i axi_fmcomms7_spi/ss_i +ad_connect spi2_csn_o axi_fmcomms7_spi/ss_o +ad_connect spi2_clk_i axi_fmcomms7_spi/sck_i +ad_connect spi2_clk_o axi_fmcomms7_spi/sck_o +ad_connect spi2_sdo_i axi_fmcomms7_spi/io0_i +ad_connect spi2_sdo_o axi_fmcomms7_spi/io0_o +ad_connect spi2_sdi_i axi_fmcomms7_spi/io1_i +ad_connect sys_cpu_clk axi_fmcomms7_spi/ext_spi_clk + # dac peripherals set axi_ad9144_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9144_xcvr] @@ -73,21 +91,17 @@ set util_fmcomms7_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcv set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_fmcomms7_xcvr set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $util_fmcomms7_xcvr -set axi_fmcomms7_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_fmcomms7_spi] -set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_fmcomms7_spi -set_property -dict [list CONFIG.C_NUM_SS_BITS {12}] $axi_fmcomms7_spi -set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_fmcomms7_spi +# reference clocks & resets -# connections (spi2) +create_bd_port -dir I tx_ref_clk_0 +create_bd_port -dir I rx_ref_clk_0 -ad_connect spi2_csn_i axi_fmcomms7_spi/ss_i -ad_connect spi2_csn_o axi_fmcomms7_spi/ss_o -ad_connect spi2_clk_i axi_fmcomms7_spi/sck_i -ad_connect spi2_clk_o axi_fmcomms7_spi/sck_o -ad_connect spi2_sdo_i axi_fmcomms7_spi/io0_i -ad_connect spi2_sdo_o axi_fmcomms7_spi/io0_o -ad_connect spi2_sdi_i axi_fmcomms7_spi/io1_i -ad_connect sys_cpu_clk axi_fmcomms7_spi/ext_spi_clk +ad_xcvrpll tx_ref_clk_0 util_fmcomms7_xcvr/qpll_ref_clk_* +ad_xcvrpll rx_ref_clk_0 util_fmcomms7_xcvr/cpll_ref_clk_* +ad_xcvrpll axi_ad9144_xcvr/up_pll_rst util_fmcomms7_xcvr/up_qpll_rst_* +ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_fmcomms7_xcvr/up_cpll_rst_* +ad_connect sys_cpu_resetn util_fmcomms7_xcvr/up_rstn +ad_connect sys_cpu_clk util_fmcomms7_xcvr/up_clk # connections (dac)