diff --git a/library/axi_ad7175/ad7175_if.v b/library/axi_ad7175/ad7175_if.v new file mode 100644 index 000000000..4587bfd36 --- /dev/null +++ b/library/axi_ad7175/ad7175_if.v @@ -0,0 +1,404 @@ +// ----------------------------------------------------------------------------- +// +// Copyright 2012(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED +// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY +// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ----------------------------------------------------------------------------- +// ----------------------------------------------------------------------------- +`timescale 1ns / 1ps +//------------------------------------------------------------------------------ +//----------- Module Declaration ----------------------------------------------- +//------------------------------------------------------------------------------ +module ad7175_if + ( + // Clock and Reset signals + input fpga_clk_i, + input adc_clk_i, + input reset_n_i, + + // Conversion control signals + input start_conversion_i, + output [31:0] dma_data_o, + output dma_data_rdy_o, + + // Transmit data on request signals + input start_transmission_i, + input [31:0] tx_data_i, + output tx_data_rdy_o, + + // Read data on request signals + input start_read_i, + output [31:0] rx_data_o, + output rx_data_rdy_o, + + // AD7175 IC control signals + input adc_sdo_i, + output adc_sdi_o, + output adc_cs_o, + output adc_sclk_o, + + // ADC status + output reg adc_status_o + ); + +//------------------------------------------------------------------------------ +//----------- Registers Declarations ------------------------------------------- +//------------------------------------------------------------------------------ +// State Machine Registers +reg [10:0] present_state; // Present FSM State +reg [10:0] next_state; // Next FSM State +reg [10:0] present_state_m1; // Used to synchronise FSM States between different clock domains + +// SCLK Registers +reg [7:0] sclk_cnt; // Used to count SCLK Ticks +reg [7:0] sclk_demand; // Used to set number of SCLK Ticks + +// Transmit Data Registers +reg [47:0] tx_data_reg; // Used to shift data out +reg [47:0] tx_data_reg_switch; // Used to select data that is being sent +reg tx_data_rdy_int; // Used to signal the end of a transmit cycle + +// Receive Data Registers +reg [47:0] rx_data_reg; // Used to shift data in +reg [31:0] rx_read_data_reg; // Used to store read data +reg rx_data_rdy_int; // Used to signal the end of a read cycle + +// Conversion Data Registers +reg [31:0] dma_rx_data_reg; // Used to store conversion result (STATUS_REG[31:24] + DATA_REG[23:0]) +reg dma_rdy_int; // Used to signal the end of a conversion read + +// Internal registers used for external ports +reg adc_sdi_o_int; // Used for adc_sdi_o +reg cs_int; // Used for adc_cs_o + +//------------------------------------------------------------------------------ +//----------- Wires Declarations ----------------------------------------------- +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +//----------- Local Parameters ------------------------------------------------- +//------------------------------------------------------------------------------ +// ADC Controller State Machine States +parameter ADC_IDLE_STATE = 11'b00000000001; // Waits for Start Conversion / Start Transmission / Start Read +parameter ADC_WAIT_FOR_DATA_STATE = 11'b00000000010; // Waits for adc_sdo_i to go low (signals new data is available) +parameter ADC_PREP_READ_RESULT_STATE = 11'b00000000100; // Prepares data to perform Status + Data Register Read +parameter ADC_READ_RESULT_STATE = 11'b00000001000; // Reads Status + Data Register +parameter ADC_READ_RESULT_DONE_STATE = 11'b00000010000; // Signals completion of Status + Data Register Read +parameter ADC_PREP_SEND_DATA_STATE = 11'b00000100000; // Prepares data to perform Data Transmit +parameter ADC_SEND_DATA_STATE = 11'b00001000000; // Transmit Data +parameter ADC_SEND_DATA_DONE_STATE = 11'b00010000000; // Signals completion of Data Transmission +parameter ADC_PREP_READ_DATA_STATE = 11'b00100000000; // Prepares data to perform Data Read +parameter ADC_READ_DATA_STATE = 11'b01000000000; // Reads Data +parameter ADC_READ_DATA_DONE_STATE = 11'b10000000000; // Signals completion of Data Read + +// Number of SCLK Periods required for Status + Data Read +parameter ADC_SCLK_PERIODS = 8'd48; + +//------------------------------------------------------------------------------ +//----------- Assign/Always Blocks --------------------------------------------- +//------------------------------------------------------------------------------ +assign adc_sdi_o = adc_sdi_o_int; +assign adc_sclk_o = (((present_state_m1 == ADC_READ_RESULT_STATE)||(present_state_m1 == ADC_SEND_DATA_STATE)||(present_state_m1 == ADC_READ_DATA_STATE))&&(sclk_cnt != 8'd0)) ? adc_clk_i : 1'b1; +assign dma_data_o = dma_rx_data_reg; +assign dma_data_rdy_o = dma_rdy_int; +assign adc_cs_o = cs_int; +assign tx_data_rdy_o = tx_data_rdy_int; +assign rx_data_o = rx_read_data_reg; +assign rx_data_rdy_o = rx_data_rdy_int; + +// Register States +always @(posedge fpga_clk_i) +begin + if(reset_n_i == 1'b0) + begin + present_state <= ADC_IDLE_STATE; + adc_status_o <= 1'b0; + end + else + begin + present_state <= next_state; + adc_status_o <= 1'b1; + end +end + +// State switch logic +always @(posedge fpga_clk_i) +begin + next_state <= present_state; + case(present_state) + ADC_IDLE_STATE: + begin + // If start conversion has been requested + if(start_conversion_i == 1'b1) + begin + next_state <= ADC_WAIT_FOR_DATA_STATE; + end + // If transmit data is required + else if(start_transmission_i == 1'b1) + begin + next_state <= ADC_PREP_SEND_DATA_STATE; + end + // If read data is required + else if(start_read_i == 1'b1) + begin + next_state <= ADC_PREP_READ_DATA_STATE; + end + end + ADC_WAIT_FOR_DATA_STATE: + begin + // If new data is available + if(adc_sdo_i == 1'b0) + begin + next_state <= ADC_PREP_READ_RESULT_STATE; + end + end + ADC_PREP_READ_RESULT_STATE: + begin + if(present_state_m1 == ADC_PREP_READ_RESULT_STATE) + begin + next_state <= ADC_READ_RESULT_STATE; + end + end + ADC_READ_RESULT_STATE: + begin + // If data has been sent + if(sclk_cnt == 8'd0) + begin + next_state <= ADC_READ_RESULT_DONE_STATE; + end + end + ADC_READ_RESULT_DONE_STATE: + begin + next_state <= ADC_IDLE_STATE; + end + ADC_PREP_SEND_DATA_STATE: + begin + if(present_state_m1 == ADC_PREP_SEND_DATA_STATE) + begin + next_state <= ADC_SEND_DATA_STATE; + end + end + ADC_SEND_DATA_STATE: + begin + // If data has been sent + if(sclk_cnt == 8'd0) + begin + next_state <= ADC_SEND_DATA_DONE_STATE; + end + end + ADC_SEND_DATA_DONE_STATE: + begin + next_state <= ADC_IDLE_STATE; + end + ADC_PREP_READ_DATA_STATE: + begin + if(present_state_m1 == ADC_PREP_READ_DATA_STATE) + begin + next_state <= ADC_READ_DATA_STATE; + end + end + ADC_READ_DATA_STATE: + begin + // If data has been sent + if(sclk_cnt == 8'd0) + begin + next_state <= ADC_READ_DATA_DONE_STATE; + end + end + ADC_READ_DATA_DONE_STATE: + begin + next_state <= ADC_IDLE_STATE; + end + default: + begin + next_state <= ADC_IDLE_STATE; + end + endcase +end + +// State output logic +always @(posedge fpga_clk_i) +begin + if(reset_n_i == 1'b0) + begin + dma_rdy_int <= 1'b0; + cs_int <= 1'b1; + tx_data_rdy_int <= 1'b0; + rx_data_rdy_int <= 1'b0; + end + else + begin + case(present_state) + ADC_IDLE_STATE: + begin + dma_rdy_int <= 1'b0; + tx_data_rdy_int <= 1'b1; + rx_data_rdy_int <= 1'b1; + cs_int <= 1'b1; + end + ADC_WAIT_FOR_DATA_STATE: + begin + cs_int <= 1'b0; + end + ADC_PREP_READ_RESULT_STATE: + begin + dma_rdy_int <= 1'b0; + tx_data_reg_switch <= 48'h400044000000; + cs_int <= 1'b0; + end + ADC_READ_RESULT_STATE: + begin + dma_rdy_int <= 1'b0; + cs_int <= 1'b0; + end + ADC_READ_RESULT_DONE_STATE: + begin + // Final data = Status Reg + Data Reg + dma_rx_data_reg <= {rx_data_reg[39:32], rx_data_reg[23:0]}; + dma_rdy_int <= 1'b1; + cs_int <= 1'b1; + end + ADC_PREP_SEND_DATA_STATE: + begin + // Maximum 32 bits transmission (that is why I add 16'd0 to the LSB) + tx_data_rdy_int <= 1'b1; + cs_int <= 1'b1; + tx_data_reg_switch <= {tx_data_i, 16'd0}; + end + ADC_SEND_DATA_STATE: + begin + tx_data_rdy_int <= 1'b0; + cs_int <= 1'b0; + end + ADC_SEND_DATA_DONE_STATE: + begin + tx_data_rdy_int <= 1'b1; + cs_int <= 1'b1; + end + ADC_PREP_READ_DATA_STATE: + begin + // Maximum 32 bits transmission (that is why I add 16'd0 to the LSB) + cs_int <= 1'b1; + rx_data_rdy_int <= 1'b1; + tx_data_reg_switch <= {tx_data_i, 16'd0}; + end + ADC_READ_DATA_STATE: + begin + cs_int <= 1'b0; + rx_data_rdy_int <= 1'b0; + end + ADC_READ_DATA_DONE_STATE: + begin + rx_read_data_reg <= rx_data_reg[31:0]; + cs_int <= 1'b1; + rx_data_rdy_int <= 1'b1; + end + default: + begin + tx_data_rdy_int <= 1'b0; + rx_data_rdy_int <= 1'b0; + dma_rdy_int <= 1'b0; + cs_int <= 1'b1; + end + endcase + end +end + +// Synchronise States between different clock domains +always @(posedge adc_clk_i) +begin + present_state_m1 <= present_state; +end + +// Select size of transfered data according to desired registers (see AD7176_2 Datasheet for details) +always @(posedge fpga_clk_i) +begin + case(tx_data_i[29:24]) + 6'h00: + begin + sclk_demand <= 8'd16; + end + 6'h01, 6'h02, 6'h06, 6'h07, 6'h10, 6'h11, 6'h12, 6'h13, 6'h20, 6'h21, 6'h22, 6'h23, 6'h28, 6'h29, 6'h2a, 6'h2b: + begin + sclk_demand <= 8'd24; + end + 6'h03, 6'h04, 6'h30, 6'h31, 6'h32, 6'h33, 6'h38, 6'h39, 6'h3a, 6'h3b: + begin + sclk_demand <= 8'd32; + end + default: + begin + sclk_demand <= 8'd16; + end + endcase +end + +// Serial Data In +always @(posedge adc_clk_i) +begin + if((present_state_m1 == ADC_READ_RESULT_STATE)||(present_state_m1 == ADC_SEND_DATA_STATE)||(present_state_m1 == ADC_READ_DATA_STATE)) + begin + sclk_cnt <= sclk_cnt - 8'd1; + rx_data_reg <= {rx_data_reg[46:0], adc_sdo_i}; + end + else + begin + if((present_state_m1 == ADC_PREP_SEND_DATA_STATE)||(present_state_m1 == ADC_PREP_READ_DATA_STATE)) + begin + sclk_cnt <= sclk_demand; + end + else + begin + sclk_cnt <= ADC_SCLK_PERIODS; + end + if(present_state_m1 == ADC_IDLE_STATE) + begin + rx_data_reg <= 48'd0; + end + end +end + +// Serial Data Out +always @(negedge adc_clk_i) +begin + if((present_state_m1 == ADC_READ_RESULT_STATE)||(present_state_m1 == ADC_SEND_DATA_STATE)||(present_state_m1 == ADC_READ_DATA_STATE)) + begin + adc_sdi_o_int <= tx_data_reg[47]; + tx_data_reg <= {tx_data_reg[46:0], 1'b0}; + end + else + begin + tx_data_reg <= tx_data_reg_switch; + end +end + +endmodule diff --git a/library/axi_ad7175/axi_ad7175.v b/library/axi_ad7175/axi_ad7175.v new file mode 100644 index 000000000..33c24685e --- /dev/null +++ b/library/axi_ad7175/axi_ad7175.v @@ -0,0 +1,353 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad7175 ( + + // adc interface (clk, data, over-range) + + adc_sdo_i, + adc_sdi_o, + adc_cs_o, + adc_sclk_o, + adc_clk_i, + + // dma interface + + adc_clk, + adc_valid_0, + adc_enable_0, + adc_data_0, + adc_valid_1, + adc_enable_1, + adc_data_1, + adc_dovf, + adc_dunf, + + // axi interface + + s_axi_aclk, + s_axi_aresetn, + s_axi_awvalid, + s_axi_awaddr, + s_axi_awready, + s_axi_wvalid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wready, + s_axi_bvalid, + s_axi_bresp, + s_axi_bready, + s_axi_arvalid, + s_axi_araddr, + s_axi_arready, + s_axi_rvalid, + s_axi_rresp, + s_axi_rdata, + s_axi_rready); + + // parameters + + parameter PCORE_ID = 0; + parameter PCORE_DEVICE_TYPE = 0; + parameter PCORE_ADC_DP_DISABLE = 0; + parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; + parameter C_S_AXI_MIN_SIZE = 32'hffff; + + // adc interface (clk, data, over-range) + + input adc_sdo_i; + output adc_sdi_o; + output adc_cs_o; + output adc_sclk_o; + input adc_clk_i; + + // dma interface + + output adc_clk; + output adc_valid_0; + output adc_enable_0; + output [31:0] adc_data_0; + output adc_valid_1; + output adc_enable_1; + output [31:0] adc_data_1; + input adc_dovf; + input adc_dunf; + + + // axi interface + + input s_axi_aclk; + input s_axi_aresetn; + input s_axi_awvalid; + input [31:0] s_axi_awaddr; + output s_axi_awready; + input s_axi_wvalid; + input [31:0] s_axi_wdata; + input [ 3:0] s_axi_wstrb; + output s_axi_wready; + output s_axi_bvalid; + output [ 1:0] s_axi_bresp; + input s_axi_bready; + input s_axi_arvalid; + input [31:0] s_axi_araddr; + output s_axi_arready; + output s_axi_rvalid; + output [ 1:0] s_axi_rresp; + output [31:0] s_axi_rdata; + input s_axi_rready; + + // internal registers + + reg [31:0] up_rdata = 'd0; + reg up_rack = 'd0; + reg up_wack = 'd0; + + // internal clocks & resets + + wire adc_rst; + wire up_rstn; + wire up_clk; + wire [13:0] up_waddr_s; + wire [13:0] up_raddr_s; + + // internal signals + + wire adc_status_s; + wire up_sel_s; + wire up_wr_s; + wire [13:0] up_addr_s; + wire [31:0] up_wdata_s; + wire [31:0] up_rdata_s[0:2]; + wire up_rack_s[0:2]; + wire up_wack_s[0:2]; + + wire [31:0] adc_data_s; + wire [ 1:0] adc_reg_rw_s; + wire [31:0] adc_reg_address_s; + wire [31:0] adc_reg_data_w_s; + wire [31:0] adc_rx_data_s; + wire adc_rx_data_rdy_s; + wire adc_tx_data_rdy_s; + + // signal name changes + assign adc_clk = s_axi_aclk; + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2]; + up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2]; + up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2]; + end + end + + // channel + + axi_ad7175_channel #( + .CHID(0), + .DP_DISABLE (PCORE_ADC_DP_DISABLE)) + i_channel_0 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data ({8'b0, adc_data_s[23:0]}), + .adc_valid_in(data_rd_ready_s && (adc_data_s[25:24] == 2'b0)), + .adc_data_out (adc_data_0), + .adc_valid (adc_valid_0), + .adc_enable (adc_enable_0), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + // channel + + axi_ad7175_channel #( + .CHID(1), + .DP_DISABLE (PCORE_ADC_DP_DISABLE)) + i_channel_1 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data ({8'b0, adc_data_s[23:0]}), + .adc_valid_in(data_rd_ready_s && (adc_data_s[25:24] == 2'b1)), + .adc_data_out (adc_data_1), + .adc_valid (adc_valid_1), + .adc_enable (adc_enable_1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + // main (device interface) + +ad7175_if ad7175_if_i( + .fpga_clk_i(s_axi_aclk), + .adc_clk_i(adc_clk_i), + .reset_n_i(~adc_rst), + + .start_conversion_i(1'b1), + .dma_data_o(adc_data_s), + .dma_data_rdy_o(data_rd_ready_s), + + .start_transmission_i(adc_reg_rw_s[1]), + .tx_data_i({adc_reg_address_s[7:0], adc_reg_data_w_s[23:0]}), + .tx_data_rdy_o(adc_tx_data_rdy_s), + + .start_read_i(adc_reg_rw_s[0]), + .rx_data_o(adc_rx_data_s), + .rx_data_rdy_o(adc_rx_data_rdy_s), + + .adc_sdo_i(adc_sdo_i), + .adc_sdi_o(adc_sdi_o), + .adc_cs_o(adc_cs_o), + .adc_sclk_o(adc_sclk_o), + .adc_status_o(adc_status_s)); + + // common processor control + + up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status (adc_status_s), + .adc_status_ovf (adc_dovf), + .adc_status_unf (adc_dunf), + .adc_clk_ratio (32'd1), + + .adc_reg_address(adc_reg_address_s), + .adc_reg_data_r(adc_rx_data_s), + .adc_reg_data_w(adc_reg_data_w_s), + .adc_reg_rw(adc_reg_rw_s), + .adc_reg_done(adc_tx_data_rdy_s | adc_rx_data_rdy_s), + + .up_status_pn_err (1'b0), + .up_status_pn_oos (1'b0), + .up_status_or (1'b0), + .delay_clk (), + .delay_rst (), + .delay_sel (), + .delay_rwn (), + .delay_addr (), + .delay_wdata (), + .delay_rdata (), + .delay_ack_t (), + .delay_locked (), + .drp_clk (1'd0), + .drp_rst (), + .drp_sel (), + .drp_wr (), + .drp_addr (), + .drp_wdata (), + .drp_rdata (16'd0), + .drp_ready (1'd0), + .drp_locked (1'd1), + .up_usr_chanmax (), + .adc_usr_chanmax (8'd0), + .up_adc_gpio_in (), + .up_adc_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + + // up bus interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad7175/axi_ad7175_channel.v b/library/axi_ad7175/axi_ad7175_channel.v new file mode 100644 index 000000000..e813c6099 --- /dev/null +++ b/library/axi_ad7175/axi_ad7175_channel.v @@ -0,0 +1,174 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// ADC channel- + +`timescale 1ns/100ps + +module axi_ad7175_channel ( + + // adc interface + adc_clk, + adc_rst, + adc_data, + adc_valid_in, + + // channel interface + adc_data_out, + adc_valid, + adc_enable, + + + // processor interface + up_rstn, + up_clk, + up_wreq, + up_waddr, + up_wdata, + up_wack, + up_rreq, + up_raddr, + up_rdata, + up_rack); + + // parameters + + parameter CHID = 0; + parameter DP_DISABLE = 0; + + // adc interface + + input adc_clk; + input adc_rst; + input [31:0] adc_data; + input adc_valid_in; + // channel interface + + output [31:0] adc_data_out; + output adc_valid; + output adc_enable; + + // processor interface + + input up_rstn; + input up_clk; + input up_wreq; + input [13:0] up_waddr; + input [31:0] up_wdata; + output up_wack; + input up_rreq; + input [13:0] up_raddr; + output [31:0] up_rdata; + output up_rack; + + // internal signals + + wire adc_dfmt_se_s; + wire adc_dfmt_type_s; + wire adc_dfmt_enable_s; + + generate + if (DP_DISABLE == 1) begin + assign adc_valid = adc_valid_in; + assign adc_data_out = {8'b0, adc_data}; + end else begin + ad_datafmt #( + .DATA_WIDTH(32), + .DATA_WIDTH_OUT(32)) + i_ad_datafmt ( + .clk (adc_clk), + .valid (adc_valid_in), + .data (adc_data), + .valid_out (adc_valid), + .data_out (adc_data_out), + .dfmt_enable (adc_dfmt_enable_s), + .dfmt_type (adc_dfmt_type_s), + .dfmt_se (adc_dfmt_se_s)); + end + endgenerate + + up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable), + .adc_iqcor_enb (), + .adc_dcfilt_enb (), + .adc_dfmt_se (adc_dfmt_se_s), + .adc_dfmt_type (adc_dfmt_type_s), + .adc_dfmt_enable (adc_dfmt_enable_s), + .adc_dcfilt_offset (), + .adc_dcfilt_coeff (), + .adc_iqcor_coeff_1 (), + .adc_iqcor_coeff_2 (), + .adc_pnseq_sel (), + .adc_data_sel (), + .adc_pn_err (), + .adc_pn_oos (), + .adc_or (), + .up_adc_pn_err (), + .up_adc_pn_oos (), + .up_adc_or (), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd32), + .adc_usr_datatype_bits (8'd32), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad7175/axi_ad7175_ip.tcl b/library/axi_ad7175/axi_ad7175_ip.tcl new file mode 100644 index 000000000..7aa902360 --- /dev/null +++ b/library/axi_ad7175/axi_ad7175_ip.tcl @@ -0,0 +1,26 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_ad7175 +adi_ip_files axi_ad7175 [list \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/common/up_drp_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "ad7175_if.v" \ + "axi_ad7175.v" \ + "axi_ad7175_channel.v" ] + +adi_ip_properties axi_ad7175 + +ipx::save_core [ipx::current_core] + +