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libraries: Correct module name according to the filename

main
Iulia Moldovan 2022-03-22 12:27:47 +02:00 committed by imoldovan
parent d40db9e204
commit d9ec44657f
19 changed files with 34 additions and 34 deletions
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2
library/axi_adrv9001/axi_adrv9001.v
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@ -408,7 +408,7 @@ module axi_adrv9001 #(
); );
// common processor control // common processor control
axi_ad9001_core #( axi_adrv9001_core #(
.ID (ID), .ID (ID),
.NUM_LANES (NUM_LANES), .NUM_LANES (NUM_LANES),
.CMOS_LVDS_N (CMOS_LVDS_N), .CMOS_LVDS_N (CMOS_LVDS_N),

2
library/axi_adrv9001/axi_adrv9001_core.v
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@ -35,7 +35,7 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module axi_ad9001_core #( module axi_adrv9001_core #(
parameter ID = 0, parameter ID = 0,
parameter CMOS_LVDS_N = 0, parameter CMOS_LVDS_N = 0,
parameter USE_RX_CLK_FOR_TX = 0, parameter USE_RX_CLK_FOR_TX = 0,

2
library/axi_dmac/address_generator.v
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@ -35,7 +35,7 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module dmac_address_generator #( module address_generator #(
parameter ID_WIDTH = 3, parameter ID_WIDTH = 3,
parameter DMA_DATA_WIDTH = 64, parameter DMA_DATA_WIDTH = 64,

2
library/axi_dmac/axi_dmac_transfer.v
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@ -315,7 +315,7 @@ assign dma_response_ready = req_response_ready;
end endgenerate end endgenerate
dmac_request_arb #( request_arb #(
.DMA_DATA_WIDTH_SRC (DMA_DATA_WIDTH_SRC), .DMA_DATA_WIDTH_SRC (DMA_DATA_WIDTH_SRC),
.DMA_DATA_WIDTH_DEST (DMA_DATA_WIDTH_DEST), .DMA_DATA_WIDTH_DEST (DMA_DATA_WIDTH_DEST),
.DMA_LENGTH_WIDTH (DMA_LENGTH_WIDTH), .DMA_LENGTH_WIDTH (DMA_LENGTH_WIDTH),

2
library/axi_dmac/data_mover.v
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@ -35,7 +35,7 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module dmac_data_mover #( module data_mover #(
parameter ID_WIDTH = 3, parameter ID_WIDTH = 3,
parameter DATA_WIDTH = 64, parameter DATA_WIDTH = 64,

6
library/axi_dmac/dest_axi_mm.v
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@ -35,7 +35,7 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module dmac_dest_mm_axi #( module dest_axi_mm #(
parameter ID_WIDTH = 3, parameter ID_WIDTH = 3,
parameter DMA_DATA_WIDTH = 64, parameter DMA_DATA_WIDTH = 64,
@ -109,7 +109,7 @@ module dmac_dest_mm_axi #(
wire address_enabled; wire address_enabled;
dmac_address_generator #( address_generator #(
.ID_WIDTH(ID_WIDTH), .ID_WIDTH(ID_WIDTH),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
.BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH), .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH),
@ -152,7 +152,7 @@ assign m_axi_wlast = fifo_last;
assign m_axi_wdata = fifo_data; assign m_axi_wdata = fifo_data;
assign m_axi_wstrb = fifo_strb; assign m_axi_wstrb = fifo_strb;
dmac_response_handler #( response_handler #(
.ID_WIDTH(ID_WIDTH) .ID_WIDTH(ID_WIDTH)
) i_response_handler ( ) i_response_handler (
.clk(m_axi_aclk), .clk(m_axi_aclk),

4
library/axi_dmac/dest_axi_stream.v
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@ -35,7 +35,7 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module dmac_dest_axi_stream #( module dest_axi_stream #(
parameter ID_WIDTH = 3, parameter ID_WIDTH = 3,
parameter S_AXIS_DATA_WIDTH = 64, parameter S_AXIS_DATA_WIDTH = 64,
@ -133,7 +133,7 @@ always @(posedge s_axis_aclk) begin
end end
end end
dmac_response_generator # ( response_generator # (
.ID_WIDTH(ID_WIDTH) .ID_WIDTH(ID_WIDTH)
) i_response_generator ( ) i_response_generator (
.clk(s_axis_aclk), .clk(s_axis_aclk),

4
library/axi_dmac/dest_fifo_inf.v
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@ -35,7 +35,7 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module dmac_dest_fifo_inf #( module dest_fifo_inf #(
parameter ID_WIDTH = 3, parameter ID_WIDTH = 3,
parameter DATA_WIDTH = 64, parameter DATA_WIDTH = 64,
@ -121,7 +121,7 @@ always @(posedge clk) begin
end end
end end
dmac_response_generator # ( response_generator # (
.ID_WIDTH(ID_WIDTH) .ID_WIDTH(ID_WIDTH)
) i_response_generator ( ) i_response_generator (
.clk(clk), .clk(clk),

16
library/axi_dmac/request_arb.v
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@ -35,7 +35,7 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module dmac_request_arb #( module request_arb #(
parameter DMA_DATA_WIDTH_SRC = 64, parameter DMA_DATA_WIDTH_SRC = 64,
parameter DMA_DATA_WIDTH_DEST = 64, parameter DMA_DATA_WIDTH_DEST = 64,
parameter DMA_LENGTH_WIDTH = 24, parameter DMA_LENGTH_WIDTH = 24,
@ -353,7 +353,7 @@ assign dbg_dest_data_id = dest_data_response_id;
assign dest_data_request_id = dest_address_id; assign dest_data_request_id = dest_address_id;
dmac_dest_mm_axi #( dest_axi_mm #(
.ID_WIDTH(ID_WIDTH), .ID_WIDTH(ID_WIDTH),
.DMA_DATA_WIDTH(DMA_DATA_WIDTH_DEST), .DMA_DATA_WIDTH(DMA_DATA_WIDTH_DEST),
.DMA_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH), .DMA_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
@ -499,7 +499,7 @@ assign dbg_dest_address_id = 'h00;
assign dbg_dest_data_id = data_id; assign dbg_dest_data_id = data_id;
dmac_dest_axi_stream #( dest_axi_stream #(
.ID_WIDTH(ID_WIDTH), .ID_WIDTH(ID_WIDTH),
.S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_DEST), .S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_DEST),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST) .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST)
@ -561,7 +561,7 @@ assign dest_data_request_id = dest_request_id;
assign dbg_dest_address_id = 'h00; assign dbg_dest_address_id = 'h00;
assign dbg_dest_data_id = data_id; assign dbg_dest_data_id = data_id;
dmac_dest_fifo_inf #( dest_fifo_inf #(
.ID_WIDTH(ID_WIDTH), .ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(DMA_DATA_WIDTH_DEST), .DATA_WIDTH(DMA_DATA_WIDTH_DEST),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST) .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST)
@ -622,7 +622,7 @@ assign src_ext_resetn = m_src_axi_aresetn;
assign dbg_src_address_id = src_address_id; assign dbg_src_address_id = src_address_id;
assign dbg_src_data_id = src_data_id; assign dbg_src_data_id = src_data_id;
dmac_src_mm_axi #( src_axi_mm #(
.ID_WIDTH(ID_WIDTH), .ID_WIDTH(ID_WIDTH),
.DMA_DATA_WIDTH(DMA_DATA_WIDTH_SRC), .DMA_DATA_WIDTH(DMA_DATA_WIDTH_SRC),
.DMA_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH), .DMA_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
@ -709,7 +709,7 @@ assign src_response_resp = 2'b0;
*/ */
dmac_src_axi_stream #( src_axi_stream #(
.ID_WIDTH(ID_WIDTH), .ID_WIDTH(ID_WIDTH),
.S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_SRC), .S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_SRC),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC) .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC)
@ -814,7 +814,7 @@ assign src_response_valid = 1'b0;
assign src_response_resp = 2'b0; assign src_response_resp = 2'b0;
*/ */
dmac_src_fifo_inf #( src_fifo_inf #(
.ID_WIDTH(ID_WIDTH), .ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(DMA_DATA_WIDTH_SRC), .DATA_WIDTH(DMA_DATA_WIDTH_SRC),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC) .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC)
@ -1132,7 +1132,7 @@ assign src_response_empty = 1'b1;
assign src_response_ready = 1'b1; assign src_response_ready = 1'b1;
*/ */
dmac_request_generator #( request_generator #(
.ID_WIDTH(ID_WIDTH), .ID_WIDTH(ID_WIDTH),
.BURSTS_PER_TRANSFER_WIDTH(BURSTS_PER_TRANSFER_WIDTH) .BURSTS_PER_TRANSFER_WIDTH(BURSTS_PER_TRANSFER_WIDTH)
) i_req_gen ( ) i_req_gen (

2
library/axi_dmac/request_generator.v
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@ -35,7 +35,7 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module dmac_request_generator #( module request_generator #(
parameter ID_WIDTH = 3, parameter ID_WIDTH = 3,
parameter BURSTS_PER_TRANSFER_WIDTH = 17)( parameter BURSTS_PER_TRANSFER_WIDTH = 17)(

2
library/axi_dmac/response_generator.v
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@ -35,7 +35,7 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module dmac_response_generator #( module response_generator #(
parameter ID_WIDTH = 3)( parameter ID_WIDTH = 3)(

2
library/axi_dmac/response_handler.v
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@ -35,7 +35,7 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module dmac_response_handler #( module response_handler #(
parameter ID_WIDTH = 3)( parameter ID_WIDTH = 3)(

4
library/axi_dmac/src_axi_mm.v
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@ -35,7 +35,7 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module dmac_src_mm_axi #( module src_axi_mm #(
parameter ID_WIDTH = 3, parameter ID_WIDTH = 3,
parameter DMA_DATA_WIDTH = 64, parameter DMA_DATA_WIDTH = 64,
@ -146,7 +146,7 @@ splitter #(
}) })
); );
dmac_address_generator #( address_generator #(
.ID_WIDTH(ID_WIDTH), .ID_WIDTH(ID_WIDTH),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
.BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH), .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH),

4
library/axi_dmac/src_axi_stream.v
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@ -35,7 +35,7 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module dmac_src_axi_stream #( module src_axi_stream #(
parameter ID_WIDTH = 3, parameter ID_WIDTH = 3,
parameter S_AXIS_DATA_WIDTH = 64, parameter S_AXIS_DATA_WIDTH = 64,
@ -86,7 +86,7 @@ module dmac_src_axi_stream #(
assign enabled = enable; assign enabled = enable;
dmac_data_mover # ( data_mover # (
.ID_WIDTH(ID_WIDTH), .ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(S_AXIS_DATA_WIDTH), .DATA_WIDTH(S_AXIS_DATA_WIDTH),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),

4
library/axi_dmac/src_fifo_inf.v
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@ -35,7 +35,7 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module dmac_src_fifo_inf #( module src_fifo_inf #(
parameter ID_WIDTH = 3, parameter ID_WIDTH = 3,
parameter DATA_WIDTH = 64, parameter DATA_WIDTH = 64,
@ -87,7 +87,7 @@ begin
end end
end end
dmac_data_mover # ( data_mover # (
.ID_WIDTH(ID_WIDTH), .ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(DATA_WIDTH), .DATA_WIDTH(DATA_WIDTH),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH) .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)

2
library/intel/jesd204_phy/jesd204_phy_glue.v
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@ -35,7 +35,7 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module jesd204_glue #( module jesd204_phy_glue #(
parameter WIDTH = 20, parameter WIDTH = 20,
parameter CONST_WIDTH = 1, parameter CONST_WIDTH = 1,
parameter NUM_OF_LANES = 1, parameter NUM_OF_LANES = 1,

2
library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl
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@ -58,7 +58,7 @@ set_module_property INTERNAL true
# files # files
ad_ip_files jesd204_glue [list \ ad_ip_files jesd204_phy_glue [list \
jesd204_phy_glue.v \ jesd204_phy_glue.v \
] ]

2
library/jesd204/jesd204_tx_static_config/jesd204_ilas_cfg_static.v
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@ -44,7 +44,7 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module jesd204_ilas_config_static #( module jesd204_ilas_cfg_static #(
parameter DID = 8'h00, parameter DID = 8'h00,
parameter BID = 4'h0, parameter BID = 4'h0,
parameter L = 5'h3, parameter L = 5'h3,

2
library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.v
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@ -105,7 +105,7 @@ assign device_cfg_lmfc_offset = 1;
assign device_cfg_sysref_oneshot = SYSREF_ONE_SHOT; assign device_cfg_sysref_oneshot = SYSREF_ONE_SHOT;
assign device_cfg_sysref_disable = SYSREF_DISABLE; assign device_cfg_sysref_disable = SYSREF_DISABLE;
jesd204_ilas_config_static #( jesd204_ilas_cfg_static #(
.DID(8'h00), .DID(8'h00),
.BID(5'h00), .BID(5'h00),
.L(NUM_LANES - 1), .L(NUM_LANES - 1),