From d9ec44657f035b508451c73b3f1e47eb0e2eba9b Mon Sep 17 00:00:00 2001 From: Iulia Moldovan Date: Tue, 22 Mar 2022 12:27:47 +0200 Subject: [PATCH] libraries: Correct module name according to the filename --- library/axi_adrv9001/axi_adrv9001.v | 2 +- library/axi_adrv9001/axi_adrv9001_core.v | 2 +- library/axi_dmac/address_generator.v | 2 +- library/axi_dmac/axi_dmac_transfer.v | 2 +- library/axi_dmac/data_mover.v | 2 +- library/axi_dmac/dest_axi_mm.v | 6 +++--- library/axi_dmac/dest_axi_stream.v | 4 ++-- library/axi_dmac/dest_fifo_inf.v | 4 ++-- library/axi_dmac/request_arb.v | 16 ++++++++-------- library/axi_dmac/request_generator.v | 2 +- library/axi_dmac/response_generator.v | 2 +- library/axi_dmac/response_handler.v | 2 +- library/axi_dmac/src_axi_mm.v | 4 ++-- library/axi_dmac/src_axi_stream.v | 4 ++-- library/axi_dmac/src_fifo_inf.v | 4 ++-- library/intel/jesd204_phy/jesd204_phy_glue.v | 2 +- .../intel/jesd204_phy/jesd204_phy_glue_hw.tcl | 4 ++-- .../jesd204_ilas_cfg_static.v | 2 +- .../jesd204_tx_static_config.v | 2 +- 19 files changed, 34 insertions(+), 34 deletions(-) diff --git a/library/axi_adrv9001/axi_adrv9001.v b/library/axi_adrv9001/axi_adrv9001.v index 6d8b82ac6..cdde36d84 100644 --- a/library/axi_adrv9001/axi_adrv9001.v +++ b/library/axi_adrv9001/axi_adrv9001.v @@ -408,7 +408,7 @@ module axi_adrv9001 #( ); // common processor control - axi_ad9001_core #( + axi_adrv9001_core #( .ID (ID), .NUM_LANES (NUM_LANES), .CMOS_LVDS_N (CMOS_LVDS_N), diff --git a/library/axi_adrv9001/axi_adrv9001_core.v b/library/axi_adrv9001/axi_adrv9001_core.v index c403b7755..13e50d5e8 100644 --- a/library/axi_adrv9001/axi_adrv9001_core.v +++ b/library/axi_adrv9001/axi_adrv9001_core.v @@ -35,7 +35,7 @@ `timescale 1ns/100ps -module axi_ad9001_core #( +module axi_adrv9001_core #( parameter ID = 0, parameter CMOS_LVDS_N = 0, parameter USE_RX_CLK_FOR_TX = 0, diff --git a/library/axi_dmac/address_generator.v b/library/axi_dmac/address_generator.v index 499667579..4b9593b4d 100644 --- a/library/axi_dmac/address_generator.v +++ b/library/axi_dmac/address_generator.v @@ -35,7 +35,7 @@ `timescale 1ns/100ps -module dmac_address_generator #( +module address_generator #( parameter ID_WIDTH = 3, parameter DMA_DATA_WIDTH = 64, diff --git a/library/axi_dmac/axi_dmac_transfer.v b/library/axi_dmac/axi_dmac_transfer.v index 1eac9175a..45dc1456d 100644 --- a/library/axi_dmac/axi_dmac_transfer.v +++ b/library/axi_dmac/axi_dmac_transfer.v @@ -315,7 +315,7 @@ assign dma_response_ready = req_response_ready; end endgenerate -dmac_request_arb #( +request_arb #( .DMA_DATA_WIDTH_SRC (DMA_DATA_WIDTH_SRC), .DMA_DATA_WIDTH_DEST (DMA_DATA_WIDTH_DEST), .DMA_LENGTH_WIDTH (DMA_LENGTH_WIDTH), diff --git a/library/axi_dmac/data_mover.v b/library/axi_dmac/data_mover.v index fec0d5e7f..1756e3d03 100644 --- a/library/axi_dmac/data_mover.v +++ b/library/axi_dmac/data_mover.v @@ -35,7 +35,7 @@ `timescale 1ns/100ps -module dmac_data_mover #( +module data_mover #( parameter ID_WIDTH = 3, parameter DATA_WIDTH = 64, diff --git a/library/axi_dmac/dest_axi_mm.v b/library/axi_dmac/dest_axi_mm.v index 338bb3841..251cf42df 100644 --- a/library/axi_dmac/dest_axi_mm.v +++ b/library/axi_dmac/dest_axi_mm.v @@ -35,7 +35,7 @@ `timescale 1ns/100ps -module dmac_dest_mm_axi #( +module dest_axi_mm #( parameter ID_WIDTH = 3, parameter DMA_DATA_WIDTH = 64, @@ -109,7 +109,7 @@ module dmac_dest_mm_axi #( wire address_enabled; -dmac_address_generator #( +address_generator #( .ID_WIDTH(ID_WIDTH), .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH), @@ -152,7 +152,7 @@ assign m_axi_wlast = fifo_last; assign m_axi_wdata = fifo_data; assign m_axi_wstrb = fifo_strb; -dmac_response_handler #( +response_handler #( .ID_WIDTH(ID_WIDTH) ) i_response_handler ( .clk(m_axi_aclk), diff --git a/library/axi_dmac/dest_axi_stream.v b/library/axi_dmac/dest_axi_stream.v index b377d8e68..f65cbd311 100644 --- a/library/axi_dmac/dest_axi_stream.v +++ b/library/axi_dmac/dest_axi_stream.v @@ -35,7 +35,7 @@ `timescale 1ns/100ps -module dmac_dest_axi_stream #( +module dest_axi_stream #( parameter ID_WIDTH = 3, parameter S_AXIS_DATA_WIDTH = 64, @@ -133,7 +133,7 @@ always @(posedge s_axis_aclk) begin end end -dmac_response_generator # ( +response_generator # ( .ID_WIDTH(ID_WIDTH) ) i_response_generator ( .clk(s_axis_aclk), diff --git a/library/axi_dmac/dest_fifo_inf.v b/library/axi_dmac/dest_fifo_inf.v index 486c7c3c8..2986aa93a 100644 --- a/library/axi_dmac/dest_fifo_inf.v +++ b/library/axi_dmac/dest_fifo_inf.v @@ -35,7 +35,7 @@ `timescale 1ns/100ps -module dmac_dest_fifo_inf #( +module dest_fifo_inf #( parameter ID_WIDTH = 3, parameter DATA_WIDTH = 64, @@ -121,7 +121,7 @@ always @(posedge clk) begin end end -dmac_response_generator # ( +response_generator # ( .ID_WIDTH(ID_WIDTH) ) i_response_generator ( .clk(clk), diff --git a/library/axi_dmac/request_arb.v b/library/axi_dmac/request_arb.v index 70b2a8dc6..879b586dd 100644 --- a/library/axi_dmac/request_arb.v +++ b/library/axi_dmac/request_arb.v @@ -35,7 +35,7 @@ `timescale 1ns/100ps -module dmac_request_arb #( +module request_arb #( parameter DMA_DATA_WIDTH_SRC = 64, parameter DMA_DATA_WIDTH_DEST = 64, parameter DMA_LENGTH_WIDTH = 24, @@ -353,7 +353,7 @@ assign dbg_dest_data_id = dest_data_response_id; assign dest_data_request_id = dest_address_id; -dmac_dest_mm_axi #( +dest_axi_mm #( .ID_WIDTH(ID_WIDTH), .DMA_DATA_WIDTH(DMA_DATA_WIDTH_DEST), .DMA_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH), @@ -499,7 +499,7 @@ assign dbg_dest_address_id = 'h00; assign dbg_dest_data_id = data_id; -dmac_dest_axi_stream #( +dest_axi_stream #( .ID_WIDTH(ID_WIDTH), .S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_DEST), .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST) @@ -561,7 +561,7 @@ assign dest_data_request_id = dest_request_id; assign dbg_dest_address_id = 'h00; assign dbg_dest_data_id = data_id; -dmac_dest_fifo_inf #( +dest_fifo_inf #( .ID_WIDTH(ID_WIDTH), .DATA_WIDTH(DMA_DATA_WIDTH_DEST), .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST) @@ -622,7 +622,7 @@ assign src_ext_resetn = m_src_axi_aresetn; assign dbg_src_address_id = src_address_id; assign dbg_src_data_id = src_data_id; -dmac_src_mm_axi #( +src_axi_mm #( .ID_WIDTH(ID_WIDTH), .DMA_DATA_WIDTH(DMA_DATA_WIDTH_SRC), .DMA_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH), @@ -709,7 +709,7 @@ assign src_response_resp = 2'b0; */ -dmac_src_axi_stream #( +src_axi_stream #( .ID_WIDTH(ID_WIDTH), .S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_SRC), .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC) @@ -814,7 +814,7 @@ assign src_response_valid = 1'b0; assign src_response_resp = 2'b0; */ -dmac_src_fifo_inf #( +src_fifo_inf #( .ID_WIDTH(ID_WIDTH), .DATA_WIDTH(DMA_DATA_WIDTH_SRC), .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC) @@ -1132,7 +1132,7 @@ assign src_response_empty = 1'b1; assign src_response_ready = 1'b1; */ -dmac_request_generator #( +request_generator #( .ID_WIDTH(ID_WIDTH), .BURSTS_PER_TRANSFER_WIDTH(BURSTS_PER_TRANSFER_WIDTH) ) i_req_gen ( diff --git a/library/axi_dmac/request_generator.v b/library/axi_dmac/request_generator.v index 3aee1e63b..2a33f0a3b 100644 --- a/library/axi_dmac/request_generator.v +++ b/library/axi_dmac/request_generator.v @@ -35,7 +35,7 @@ `timescale 1ns/100ps -module dmac_request_generator #( +module request_generator #( parameter ID_WIDTH = 3, parameter BURSTS_PER_TRANSFER_WIDTH = 17)( diff --git a/library/axi_dmac/response_generator.v b/library/axi_dmac/response_generator.v index 4e7e87b72..2d0493dea 100644 --- a/library/axi_dmac/response_generator.v +++ b/library/axi_dmac/response_generator.v @@ -35,7 +35,7 @@ `timescale 1ns/100ps -module dmac_response_generator #( +module response_generator #( parameter ID_WIDTH = 3)( diff --git a/library/axi_dmac/response_handler.v b/library/axi_dmac/response_handler.v index 9dec16b7d..a42099299 100644 --- a/library/axi_dmac/response_handler.v +++ b/library/axi_dmac/response_handler.v @@ -35,7 +35,7 @@ `timescale 1ns/100ps -module dmac_response_handler #( +module response_handler #( parameter ID_WIDTH = 3)( diff --git a/library/axi_dmac/src_axi_mm.v b/library/axi_dmac/src_axi_mm.v index 5d5291d93..e50007642 100644 --- a/library/axi_dmac/src_axi_mm.v +++ b/library/axi_dmac/src_axi_mm.v @@ -35,7 +35,7 @@ `timescale 1ns/100ps -module dmac_src_mm_axi #( +module src_axi_mm #( parameter ID_WIDTH = 3, parameter DMA_DATA_WIDTH = 64, @@ -146,7 +146,7 @@ splitter #( }) ); -dmac_address_generator #( +address_generator #( .ID_WIDTH(ID_WIDTH), .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH), diff --git a/library/axi_dmac/src_axi_stream.v b/library/axi_dmac/src_axi_stream.v index e9d59c061..7901bce26 100644 --- a/library/axi_dmac/src_axi_stream.v +++ b/library/axi_dmac/src_axi_stream.v @@ -35,7 +35,7 @@ `timescale 1ns/100ps -module dmac_src_axi_stream #( +module src_axi_stream #( parameter ID_WIDTH = 3, parameter S_AXIS_DATA_WIDTH = 64, @@ -86,7 +86,7 @@ module dmac_src_axi_stream #( assign enabled = enable; -dmac_data_mover # ( +data_mover # ( .ID_WIDTH(ID_WIDTH), .DATA_WIDTH(S_AXIS_DATA_WIDTH), .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), diff --git a/library/axi_dmac/src_fifo_inf.v b/library/axi_dmac/src_fifo_inf.v index a9e417bb9..79409b35f 100644 --- a/library/axi_dmac/src_fifo_inf.v +++ b/library/axi_dmac/src_fifo_inf.v @@ -35,7 +35,7 @@ `timescale 1ns/100ps -module dmac_src_fifo_inf #( +module src_fifo_inf #( parameter ID_WIDTH = 3, parameter DATA_WIDTH = 64, @@ -87,7 +87,7 @@ begin end end -dmac_data_mover # ( +data_mover # ( .ID_WIDTH(ID_WIDTH), .DATA_WIDTH(DATA_WIDTH), .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH) diff --git a/library/intel/jesd204_phy/jesd204_phy_glue.v b/library/intel/jesd204_phy/jesd204_phy_glue.v index 7c3359d84..8c8f4d58f 100644 --- a/library/intel/jesd204_phy/jesd204_phy_glue.v +++ b/library/intel/jesd204_phy/jesd204_phy_glue.v @@ -35,7 +35,7 @@ `timescale 1ns/100ps -module jesd204_glue #( +module jesd204_phy_glue #( parameter WIDTH = 20, parameter CONST_WIDTH = 1, parameter NUM_OF_LANES = 1, diff --git a/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl b/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl index 3dbcd835a..d4444abe8 100644 --- a/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl +++ b/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl @@ -58,7 +58,7 @@ set_module_property INTERNAL true # files -ad_ip_files jesd204_glue [list \ +ad_ip_files jesd204_phy_glue [list \ jesd204_phy_glue.v \ ] @@ -272,7 +272,7 @@ proc jesd204_phy_glue_elab {} { if {$bonding_clocks_en && $num_of_lanes > 6} { glue_add_if $num_of_lanes tx_bonding_clocks hssi_bonded_clock sink true - glue_add_if_port $num_of_lanes tx_bonding_clocks tx_bonding_clocks clk Input 6 true + glue_add_if_port $num_of_lanes tx_bonding_clocks tx_bonding_clocks clk Input 6 true } else { glue_add_tx_serial_clk $num_of_lanes } diff --git a/library/jesd204/jesd204_tx_static_config/jesd204_ilas_cfg_static.v b/library/jesd204/jesd204_tx_static_config/jesd204_ilas_cfg_static.v index 6517035d4..3a2b8dbfc 100755 --- a/library/jesd204/jesd204_tx_static_config/jesd204_ilas_cfg_static.v +++ b/library/jesd204/jesd204_tx_static_config/jesd204_ilas_cfg_static.v @@ -44,7 +44,7 @@ `timescale 1ns/100ps -module jesd204_ilas_config_static #( +module jesd204_ilas_cfg_static #( parameter DID = 8'h00, parameter BID = 4'h0, parameter L = 5'h3, diff --git a/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.v b/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.v index ba159a46c..64f36f797 100755 --- a/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.v +++ b/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.v @@ -105,7 +105,7 @@ assign device_cfg_lmfc_offset = 1; assign device_cfg_sysref_oneshot = SYSREF_ONE_SHOT; assign device_cfg_sysref_disable = SYSREF_DISABLE; -jesd204_ilas_config_static #( +jesd204_ilas_cfg_static #( .DID(8'h00), .BID(5'h00), .L(NUM_LANES - 1),