From d931b2ee64079b7d666baed5bbbf34cf76616978 Mon Sep 17 00:00:00 2001 From: Shrutika Redkar Date: Wed, 29 Jun 2016 15:05:44 -0400 Subject: [PATCH] ad9162 core verilog files --- library/axi_ad9162/axi_ad9162.v | 260 ++++++++++ library/axi_ad9162/axi_ad9162_channel.v | 630 ++++++++++++++++++++++++ library/axi_ad9162/axi_ad9162_core.v | 234 +++++++++ library/axi_ad9162/axi_ad9162_if.v | 145 ++++++ library/axi_ad9162/axi_ad9162_ip.tcl | 35 ++ 5 files changed, 1304 insertions(+) create mode 100644 library/axi_ad9162/axi_ad9162.v create mode 100644 library/axi_ad9162/axi_ad9162_channel.v create mode 100644 library/axi_ad9162/axi_ad9162_core.v create mode 100644 library/axi_ad9162/axi_ad9162_if.v create mode 100644 library/axi_ad9162/axi_ad9162_ip.tcl diff --git a/library/axi_ad9162/axi_ad9162.v b/library/axi_ad9162/axi_ad9162.v new file mode 100644 index 000000000..0590af546 --- /dev/null +++ b/library/axi_ad9162/axi_ad9162.v @@ -0,0 +1,260 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns / 1ps + +module axi_ad9162( + + // jesd interface + // tx_clk is (line-rate/40) + + tx_clk, + tx_data, + + // dma interface + + dac_clk, + dac_valid_0, + dac_enable_0, + dac_ddata_0, + dac_dovf, + dac_dunf, + + // axi interface + + s_axi_aclk, + s_axi_aresetn, + s_axi_awvalid, + s_axi_awaddr, + s_axi_awprot, + s_axi_awready, + s_axi_wvalid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wready, + s_axi_bvalid, + s_axi_bresp, + s_axi_bready, + s_axi_arvalid, + s_axi_araddr, + s_axi_arprot, + s_axi_arready, + s_axi_rvalid, + s_axi_rdata, + s_axi_rresp, + s_axi_rready); + + // parameters + + parameter ID = 0; + parameter DAC_DATAPATH_DISABLE = 0; + + // jesd interface + // tx_clk is (line-rate/40) + + input tx_clk; + output [255:0] tx_data; + + // dma interface + + output dac_clk; + output dac_valid_0; + output dac_enable_0; + input [255:0] dac_ddata_0; + input dac_dovf; + input dac_dunf; + + // axi interface + + input s_axi_aclk; + input s_axi_aresetn; + input s_axi_awvalid; + input [ 31:0] s_axi_awaddr; + input [ 2:0] s_axi_awprot; + output s_axi_awready; + input s_axi_wvalid; + input [ 31:0] s_axi_wdata; + input [ 3:0] s_axi_wstrb; + output s_axi_wready; + output s_axi_bvalid; + output [ 1:0] s_axi_bresp; + input s_axi_bready; + input s_axi_arvalid; + input [ 31:0] s_axi_araddr; + input [ 2:0] s_axi_arprot; + output s_axi_arready; + output s_axi_rvalid; + output [ 31:0] s_axi_rdata; + output [ 1:0] s_axi_rresp; + input s_axi_rready; + + // internal clocks and resets + + wire dac_rst; + wire up_clk; + wire up_rstn; + + // internal signals + + wire [255:0] tx_data_s; + wire [ 15:0] dac_data_0_0_s; + wire [ 15:0] dac_data_0_1_s; + wire [ 15:0] dac_data_0_2_s; + wire [ 15:0] dac_data_0_3_s; + wire [ 15:0] dac_data_0_4_s; + wire [ 15:0] dac_data_0_5_s; + wire [ 15:0] dac_data_0_6_s; + wire [ 15:0] dac_data_0_7_s; + wire [ 15:0] dac_data_0_8_s; + wire [ 15:0] dac_data_0_9_s; + wire [ 15:0] dac_data_0_10_s; + wire [ 15:0] dac_data_0_11_s; + wire [ 15:0] dac_data_0_12_s; + wire [ 15:0] dac_data_0_13_s; + wire [ 15:0] dac_data_0_14_s; + wire [ 15:0] dac_data_0_15_s; + wire up_wreq_s; + wire [ 13:0] up_waddr_s; + wire [ 31:0] up_wdata_s; + wire up_wack_s; + wire up_rreq_s; + wire [ 13:0] up_raddr_s; + wire [ 31:0] up_rdata_s; + wire up_rack_s; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + assign tx_data = tx_data_s; + + // device interface + + axi_ad9162_if i_if ( + .tx_clk (tx_clk), + .tx_data (tx_data_s), + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_data_0_0 (dac_data_0_0_s), + .dac_data_0_1 (dac_data_0_1_s), + .dac_data_0_2 (dac_data_0_2_s), + .dac_data_0_3 (dac_data_0_3_s), + .dac_data_0_4 (dac_data_0_4_s), + .dac_data_0_5 (dac_data_0_5_s), + .dac_data_0_6 (dac_data_0_6_s), + .dac_data_0_7 (dac_data_0_7_s), + .dac_data_0_8 (dac_data_0_8_s), + .dac_data_0_9 (dac_data_0_9_s), + .dac_data_0_10 (dac_data_0_10_s), + .dac_data_0_11 (dac_data_0_11_s), + .dac_data_0_12 (dac_data_0_12_s), + .dac_data_0_13 (dac_data_0_13_s), + .dac_data_0_14 (dac_data_0_14_s), + .dac_data_0_15 (dac_data_0_15_s)); + + // core + + axi_ad9162_core #(.ID(ID), .DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)) i_core ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_data_0_0 (dac_data_0_0_s), + .dac_data_0_1 (dac_data_0_1_s), + .dac_data_0_2 (dac_data_0_2_s), + .dac_data_0_3 (dac_data_0_3_s), + .dac_data_0_4 (dac_data_0_4_s), + .dac_data_0_5 (dac_data_0_5_s), + .dac_data_0_6 (dac_data_0_6_s), + .dac_data_0_7 (dac_data_0_7_s), + .dac_data_0_8 (dac_data_0_8_s), + .dac_data_0_9 (dac_data_0_9_s), + .dac_data_0_10 (dac_data_0_10_s), + .dac_data_0_11 (dac_data_0_11_s), + .dac_data_0_12 (dac_data_0_12_s), + .dac_data_0_13 (dac_data_0_13_s), + .dac_data_0_14 (dac_data_0_14_s), + .dac_data_0_15 (dac_data_0_15_s), + .dac_valid_0 (dac_valid_0), + .dac_enable_0 (dac_enable_0), + .dac_ddata_0 (dac_ddata_0), + .dac_dovf (dac_dovf), + .dac_dunf (dac_dunf), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + + // up bus interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + +endmodule + diff --git a/library/axi_ad9162/axi_ad9162_channel.v b/library/axi_ad9162/axi_ad9162_channel.v new file mode 100644 index 000000000..238107a43 --- /dev/null +++ b/library/axi_ad9162/axi_ad9162_channel.v @@ -0,0 +1,630 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns / 1ps + +module axi_ad9162_channel( + + // dac interface + + dac_clk, + dac_rst, + dac_enable, + dac_data, + dma_data, + + // processor interface + + dac_data_sync, + dac_dds_format, + + // bus interface + + up_rstn, + up_clk, + up_wreq, + up_waddr, + up_wdata, + up_wack, + up_rreq, + up_raddr, + up_rdata, + up_rack); + + // parameters + + parameter CHANNEL_ID = 32'h0; + parameter DATAPATH_DISABLE = 0; + + // dac interface + + input dac_clk; + input dac_rst; + output dac_enable; + output [255:0] dac_data; + input [255:0] dma_data; + + // processor interface + + input dac_data_sync; + input dac_dds_format; + + // bus interface + + input up_rstn; + input up_clk; + input up_wreq; + input [13:0] up_waddr; + input [31:0] up_wdata; + output up_wack; + input up_rreq; + input [13:0] up_raddr; + output [31:0] up_rdata; + output up_rack; + + // internal registers + + reg dac_enable = 'd0; + reg [255:0] dac_data = 'd0; + reg [15: 0] dac_dds_phase_0_0 = 'd0; + reg [15: 0] dac_dds_phase_0_1 = 'd0; + reg [15: 0] dac_dds_phase_1_0 = 'd0; + reg [15: 0] dac_dds_phase_1_1 = 'd0; + reg [15: 0] dac_dds_phase_2_0 = 'd0; + reg [15: 0] dac_dds_phase_2_1 = 'd0; + reg [15: 0] dac_dds_phase_3_0 = 'd0; + reg [15: 0] dac_dds_phase_3_1 = 'd0; + reg [15: 0] dac_dds_phase_4_0 = 'd0; + reg [15: 0] dac_dds_phase_4_1 = 'd0; + reg [15: 0] dac_dds_phase_5_0 = 'd0; + reg [15: 0] dac_dds_phase_5_1 = 'd0; + reg [15: 0] dac_dds_phase_6_0 = 'd0; + reg [15: 0] dac_dds_phase_6_1 = 'd0; + reg [15: 0] dac_dds_phase_7_0 = 'd0; + reg [15: 0] dac_dds_phase_7_1 = 'd0; + reg [15: 0] dac_dds_phase_8_0 = 'd0; + reg [15: 0] dac_dds_phase_8_1 = 'd0; + reg [15: 0] dac_dds_phase_9_0 = 'd0; + reg [15: 0] dac_dds_phase_9_1 = 'd0; + reg [15: 0] dac_dds_phase_10_0 = 'd0; + reg [15: 0] dac_dds_phase_10_1 = 'd0; + reg [15: 0] dac_dds_phase_11_0 = 'd0; + reg [15: 0] dac_dds_phase_11_1 = 'd0; + reg [15: 0] dac_dds_phase_12_0 = 'd0; + reg [15: 0] dac_dds_phase_12_1 = 'd0; + reg [15: 0] dac_dds_phase_13_0 = 'd0; + reg [15: 0] dac_dds_phase_13_1 = 'd0; + reg [15: 0] dac_dds_phase_14_0 = 'd0; + reg [15: 0] dac_dds_phase_14_1 = 'd0; + reg [15: 0] dac_dds_phase_15_0 = 'd0; + reg [15: 0] dac_dds_phase_15_1 = 'd0; + reg [15: 0] dac_dds_incr_0 = 'd0; + reg [15: 0] dac_dds_incr_1 = 'd0; + reg [255:0] dac_dds_data = 'd0; + reg [255:0] dac_pn7_data = 'd0; + reg [255:0] dac_pn15_data = 'd0; + + // internal signals + + wire [15: 0] dac_dds_data_0_s; + wire [15: 0] dac_dds_data_1_s; + wire [15: 0] dac_dds_data_2_s; + wire [15: 0] dac_dds_data_3_s; + wire [15: 0] dac_dds_data_4_s; + wire [15: 0] dac_dds_data_5_s; + wire [15: 0] dac_dds_data_6_s; + wire [15: 0] dac_dds_data_7_s; + wire [15: 0] dac_dds_data_8_s; + wire [15: 0] dac_dds_data_9_s; + wire [15: 0] dac_dds_data_10_s; + wire [15: 0] dac_dds_data_11_s; + wire [15: 0] dac_dds_data_12_s; + wire [15: 0] dac_dds_data_13_s; + wire [15: 0] dac_dds_data_14_s; + wire [15: 0] dac_dds_data_15_s; + wire [15: 0] dac_dds_scale_1_s; + wire [15: 0] dac_dds_init_1_s; + wire [15: 0] dac_dds_incr_1_s; + wire [15: 0] dac_dds_scale_2_s; + wire [15: 0] dac_dds_init_2_s; + wire [15: 0] dac_dds_incr_2_s; + wire [15: 0] dac_pat_data_1_s; + wire [15: 0] dac_pat_data_2_s; + wire [ 3: 0] dac_data_sel_s; + wire [255:0] dac_pn7_data_i_s; + wire [255:0] dac_pn15_data_i_s; + wire [255:0] dac_pn7_data_s; + wire [255:0] dac_pn15_data_s; + + + // PN7 function + + function [255:0] pn7; + input [7:0] din; + reg [255:0] dout; + reg [15:0] dout16; + reg [7:0] din_reg; + integer i; + integer j; + begin + din_reg = din; + for ( j=0 ; j<16 ; j=j+1)begin + for ( i=0 ; i<16 ; i= i+1)begin + din_reg = {din_reg,din_reg[6]^din_reg[5]}; + dout16[15-i] = din_reg[0]; + end + dout = {dout16,dout[255:16]}; + end + pn7 = dout; + end + endfunction + + // PN15 function + + function [255:0] pn15; + input [15:0] din; + reg [255:0] dout; + reg [15:0] dout16; + reg [15:0] din_reg; + integer i; + integer j; + begin + din_reg = din; + for (j=0 ; j<16 ; j=j+1)begin + for (i=0 ; i<16 ; i= i+1)begin + din_reg = {din_reg,din_reg[14]^din_reg[13]}; + dout16[15-i] = din_reg[0]; + end + dout = {dout16,dout[255:16]}; + end + pn15 = dout; + end + endfunction + + assign dac_pn7_data_i_s = ~dac_pn7_data; + assign dac_pn15_data_i_s = ~dac_pn15_data; + + assign dac_pn7_data_s = dac_pn7_data; + assign dac_pn15_data_s = dac_pn15_data; + + + // dac data select + + always @(posedge dac_clk) begin + dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0; + case (dac_data_sel_s) + 4'h7: dac_data <= dac_pn15_data_s; + 4'h6: dac_data <= dac_pn7_data_s; + 4'h5: dac_data <= dac_pn15_data_i_s; + 4'h4: dac_data <= dac_pn7_data_i_s; + 4'h3: dac_data <= 256'd0; + 4'h2: dac_data <= dma_data; + 4'h1: dac_data <= { dac_pat_data_2_s, dac_pat_data_1_s, + dac_pat_data_2_s, dac_pat_data_1_s, + dac_pat_data_2_s, dac_pat_data_1_s, + dac_pat_data_2_s, dac_pat_data_1_s, + dac_pat_data_2_s, dac_pat_data_1_s, + dac_pat_data_2_s, dac_pat_data_1_s, + dac_pat_data_2_s, dac_pat_data_1_s, + dac_pat_data_2_s, dac_pat_data_1_s}; + default: dac_data <= dac_dds_data; + endcase + end + + // pn registers + + always @(posedge dac_clk) begin + if (dac_data_sync == 1'b1) begin + dac_pn7_data <= {255{1'd1}}; + dac_pn15_data <= {255{1'd1}}; + end else begin + dac_pn7_data <= pn7(dac_pn7_data[247:240]); + dac_pn15_data <= pn15(dac_pn15_data[255:240]); + end + end + + // dds + + always @(posedge dac_clk) begin + if (dac_data_sync == 1'b1) begin + dac_dds_phase_0_0 <= dac_dds_init_1_s; + dac_dds_phase_0_1 <= dac_dds_init_2_s; + dac_dds_phase_1_0 <= dac_dds_phase_0_0 + dac_dds_incr_1_s; + dac_dds_phase_1_1 <= dac_dds_phase_0_1 + dac_dds_incr_2_s; + dac_dds_phase_2_0 <= dac_dds_phase_1_0 + dac_dds_incr_1_s; + dac_dds_phase_2_1 <= dac_dds_phase_1_1 + dac_dds_incr_2_s; + dac_dds_phase_3_0 <= dac_dds_phase_2_0 + dac_dds_incr_1_s; + dac_dds_phase_3_1 <= dac_dds_phase_2_1 + dac_dds_incr_2_s; + dac_dds_phase_4_0 <= dac_dds_phase_3_0 + dac_dds_incr_1_s; + dac_dds_phase_4_1 <= dac_dds_phase_3_1 + dac_dds_incr_2_s; + dac_dds_phase_5_0 <= dac_dds_phase_4_0 + dac_dds_incr_1_s; + dac_dds_phase_5_1 <= dac_dds_phase_4_1 + dac_dds_incr_2_s; + dac_dds_phase_6_0 <= dac_dds_phase_5_0 + dac_dds_incr_1_s; + dac_dds_phase_6_1 <= dac_dds_phase_5_1 + dac_dds_incr_2_s; + dac_dds_phase_7_0 <= dac_dds_phase_6_0 + dac_dds_incr_1_s; + dac_dds_phase_7_1 <= dac_dds_phase_6_1 + dac_dds_incr_2_s; + dac_dds_phase_8_0 <= dac_dds_phase_7_0 + dac_dds_incr_1_s; + dac_dds_phase_8_1 <= dac_dds_phase_7_1 + dac_dds_incr_2_s; + dac_dds_phase_9_0 <= dac_dds_phase_8_0 + dac_dds_incr_1_s; + dac_dds_phase_9_1 <= dac_dds_phase_8_1 + dac_dds_incr_2_s; + dac_dds_phase_10_0 <= dac_dds_phase_9_0 + dac_dds_incr_1_s; + dac_dds_phase_10_1 <= dac_dds_phase_9_1 + dac_dds_incr_2_s; + dac_dds_phase_11_0 <= dac_dds_phase_10_0 + dac_dds_incr_1_s; + dac_dds_phase_11_1 <= dac_dds_phase_10_1 + dac_dds_incr_2_s; + dac_dds_phase_12_0 <= dac_dds_phase_11_0 + dac_dds_incr_1_s; + dac_dds_phase_12_1 <= dac_dds_phase_11_1 + dac_dds_incr_2_s; + dac_dds_phase_13_0 <= dac_dds_phase_12_0 + dac_dds_incr_1_s; + dac_dds_phase_13_1 <= dac_dds_phase_12_1 + dac_dds_incr_2_s; + dac_dds_phase_14_0 <= dac_dds_phase_13_0 + dac_dds_incr_1_s; + dac_dds_phase_14_1 <= dac_dds_phase_13_1 + dac_dds_incr_2_s; + dac_dds_phase_15_0 <= dac_dds_phase_14_0 + dac_dds_incr_1_s; + dac_dds_phase_15_1 <= dac_dds_phase_14_1 + dac_dds_incr_2_s; + dac_dds_incr_0 <= {dac_dds_incr_1_s[11:0], 4'd0}; + dac_dds_incr_1 <= {dac_dds_incr_2_s[11:0], 4'd0}; + dac_dds_data <= 256'd0; + end else begin + dac_dds_phase_0_0 <= dac_dds_phase_0_0 + dac_dds_incr_0; + dac_dds_phase_0_1 <= dac_dds_phase_0_1 + dac_dds_incr_1; + dac_dds_phase_1_0 <= dac_dds_phase_1_0 + dac_dds_incr_0; + dac_dds_phase_1_1 <= dac_dds_phase_1_1 + dac_dds_incr_1; + dac_dds_phase_2_0 <= dac_dds_phase_2_0 + dac_dds_incr_0; + dac_dds_phase_2_1 <= dac_dds_phase_2_1 + dac_dds_incr_1; + dac_dds_phase_3_0 <= dac_dds_phase_3_0 + dac_dds_incr_0; + dac_dds_phase_3_1 <= dac_dds_phase_3_1 + dac_dds_incr_1; + dac_dds_phase_4_0 <= dac_dds_phase_4_0 + dac_dds_incr_1_s; + dac_dds_phase_4_1 <= dac_dds_phase_4_1 + dac_dds_incr_2_s; + dac_dds_phase_5_0 <= dac_dds_phase_5_0 + dac_dds_incr_1_s; + dac_dds_phase_5_1 <= dac_dds_phase_5_1 + dac_dds_incr_2_s; + dac_dds_phase_6_0 <= dac_dds_phase_6_0 + dac_dds_incr_1_s; + dac_dds_phase_6_1 <= dac_dds_phase_6_1 + dac_dds_incr_2_s; + dac_dds_phase_7_0 <= dac_dds_phase_7_0 + dac_dds_incr_1_s; + dac_dds_phase_7_1 <= dac_dds_phase_7_1 + dac_dds_incr_2_s; + dac_dds_phase_8_0 <= dac_dds_phase_8_0 + dac_dds_incr_1_s; + dac_dds_phase_8_1 <= dac_dds_phase_8_1 + dac_dds_incr_2_s; + dac_dds_phase_9_0 <= dac_dds_phase_9_0 + dac_dds_incr_1_s; + dac_dds_phase_9_1 <= dac_dds_phase_9_1 + dac_dds_incr_2_s; + dac_dds_phase_10_0 <= dac_dds_phase_10_0 + dac_dds_incr_1_s; + dac_dds_phase_10_1 <= dac_dds_phase_10_1 + dac_dds_incr_2_s; + dac_dds_phase_11_0 <= dac_dds_phase_11_0 + dac_dds_incr_1_s; + dac_dds_phase_11_1 <= dac_dds_phase_11_1 + dac_dds_incr_2_s; + dac_dds_phase_12_0 <= dac_dds_phase_12_0 + dac_dds_incr_1_s; + dac_dds_phase_12_1 <= dac_dds_phase_12_1 + dac_dds_incr_2_s; + dac_dds_phase_13_0 <= dac_dds_phase_13_0 + dac_dds_incr_1_s; + dac_dds_phase_13_1 <= dac_dds_phase_13_1 + dac_dds_incr_2_s; + dac_dds_phase_14_0 <= dac_dds_phase_14_0 + dac_dds_incr_1_s; + dac_dds_phase_14_1 <= dac_dds_phase_14_1 + dac_dds_incr_2_s; + dac_dds_phase_15_0 <= dac_dds_phase_15_0 + dac_dds_incr_1_s; + dac_dds_phase_15_1 <= dac_dds_phase_15_1 + dac_dds_incr_2_s; + dac_dds_incr_0 <= dac_dds_incr_0; + dac_dds_incr_1 <= dac_dds_incr_1; + dac_dds_data <= { dac_dds_data_15_s, dac_dds_data_14_s, + dac_dds_data_13_s, dac_dds_data_12_s, + dac_dds_data_11_s, dac_dds_data_10_s, + dac_dds_data_9_s, dac_dds_data_8_s, + dac_dds_data_7_s, dac_dds_data_6_s, + dac_dds_data_5_s, dac_dds_data_4_s, + dac_dds_data_3_s, dac_dds_data_2_s, + dac_dds_data_1_s, dac_dds_data_0_s}; + end + end + + generate + if (DATAPATH_DISABLE == 1) begin + assign dac_dds_data_0_s = 16'd0; + end else begin + ad_dds i_dds_0 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_0_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_0_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_0_s)); + end + endgenerate + + generate + if (DATAPATH_DISABLE == 1) begin + assign dac_dds_data_1_s = 16'd0; + end else begin + ad_dds i_dds_1 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_1_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_1_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_1_s)); + end + endgenerate + + generate + if (DATAPATH_DISABLE == 1) begin + assign dac_dds_data_2_s = 16'd0; + end else begin + ad_dds i_dds_2 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_2_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_2_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_2_s)); + end + endgenerate + + generate + if (DATAPATH_DISABLE == 1) begin + assign dac_dds_data_3_s = 16'd0; + end else begin + ad_dds i_dds_3 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_3_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_3_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_3_s)); + end + endgenerate + + generate + if (DATAPATH_DISABLE == 1) begin + assign dac_dds_data_4_s = 16'd0; + end else begin + ad_dds i_dds_4 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_4_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_4_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_4_s)); + end + endgenerate + + generate + if (DATAPATH_DISABLE == 1) begin + assign dac_dds_data_5_s = 16'd0; + end else begin + ad_dds i_dds_5 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_5_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_5_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_5_s)); + end + endgenerate + + generate + if (DATAPATH_DISABLE == 1) begin + assign dac_dds_data_6_s = 16'd0; + end else begin + ad_dds i_dds_6 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_6_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_6_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_6_s)); + end + endgenerate + + generate + if (DATAPATH_DISABLE == 1) begin + assign dac_dds_data_7_s = 16'd0; + end else begin + ad_dds i_dds_7 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_7_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_7_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_7_s)); + end + endgenerate + + generate + if (DATAPATH_DISABLE == 1) begin + assign dac_dds_data_8_s = 16'd0; + end else begin + ad_dds i_dds_8 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_8_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_8_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_8_s)); + end + endgenerate + + generate + if (DATAPATH_DISABLE == 1) begin + assign dac_dds_data_9_s = 16'd0; + end else begin + ad_dds i_dds_9 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_9_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_9_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_9_s)); + end + endgenerate + + generate + if (DATAPATH_DISABLE == 1) begin + assign dac_dds_data_10_s = 16'd0; + end else begin + ad_dds i_dds_10 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_10_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_10_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_10_s)); + end + endgenerate + + generate + if (DATAPATH_DISABLE == 1) begin + assign dac_dds_data_11_s = 16'd0; + end else begin + ad_dds i_dds_11 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_11_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_11_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_11_s)); + end + endgenerate + + generate + if (DATAPATH_DISABLE == 1) begin + assign dac_dds_data_12_s = 16'd0; + end else begin + ad_dds i_dds_12 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_12_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_12_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_12_s)); + end + endgenerate + + generate + if (DATAPATH_DISABLE == 1) begin + assign dac_dds_data_13_s = 16'd0; + end else begin + ad_dds i_dds_13 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_13_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_13_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_13_s)); + end + endgenerate + + generate + if (DATAPATH_DISABLE == 1) begin + assign dac_dds_data_14_s = 16'd0; + end else begin + ad_dds i_dds_14 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_14_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_14_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_14_s)); + end + endgenerate + + generate + if (DATAPATH_DISABLE == 1) begin + assign dac_dds_data_15_s = 16'd0; + end else begin + ad_dds i_dds_15 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_15_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_15_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_15_s)); + end + endgenerate + + // single channel processor + + up_dac_channel #(.DAC_CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_dds_scale_1 (dac_dds_scale_1_s), + .dac_dds_init_1 (dac_dds_init_1_s), + .dac_dds_incr_1 (dac_dds_incr_1_s), + .dac_dds_scale_2 (dac_dds_scale_2_s), + .dac_dds_init_2 (dac_dds_init_2_s), + .dac_dds_incr_2 (dac_dds_incr_2_s), + .dac_pat_data_1 (dac_pat_data_1_s), + .dac_pat_data_2 (dac_pat_data_2_s), + .dac_data_sel (dac_data_sel_s), + .dac_iqcor_enb (), + .dac_iqcor_coeff_1 (), + .dac_iqcor_coeff_2 (), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_interpolation_m (), + .up_usr_interpolation_n (), + .dac_usr_datatype_be (1'b0), + .dac_usr_datatype_signed (1'b1), + .dac_usr_datatype_shift (8'd0), + .dac_usr_datatype_total_bits (8'd16), + .dac_usr_datatype_bits (8'd16), + .dac_usr_interpolation_m (16'd1), + .dac_usr_interpolation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + diff --git a/library/axi_ad9162/axi_ad9162_core.v b/library/axi_ad9162/axi_ad9162_core.v new file mode 100644 index 000000000..87f9620d2 --- /dev/null +++ b/library/axi_ad9162/axi_ad9162_core.v @@ -0,0 +1,234 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns / 1ps + +module axi_ad9162_core( + + // dac interface + + dac_clk, + dac_rst, + dac_data_0_0, + dac_data_0_1, + dac_data_0_2, + dac_data_0_3, + dac_data_0_4, + dac_data_0_5, + dac_data_0_6, + dac_data_0_7, + dac_data_0_8, + dac_data_0_9, + dac_data_0_10, + dac_data_0_11, + dac_data_0_12, + dac_data_0_13, + dac_data_0_14, + dac_data_0_15, + + // dma interface + + dac_valid_0, + dac_enable_0, + dac_ddata_0, + dac_dovf, + dac_dunf, + + // processor interface + + up_rstn, + up_clk, + up_wreq, + up_waddr, + up_wdata, + up_wack, + up_rreq, + up_raddr, + up_rdata, + up_rack); + + // parameters + + parameter ID = 0; + parameter DATAPATH_DISABLE = 0; + + // dac interface + + input dac_clk; + output dac_rst; + output [ 15:0] dac_data_0_0; + output [ 15:0] dac_data_0_1; + output [ 15:0] dac_data_0_2; + output [ 15:0] dac_data_0_3; + output [ 15:0] dac_data_0_4; + output [ 15:0] dac_data_0_5; + output [ 15:0] dac_data_0_6; + output [ 15:0] dac_data_0_7; + output [ 15:0] dac_data_0_8; + output [ 15:0] dac_data_0_9; + output [ 15:0] dac_data_0_10; + output [ 15:0] dac_data_0_11; + output [ 15:0] dac_data_0_12; + output [ 15:0] dac_data_0_13; + output [ 15:0] dac_data_0_14; + output [ 15:0] dac_data_0_15; + + // dma interface + + output dac_valid_0; + output dac_enable_0; + input [255:0] dac_ddata_0; + input dac_dovf; + input dac_dunf; + + + // processor interface + + input up_rstn; + input up_clk; + input up_wreq; + input [ 13:0] up_waddr; + input [ 31:0] up_wdata; + output up_wack; + input up_rreq; + input [ 13:0] up_raddr; + output [ 31:0] up_rdata; + output up_rack; + + // internal registers + + reg [ 31:0] up_rdata = 'd0; + reg up_rack = 'd0; + reg up_wack = 'd0; + + // internal signals + + wire dac_sync_s; + wire dac_datafmt_s; + wire [ 31:0] up_rdata_0_s; + wire up_rack_0_s; + wire up_wack_0_s; + wire [ 31:0] up_rdata_s; + wire up_rack_s; + wire up_wack_s; + + // dac valid + + assign dac_valid_0 = 1'b1; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_rdata <= up_rdata_s | up_rdata_0_s; + up_rack <= up_rack_s | up_rack_0_s; + up_wack <= up_wack_s | up_wack_0_s; + end + end + + // dac channel + + axi_ad9162_channel #(.CHANNEL_ID(0), .DATAPATH_DISABLE(DATAPATH_DISABLE)) i_channel_0 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_enable (dac_enable_0), + .dac_data ({dac_data_0_15, dac_data_0_14, dac_data_0_13, dac_data_0_12, + dac_data_0_11, dac_data_0_10, dac_data_0_9, dac_data_0_8, + dac_data_0_7, dac_data_0_6, dac_data_0_5, dac_data_0_4, + dac_data_0_3, dac_data_0_2, dac_data_0_1, dac_data_0_0}), + .dma_data (dac_ddata_0), + .dac_data_sync (dac_sync_s), + .dac_dds_format (dac_datafmt_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_0_s), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_0_s), + .up_rack (up_rack_0_s)); + + + // dac common processor interface + + up_dac_common #(.ID(ID)) i_up_dac_common ( + .mmcm_rst (), + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_sync (dac_sync_s), + .dac_frame (), + .dac_par_type (), + .dac_par_enb (), + .dac_r1_mode (), + .dac_datafmt (dac_datafmt_s), + .dac_datarate (), + .dac_status (1'b1), + .dac_status_ovf (dac_dovf), + .dac_status_unf (dac_dunf), + .dac_clk_ratio (32'd16), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (16'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .up_usr_chanmax (), + .dac_usr_chanmax (8'd0), + .up_dac_gpio_in (32'd0), + .up_dac_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + +endmodule + diff --git a/library/axi_ad9162/axi_ad9162_if.v b/library/axi_ad9162/axi_ad9162_if.v new file mode 100644 index 000000000..9727a82f2 --- /dev/null +++ b/library/axi_ad9162/axi_ad9162_if.v @@ -0,0 +1,145 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns / 1ps + +module axi_ad9162_if( + + // jesd interface + // tx_clk is (line-rate/40) + + tx_clk, + tx_data, + + // dac interface + + dac_clk, + dac_rst, + dac_data_0_0, + dac_data_0_1, + dac_data_0_2, + dac_data_0_3, + dac_data_0_4, + dac_data_0_5, + dac_data_0_6, + dac_data_0_7, + dac_data_0_8, + dac_data_0_9, + dac_data_0_10, + dac_data_0_11, + dac_data_0_12, + dac_data_0_13, + dac_data_0_14, + dac_data_0_15); + + // jesd interface + // tx_clk is (line-rate/40) + + input tx_clk; + output [255:0] tx_data; + + // dac interface + + output dac_clk; + input dac_rst; + input [15:0] dac_data_0_0; + input [15:0] dac_data_0_1; + input [15:0] dac_data_0_2; + input [15:0] dac_data_0_3; + input [15:0] dac_data_0_4; + input [15:0] dac_data_0_5; + input [15:0] dac_data_0_6; + input [15:0] dac_data_0_7; + input [15:0] dac_data_0_8; + input [15:0] dac_data_0_9; + input [15:0] dac_data_0_10; + input [15:0] dac_data_0_11; + input [15:0] dac_data_0_12; + input [15:0] dac_data_0_13; + input [15:0] dac_data_0_14; + input [15:0] dac_data_0_15; + + // internal registers + + reg [255:0] tx_data = 'd0; + + // reorder data for the jesd links + + assign dac_clk = tx_clk; + + always @(posedge dac_clk) begin + if (dac_rst == 1'b1) begin + tx_data <= 256'd0; + end else begin + tx_data[255:248] <= dac_data_0_15 [ 7: 0]; + tx_data[247:240] <= dac_data_0_11 [ 7: 0]; + tx_data[239:232] <= dac_data_0_7 [ 7: 0]; + tx_data[231:224] <= dac_data_0_3 [ 7: 0]; + tx_data[223:216] <= dac_data_0_15 [15: 8]; + tx_data[215:208] <= dac_data_0_11 [15: 8]; + tx_data[207:200] <= dac_data_0_7 [15: 8]; + tx_data[199:192] <= dac_data_0_3 [15: 8]; + tx_data[191:184] <= dac_data_0_14 [ 7: 0]; + tx_data[183:176] <= dac_data_0_10 [ 7: 0]; + tx_data[175:168] <= dac_data_0_6 [ 7: 0]; + tx_data[167:160] <= dac_data_0_2 [ 7: 0]; + tx_data[159:152] <= dac_data_0_14 [15: 8]; + tx_data[151:144] <= dac_data_0_10 [15: 8]; + tx_data[143:136] <= dac_data_0_6 [15: 8]; + tx_data[135:128] <= dac_data_0_2 [15: 8]; + tx_data[127:120] <= dac_data_0_13 [ 7: 0]; + tx_data[119:112] <= dac_data_0_9 [ 7: 0]; + tx_data[111:104] <= dac_data_0_5 [ 7: 0]; + tx_data[103: 96] <= dac_data_0_1 [ 7: 0]; + tx_data[ 95: 88] <= dac_data_0_13 [15: 8]; + tx_data[ 87: 80] <= dac_data_0_9 [15: 8]; + tx_data[ 79: 72] <= dac_data_0_5 [15: 8]; + tx_data[ 71: 64] <= dac_data_0_1 [15: 8]; + tx_data[ 63: 56] <= dac_data_0_12 [ 7: 0]; + tx_data[ 55: 48] <= dac_data_0_8 [ 7: 0]; + tx_data[ 47: 40] <= dac_data_0_4 [ 7: 0]; + tx_data[ 39: 32] <= dac_data_0_0 [ 7: 0]; + tx_data[ 31: 24] <= dac_data_0_12 [15: 8]; + tx_data[ 23: 16] <= dac_data_0_8 [15: 8]; + tx_data[ 15: 8] <= dac_data_0_4 [15: 8]; + tx_data[ 7: 0] <= dac_data_0_0 [15: 8]; + end + end + +endmodule diff --git a/library/axi_ad9162/axi_ad9162_ip.tcl b/library/axi_ad9162/axi_ad9162_ip.tcl new file mode 100644 index 000000000..7c30478c1 --- /dev/null +++ b/library/axi_ad9162/axi_ad9162_ip.tcl @@ -0,0 +1,35 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_ad9162 +adi_ip_files axi_ad9162 [list \ + "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_mul.v" \ + "$ad_hdl_dir/library/common/ad_dds_sine.v" \ + "$ad_hdl_dir/library/common/ad_dds_1.v" \ + "$ad_hdl_dir/library/common/ad_dds.v" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_dac_common.v" \ + "$ad_hdl_dir/library/common/up_dac_channel.v" \ + "axi_ad9162_channel.v" \ + "axi_ad9162_core.v" \ + "axi_ad9162_if.v" \ + "axi_ad9162.v" ] + +adi_ip_properties axi_ad9162 + +adi_ip_constraints axi_ad9162 [list \ + "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ] + +set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] + +ipx::save_core [ipx::current_core] + +