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axi_spi_engine: Fix IRQ generation

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Istvan Csomortani 2021-02-12 13:53:07 +00:00 committed by István Csomortáni
parent 22ce3ef9ce
commit d91b50071f
1 changed files with 4 additions and 4 deletions
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8
library/spi_engine/axi_spi_engine/axi_spi_engine.v
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@ -251,9 +251,9 @@ module axi_spi_engine #(
endgenerate
// IRQ handling
reg [3:0] up_irq_mask = 'h0;
wire [3:0] up_irq_source;
wire [3:0] up_irq_pending;
reg [4:0] up_irq_mask = 5'h0;
wire [4:0] up_irq_source;
wire [4:0] up_irq_pending;
assign up_irq_source = {
offload_sync_id_pending,
@ -372,7 +372,7 @@ module axi_spi_engine #(
if (offload_sync_fifo_valid == 1'b1) begin
offload_sync_id <= offload_sync_fifo_data;
offload_sync_id_pending <= 1'b1;
end else if (up_wreq_s == 1'b1 && up_waddr_s == 8'h21 && up_wdata_s[3] == 1'b1) begin
end else if (up_wreq_s == 1'b1 && up_waddr_s == 8'h21 && up_wdata_s[4] == 1'b1) begin
offload_sync_id_pending <= 1'b0;
end
end