fmcomms2: c5soc: Set dac_util_unpack number of channels to 4
We only do have 4 channels in this design. Reducing the number of supported channels for the dac_util_unpack core to 4 from 8 lowers the DMA alignment requirement from 128bit to 64bit. We need this since applications only expect a DMA alignment requirement of 64bit. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
parent
ecc498313c
commit
d8651cdd2e
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@ -951,7 +951,7 @@
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<module kind="axi_dmac" version="1.0" enabled="1" name="axi_dmac_dac">
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<parameter name="PCORE_ID" value="0" />
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<parameter name="C_DMA_DATA_WIDTH_SRC" value="64" />
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<parameter name="C_DMA_DATA_WIDTH_DEST" value="128" />
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<parameter name="C_DMA_DATA_WIDTH_DEST" value="64" />
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<parameter name="C_DMA_LENGTH_WIDTH" value="24" />
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<parameter name="C_2D_TRANSFER" value="0" />
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<parameter name="C_CLKS_ASYNC_REQ_SRC" value="1" />
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@ -1277,6 +1277,8 @@
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version="1.0"
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enabled="1"
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name="util_dac_unpack">
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<parameter name="CHANNELS" value="4" />
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<parameter name="DATA_WIDTH" value="16" />
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<parameter name="AUTO_DATA_CLOCK_CLOCK_RATE" value="0" />
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</module>
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<connection
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@ -283,7 +283,7 @@ module system_top (
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wire [ 15:0] dac_data_q0;
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wire [ 15:0] dac_data_i1;
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wire [ 15:0] dac_data_q1;
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wire [127:0] dac_ddata;
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wire [ 63:0] dac_ddata;
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wire dac_dunf;
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wire dac_rd_en;
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wire dac_fifo_valid;
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@ -490,36 +490,24 @@ module system_top (
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.adc_pack_channels_data_chan_data_3 (adc_chan_q1),
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.adc_pack_channels_data_dvalid (adc_dwr),
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.adc_pack_channels_data_dsync (adc_dsync),
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.adc_pack_channels_data_ddata (adc_ddata),
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.util_dac_unpack_data_clock_clk (clk),
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.util_dac_unpack_channels_data_dac_enable_00 (dac_enable_i0),
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.util_dac_unpack_channels_data_dac_valid_00 (dac_valid_i0),
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.util_dac_unpack_channels_data_dac_data_00 (dac_data_i0),
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.util_dac_unpack_channels_data_dac_enable_01 (dac_enable_q0),
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.util_dac_unpack_channels_data_dac_valid_01 (dac_valid_q0),
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.util_dac_unpack_channels_data_dac_data_01 (dac_data_q0),
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.util_dac_unpack_channels_data_dac_enable_02 (dac_enable_i1),
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.util_dac_unpack_channels_data_dac_valid_02 (dac_valid_i1),
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.util_dac_unpack_channels_data_dac_data_02 (dac_data_i1),
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.util_dac_unpack_channels_data_dac_enable_03 (dac_enable_q1),
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.util_dac_unpack_channels_data_dac_valid_03 (dac_valid_q1),
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.util_dac_unpack_channels_data_dac_data_03 (dac_data_q1),
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.util_dac_unpack_channels_data_dac_enable_04 (1'b0),
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.util_dac_unpack_channels_data_dac_valid_04 (1'b0),
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.util_dac_unpack_channels_data_dac_data_04 (),
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.util_dac_unpack_channels_data_dac_enable_05 (1'b0),
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.util_dac_unpack_channels_data_dac_valid_05 (1'b0),
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.util_dac_unpack_channels_data_dac_data_05 (),
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.util_dac_unpack_channels_data_dac_enable_06 (1'b0),
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.util_dac_unpack_channels_data_dac_valid_06 (1'b0),
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.util_dac_unpack_channels_data_dac_data_06 (),
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.util_dac_unpack_channels_data_dac_enable_07 (1'b0),
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.util_dac_unpack_channels_data_dac_valid_07 (1'b0),
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.util_dac_unpack_channels_data_dac_data_07 (),
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.util_dac_unpack_channels_data_fifo_valid (dac_fifo_valid),
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.util_dac_unpack_channels_data_dma_rd (dac_rd_en),
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.util_dac_unpack_channels_data_dma_data (dac_ddata)
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);
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.adc_pack_channels_data_ddata (adc_ddata),
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.util_dac_unpack_data_clock_clk (clk),
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.util_dac_unpack_channels_data_dac_enable_00 (dac_enable_i0),
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.util_dac_unpack_channels_data_dac_valid_00 (dac_valid_i0),
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.util_dac_unpack_channels_data_dac_data_00 (dac_data_i0),
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.util_dac_unpack_channels_data_dac_enable_01 (dac_enable_q0),
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.util_dac_unpack_channels_data_dac_valid_01 (dac_valid_q0),
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.util_dac_unpack_channels_data_dac_data_01 (dac_data_q0),
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.util_dac_unpack_channels_data_dac_enable_02 (dac_enable_i1),
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.util_dac_unpack_channels_data_dac_valid_02 (dac_valid_i1),
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.util_dac_unpack_channels_data_dac_data_02 (dac_data_i1),
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.util_dac_unpack_channels_data_dac_enable_03 (dac_enable_q1),
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.util_dac_unpack_channels_data_dac_valid_03 (dac_valid_q1),
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.util_dac_unpack_channels_data_dac_data_03 (dac_data_q1),
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.util_dac_unpack_channels_data_fifo_valid (dac_fifo_valid),
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.util_dac_unpack_channels_data_dma_rd (dac_rd_en),
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.util_dac_unpack_channels_data_dma_data (dac_ddata)
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);
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endmodule
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