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daq2/kcu105: lane assignment fixes

main
Rejeesh Kutty 2014-12-11 11:19:38 -05:00
parent 04c10abc2f
commit d82952b22a
1 changed files with 51 additions and 46 deletions
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23
projects/daq2/kcu105/system_constr.xdc
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@ -13,9 +13,8 @@ set_property -dict {PACKAGE_PIN D2} [get_ports rx_data_p[3]]
set_property -dict {PACKAGE_PIN D1} [get_ports rx_data_n[3]] ; ## A03 FMC_HPC_DP1_M2C_N
set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVDS} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P
set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVDS} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N
set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P
set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N
set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P
set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N
set_property -dict {PACKAGE_PIN K6} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P
set_property -dict {PACKAGE_PIN K5} [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N
@ -27,10 +26,10 @@ set_property -dict {PACKAGE_PIN C4} [get_ports tx_data_p[2]]
set_property -dict {PACKAGE_PIN C3} [get_ports tx_data_n[2]] ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[1])
set_property -dict {PACKAGE_PIN D6} [get_ports tx_data_p[3]] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[2])
set_property -dict {PACKAGE_PIN D5} [get_ports tx_data_n[3]] ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[2])
set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P
set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N
set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P
set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sysref_n] ; ## H11 FMC_HPC_LA04_N
set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P
set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N
set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P
set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sysref_n] ; ## H11 FMC_HPC_LA04_N
set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports spi_csn_clk] ; ## D11 FMC_HPC_LA05_P
set_property -dict {PACKAGE_PIN L8 IOSTANDARD LVCMOS18} [get_ports spi_csn_dac] ; ## C14 FMC_HPC_LA10_P
@ -50,8 +49,8 @@ set_property -dict {PACKAGE_PIN E10 IOSTANDARD LVCMOS18} [get_ports dac_irq]
set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P
set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N
set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports trig_p] ; ## H13 FMC_HPC_LA07_P
set_property -dict {PACKAGE_PIN E8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports trig_n] ; ## H14 FMC_HPC_LA07_N
set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_p] ; ## H13 FMC_HPC_LA07_P
set_property -dict {PACKAGE_PIN E8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_n] ; ## H14 FMC_HPC_LA07_N
# clocks
@ -60,4 +59,10 @@ create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p]
create_clock -name tx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_tx_clk]
create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_rx_clk]
# gt pin assignments above are for reference only and are ignored by the tool!
set_property LOC GTHE3_CHANNEL_X0Y19 [get_cells -hierarchical -filter {NAME =~ *axi_daq2_gt/inst/g_lane_1[0].i_gt_channel_1/i_gthe3_channel}]
set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ *axi_daq2_gt/inst/g_lane_1[1].i_gt_channel_1/i_gthe3_channel}]
set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ *axi_daq2_gt/inst/g_lane_1[2].i_gt_channel_1/i_gthe3_channel}]
set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ *axi_daq2_gt/inst/g_lane_1[3].i_gt_channel_1/i_gthe3_channel}]