From d825fffd6272f0a02dfc20442f933f8301efd91f Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Thu, 3 Sep 2020 16:37:20 +0100 Subject: [PATCH] jesd204/jesd204_rx: Reset error counter once all lanes synced If all lanes are synchronized (CGS state machine is in DATA phase) for long enough therefore the link is also synchronized/DATA phase reset the error counter since the accumulated values during INIT/CHECK are irrelevant. These errors are handled by the per-lane CGS state machine. All errors accumulated during INIT/CHECK phase of CGS are relevant only if the link is unable to reach the DATA phase. The link stays in DATA phase unless software resets it, so all errors accumulated during the DATA phase are relevant. --- library/jesd204/jesd204_rx/jesd204_rx.v | 12 ++++++++++-- library/jesd204/jesd204_rx/jesd204_rx_ctrl.v | 7 ++++++- library/jesd204/jesd204_rx/jesd204_rx_lane.v | 4 ++-- 3 files changed, 18 insertions(+), 5 deletions(-) diff --git a/library/jesd204/jesd204_rx/jesd204_rx.v b/library/jesd204/jesd204_rx/jesd204_rx.v index f5912b556..b533197c6 100755 --- a/library/jesd204/jesd204_rx/jesd204_rx.v +++ b/library/jesd204/jesd204_rx/jesd204_rx.v @@ -174,6 +174,9 @@ wire latency_monitor_reset; wire [2*NUM_LANES-1:0] frame_align; wire [NUM_LANES-1:0] ifs_ready; +wire event_data_phase; +wire err_statistics_reset; + reg [NUM_LANES-1:0] frame_align_err_thresh_met = {NUM_LANES{1'b0}}; reg [NUM_LANES-1:0] event_frame_alignment_error_per_lane = {NUM_LANES{1'b0}}; @@ -309,7 +312,9 @@ jesd204_rx_ctrl #( .ifs_reset(ifs_reset), - .status_state(status_ctrl_state) + .status_state(status_ctrl_state), + + .event_data_phase(event_data_phase) ); // Reset core when frame alignment errors occur @@ -337,6 +342,9 @@ end else begin : gen_no_frame_align_err_reset end end +assign err_statistics_reset = ctrl_err_statistics_reset || + event_data_phase; + for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane localparam D_START = i * DATA_PATH_WIDTH*8; @@ -374,7 +382,7 @@ for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane .cfg_octets_per_frame(cfg_octets_per_frame), .cfg_disable_scrambler(cfg_disable_scrambler), - .ctrl_err_statistics_reset(ctrl_err_statistics_reset), + .err_statistics_reset(err_statistics_reset), .ctrl_err_statistics_mask(ctrl_err_statistics_mask[2:0]), .status_err_statistics_cnt(status_err_statistics_cnt[32*i+31:32*i]), diff --git a/library/jesd204/jesd204_rx/jesd204_rx_ctrl.v b/library/jesd204/jesd204_rx/jesd204_rx_ctrl.v index 9ad73ea50..972945364 100644 --- a/library/jesd204/jesd204_rx/jesd204_rx_ctrl.v +++ b/library/jesd204/jesd204_rx/jesd204_rx_ctrl.v @@ -68,7 +68,8 @@ module jesd204_rx_ctrl #( output [NUM_LINKS-1:0] sync, output reg latency_monitor_reset, - output [1:0] status_state + output [1:0] status_state, + output event_data_phase ); localparam STATE_RESET = 0; @@ -172,4 +173,8 @@ always @(posedge clk) begin end end +assign event_data_phase = state == STATE_CGS && + next_state == STATE_SYNCHRONIZED && + good_cnt_limit_reached_s; + endmodule diff --git a/library/jesd204/jesd204_rx/jesd204_rx_lane.v b/library/jesd204/jesd204_rx/jesd204_rx_lane.v index a4c35c6ff..679283e9e 100755 --- a/library/jesd204/jesd204_rx/jesd204_rx_lane.v +++ b/library/jesd204/jesd204_rx/jesd204_rx_lane.v @@ -78,7 +78,7 @@ module jesd204_rx_lane #( output [1:0] ilas_config_addr, output [DATA_PATH_WIDTH*8-1:0] ilas_config_data, - input ctrl_err_statistics_reset, + input err_statistics_reset, input [2:0]ctrl_err_statistics_mask, output reg [31:0] status_err_statistics_cnt, @@ -175,7 +175,7 @@ end endfunction always @(posedge clk) begin - if (reset == 1'b1 || ctrl_err_statistics_reset == 1'b1) begin + if (reset == 1'b1 || err_statistics_reset == 1'b1) begin status_err_statistics_cnt <= 32'h0; end else if (status_err_statistics_cnt[31:5] != 27'h7ffffff) begin status_err_statistics_cnt <= status_err_statistics_cnt + num_set_bits(phy_char_err);