From d77e28e372b7c059d77066a1a342f23218605855 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 18 Dec 2014 10:07:52 +0200 Subject: [PATCH] daq3_zc706: Connect PLDDR rst to external push button --- projects/daq3/zc706/system_bd.tcl | 3 +++ projects/daq3/zc706/system_top.v | 3 +++ 2 files changed, 6 insertions(+) diff --git a/projects/daq3/zc706/system_bd.tcl b/projects/daq3/zc706/system_bd.tcl index 401e1e9d9..53e407d56 100644 --- a/projects/daq3/zc706/system_bd.tcl +++ b/projects/daq3/zc706/system_bd.tcl @@ -4,8 +4,11 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 128 +create_bd_port -dir I -type rst sys_rst +set_property CONFIG.POLARITY {ACTIVE_HIGH} [get_bd_ports sys_rst] create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3 create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk +connect_bd_net -net sys_rst [get_bd_ports sys_rst] [get_bd_pins axi_ad9680_fifo/sys_rst] connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins axi_ad9680_fifo/DDR3] connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins axi_ad9680_fifo/sys_clk] create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_fifo/axi_fifo2s/axi] \ diff --git a/projects/daq3/zc706/system_top.v b/projects/daq3/zc706/system_top.v index 0465aaae7..03262dac8 100644 --- a/projects/daq3/zc706/system_top.v +++ b/projects/daq3/zc706/system_top.v @@ -43,6 +43,7 @@ module system_top ( sys_clk_p, sys_clk_n, + sys_rst, DDR3_addr, DDR3_ba, @@ -136,6 +137,7 @@ module system_top ( input sys_clk_p; input sys_clk_n; + input sys_rst; output [13:0] DDR3_addr; output [ 2:0] DDR3_ba; @@ -539,6 +541,7 @@ module system_top ( .spi_sdo_o (spi_mosi), .sys_clk_clk_n (sys_clk_n), .sys_clk_clk_p (sys_clk_p), + .sys_rst (sys_rst), .tx_data_n (tx_data_n), .tx_data_p (tx_data_p), .tx_ref_clk (tx_ref_clk),