From d72fac4b1e3bf05e5c2fe373567652b7b51bdf40 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 27 Aug 2018 09:14:54 +0200 Subject: [PATCH] Add missing timescale annotations For consistent simulation behavior it is recommended to annotate all source files with a timescale. Add it to those where it is currently missing. Signed-off-by: Lars-Peter Clausen --- .../altera/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap.v | 2 ++ library/altera/jesd204_phy/jesd204_phy_glue.v | 2 ++ library/axi_clkgen/axi_clkgen.v | 2 ++ library/axi_dmac/2d_transfer.v | 2 ++ library/axi_dmac/address_generator.v | 2 ++ library/axi_dmac/axi_dmac.v | 2 ++ library/axi_dmac/axi_dmac_burst_memory.v | 2 ++ library/axi_dmac/axi_dmac_regmap.v | 2 ++ library/axi_dmac/axi_dmac_regmap_request.v | 2 ++ library/axi_dmac/axi_dmac_reset_manager.v | 2 ++ library/axi_dmac/axi_dmac_resize_dest.v | 2 ++ library/axi_dmac/axi_dmac_resize_src.v | 2 ++ library/axi_dmac/axi_dmac_response_manager.v | 2 ++ library/axi_dmac/axi_dmac_transfer.v | 2 ++ library/axi_dmac/axi_register_slice.v | 2 ++ library/axi_dmac/data_mover.v | 2 ++ library/axi_dmac/dest_axi_mm.v | 2 ++ library/axi_dmac/dest_axi_stream.v | 2 ++ library/axi_dmac/dest_fifo_inf.v | 2 ++ library/axi_dmac/request_arb.v | 2 ++ library/axi_dmac/request_generator.v | 2 ++ library/axi_dmac/response_generator.v | 2 ++ library/axi_dmac/response_handler.v | 2 ++ library/axi_dmac/splitter.v | 1 + library/axi_dmac/src_axi_mm.v | 2 ++ library/axi_dmac/src_axi_stream.v | 2 ++ library/axi_dmac/src_fifo_inf.v | 2 ++ library/axi_dmac/tb/axi_read_slave.v | 2 ++ library/axi_dmac/tb/axi_slave.v | 2 ++ library/axi_dmac/tb/axi_write_slave.v | 2 ++ library/axi_dmac/tb/reset_manager_tb.v | 2 ++ library/axi_generic_adc/axi_generic_adc.v | 2 ++ library/axi_hdmi_rx/axi_hdmi_rx.v | 2 ++ library/axi_hdmi_rx/axi_hdmi_rx_core.v | 2 ++ library/axi_hdmi_rx/axi_hdmi_rx_es.v | 2 ++ library/axi_hdmi_rx/axi_hdmi_rx_tpm.v | 2 ++ library/axi_hdmi_tx/axi_hdmi_tx.v | 2 ++ library/axi_hdmi_tx/axi_hdmi_tx_core.v | 2 ++ library/axi_hdmi_tx/axi_hdmi_tx_es.v | 2 ++ library/axi_hdmi_tx/axi_hdmi_tx_vdma.v | 2 ++ library/axi_mc_controller/control_registers.v | 2 ++ library/axi_rd_wr_combiner/axi_rd_wr_combiner.v | 2 ++ library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v | 2 ++ .../cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v | 1 + library/common/ad_csc_1.v | 2 ++ library/common/ad_csc_CrYCb2RGB.v | 2 ++ library/common/ad_csc_RGB2CrYCb.v | 2 ++ library/common/ad_ss_422to444.v | 2 ++ library/common/ad_ss_444to422.v | 2 ++ library/common/up_hdmi_rx.v | 2 ++ library/common/util_axis_upscale.v | 2 ++ library/cordic_demod/cordic_demod.v | 2 ++ .../ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v | 2 +- .../ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v | 2 ++ library/jesd204/axi_jesd204_common/jesd204_up_common.v | 2 ++ library/jesd204/axi_jesd204_common/jesd204_up_sysref.v | 2 ++ library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v | 2 ++ library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v | 2 ++ library/jesd204/axi_jesd204_rx/jesd204_up_rx.v | 2 ++ library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v | 2 ++ library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v | 1 + library/jesd204/axi_jesd204_tx/jesd204_up_tx.v | 2 ++ library/jesd204/jesd204_common/jesd204_eof_generator.v | 2 ++ library/jesd204/jesd204_common/jesd204_lmfc.v | 2 ++ library/jesd204/jesd204_common/jesd204_scrambler.v | 2 ++ library/jesd204/jesd204_common/pipeline_stage.v | 2 ++ library/jesd204/jesd204_rx/align_mux.v | 2 ++ library/jesd204/jesd204_rx/elastic_buffer.v | 2 ++ library/jesd204/jesd204_rx/jesd204_ilas_monitor.v | 2 ++ library/jesd204/jesd204_rx/jesd204_lane_latency_monitor.v | 2 ++ library/jesd204/jesd204_rx/jesd204_rx.v | 2 ++ library/jesd204/jesd204_rx/jesd204_rx_cgs.v | 2 ++ library/jesd204/jesd204_rx/jesd204_rx_ctrl.v | 2 ++ library/jesd204/jesd204_rx/jesd204_rx_lane.v | 2 ++ .../jesd204_rx_static_config/jesd204_rx_static_config.v | 2 ++ library/jesd204/jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v | 2 ++ library/jesd204/jesd204_soft_pcs_rx/jesd204_pattern_align.v | 2 ++ library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v | 2 ++ library/jesd204/jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v | 2 ++ library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v | 2 ++ library/jesd204/jesd204_tx/jesd204_tx.v | 2 ++ library/jesd204/jesd204_tx/jesd204_tx_ctrl.v | 2 ++ library/jesd204/jesd204_tx/jesd204_tx_lane.v | 2 ++ .../jesd204_tx_static_config/jesd204_ilas_cfg_static.v | 2 ++ .../jesd204_tx_static_config/jesd204_tx_static_config.v | 2 ++ library/jesd204/tb/axi_jesd204_rx_regmap_tb.v | 2 ++ library/jesd204/tb/axi_jesd204_tx_regmap_tb.v | 2 ++ library/jesd204/tb/loopback_tb.v | 2 ++ library/jesd204/tb/rx_cgs_tb.v | 2 ++ library/jesd204/tb/rx_ctrl_tb.v | 2 ++ library/jesd204/tb/rx_lane_tb.v | 2 ++ library/jesd204/tb/rx_tb.v | 2 ++ library/jesd204/tb/scrambler_tb.v | 2 ++ library/jesd204/tb/soft_pcs_8b10b_sequence_tb.v | 2 ++ library/jesd204/tb/soft_pcs_8b10b_table_tb.v | 2 ++ library/jesd204/tb/soft_pcs_loopback_tb.v | 2 ++ library/jesd204/tb/soft_pcs_pattern_align_tb.v | 2 ++ library/jesd204/tb/tx_ctrl_phase_tb.v | 2 ++ library/jesd204/tb/tx_tb.v | 6 ++++++ .../spi_engine/spi_engine_execution/spi_engine_execution.v | 2 ++ .../spi_engine_interconnect/spi_engine_interconnect.v | 1 + library/spi_engine/spi_engine_offload/spi_engine_offload.v | 2 ++ library/util_axis_fifo/address_gray.v | 2 ++ library/util_axis_fifo/address_gray_pipelined.v | 2 ++ library/util_axis_fifo/address_sync.v | 2 ++ library/util_axis_fifo/util_axis_fifo.v | 2 ++ library/util_axis_resize/util_axis_resize.v | 2 ++ library/util_cdc/sync_bits.v | 3 +++ library/util_cdc/sync_data.v | 2 ++ library/util_cdc/sync_event.v | 2 ++ library/util_cdc/sync_gray.v | 3 +++ library/util_cic/cic_comb.v | 2 ++ library/util_cic/cic_int.v | 2 ++ library/util_gmii_to_rgmii/mdc_mdio.v | 2 ++ library/util_gmii_to_rgmii/util_gmii_to_rgmii.v | 2 ++ library/util_sigma_delta_spi/util_sigma_delta_spi.v | 2 ++ 116 files changed, 233 insertions(+), 1 deletion(-) diff --git a/library/altera/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap.v b/library/altera/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap.v index 2702671ca..e959ab298 100644 --- a/library/altera/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap.v +++ b/library/altera/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module avl_adxcvr_octet_swap #( parameter NUM_OF_LANES = 1 ) ( diff --git a/library/altera/jesd204_phy/jesd204_phy_glue.v b/library/altera/jesd204_phy/jesd204_phy_glue.v index cef32aa3a..7c3359d84 100644 --- a/library/altera/jesd204_phy/jesd204_phy_glue.v +++ b/library/altera/jesd204_phy/jesd204_phy_glue.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module jesd204_glue #( parameter WIDTH = 20, parameter CONST_WIDTH = 1, diff --git a/library/axi_clkgen/axi_clkgen.v b/library/axi_clkgen/axi_clkgen.v index 3e6ba9b6b..582495e7d 100644 --- a/library/axi_clkgen/axi_clkgen.v +++ b/library/axi_clkgen/axi_clkgen.v @@ -34,6 +34,8 @@ // *************************************************************************** // software programmable clock generator (still needs a reference input!) +`timescale 1ns/100ps + module axi_clkgen #( parameter ID = 0, diff --git a/library/axi_dmac/2d_transfer.v b/library/axi_dmac/2d_transfer.v index 626ddc887..69ac6d0c0 100644 --- a/library/axi_dmac/2d_transfer.v +++ b/library/axi_dmac/2d_transfer.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module dmac_2d_transfer #( parameter DMA_AXI_ADDR_WIDTH = 32, diff --git a/library/axi_dmac/address_generator.v b/library/axi_dmac/address_generator.v index 02ffcc1fb..499667579 100644 --- a/library/axi_dmac/address_generator.v +++ b/library/axi_dmac/address_generator.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module dmac_address_generator #( parameter ID_WIDTH = 3, diff --git a/library/axi_dmac/axi_dmac.v b/library/axi_dmac/axi_dmac.v index b259f67bc..30e3901c8 100644 --- a/library/axi_dmac/axi_dmac.v +++ b/library/axi_dmac/axi_dmac.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module axi_dmac #( parameter ID = 0, diff --git a/library/axi_dmac/axi_dmac_burst_memory.v b/library/axi_dmac/axi_dmac_burst_memory.v index 853fb0784..2addd78f4 100644 --- a/library/axi_dmac/axi_dmac_burst_memory.v +++ b/library/axi_dmac/axi_dmac_burst_memory.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module axi_dmac_burst_memory #( parameter DATA_WIDTH_SRC = 64, parameter DATA_WIDTH_DEST = 64, diff --git a/library/axi_dmac/axi_dmac_regmap.v b/library/axi_dmac/axi_dmac_regmap.v index 0bb12016b..5f8bfafb9 100644 --- a/library/axi_dmac/axi_dmac_regmap.v +++ b/library/axi_dmac/axi_dmac_regmap.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module axi_dmac_regmap #( parameter ID = 0, parameter DISABLE_DEBUG_REGISTERS = 0, diff --git a/library/axi_dmac/axi_dmac_regmap_request.v b/library/axi_dmac/axi_dmac_regmap_request.v index b2d487140..9ff1de2e4 100644 --- a/library/axi_dmac/axi_dmac_regmap_request.v +++ b/library/axi_dmac/axi_dmac_regmap_request.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module axi_dmac_regmap_request #( parameter DISABLE_DEBUG_REGISTERS = 0, parameter BYTES_PER_BEAT_WIDTH_DEST = 1, diff --git a/library/axi_dmac/axi_dmac_reset_manager.v b/library/axi_dmac/axi_dmac_reset_manager.v index 5f75b7349..e889e6e85 100644 --- a/library/axi_dmac/axi_dmac_reset_manager.v +++ b/library/axi_dmac/axi_dmac_reset_manager.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module axi_dmac_reset_manager #( parameter ASYNC_CLK_REQ_SRC = 1, parameter ASYNC_CLK_SRC_DEST = 1, diff --git a/library/axi_dmac/axi_dmac_resize_dest.v b/library/axi_dmac/axi_dmac_resize_dest.v index 1cffc45f5..c57b78976 100644 --- a/library/axi_dmac/axi_dmac_resize_dest.v +++ b/library/axi_dmac/axi_dmac_resize_dest.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module axi_dmac_resize_dest #( parameter DATA_WIDTH_DEST = 64, parameter DATA_WIDTH_MEM = 64 diff --git a/library/axi_dmac/axi_dmac_resize_src.v b/library/axi_dmac/axi_dmac_resize_src.v index 408acb64c..24f696f08 100644 --- a/library/axi_dmac/axi_dmac_resize_src.v +++ b/library/axi_dmac/axi_dmac_resize_src.v @@ -38,6 +38,8 @@ * if necessary. */ +`timescale 1ns/100ps + module axi_dmac_resize_src #( parameter DATA_WIDTH_SRC = 64, parameter DATA_WIDTH_MEM = 64 diff --git a/library/axi_dmac/axi_dmac_response_manager.v b/library/axi_dmac/axi_dmac_response_manager.v index b71b6590a..f55ae9336 100644 --- a/library/axi_dmac/axi_dmac_response_manager.v +++ b/library/axi_dmac/axi_dmac_response_manager.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module axi_dmac_response_manager #( parameter DMA_DATA_WIDTH_SRC = 64, parameter DMA_DATA_WIDTH_DEST = 64, diff --git a/library/axi_dmac/axi_dmac_transfer.v b/library/axi_dmac/axi_dmac_transfer.v index 8b290e4a0..d9afc7513 100644 --- a/library/axi_dmac/axi_dmac_transfer.v +++ b/library/axi_dmac/axi_dmac_transfer.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module axi_dmac_transfer #( parameter DMA_DATA_WIDTH_SRC = 64, parameter DMA_DATA_WIDTH_DEST = 64, diff --git a/library/axi_dmac/axi_register_slice.v b/library/axi_dmac/axi_register_slice.v index 329be2c89..e2eea5007 100644 --- a/library/axi_dmac/axi_register_slice.v +++ b/library/axi_dmac/axi_register_slice.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module axi_register_slice #( parameter DATA_WIDTH = 32, diff --git a/library/axi_dmac/data_mover.v b/library/axi_dmac/data_mover.v index a67a80a39..b6aaf67e4 100644 --- a/library/axi_dmac/data_mover.v +++ b/library/axi_dmac/data_mover.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module dmac_data_mover #( parameter ID_WIDTH = 3, diff --git a/library/axi_dmac/dest_axi_mm.v b/library/axi_dmac/dest_axi_mm.v index a38d0c51f..7b54c4853 100644 --- a/library/axi_dmac/dest_axi_mm.v +++ b/library/axi_dmac/dest_axi_mm.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module dmac_dest_mm_axi #( parameter ID_WIDTH = 3, diff --git a/library/axi_dmac/dest_axi_stream.v b/library/axi_dmac/dest_axi_stream.v index 261c93b53..b377d8e68 100644 --- a/library/axi_dmac/dest_axi_stream.v +++ b/library/axi_dmac/dest_axi_stream.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module dmac_dest_axi_stream #( parameter ID_WIDTH = 3, diff --git a/library/axi_dmac/dest_fifo_inf.v b/library/axi_dmac/dest_fifo_inf.v index 149984ad8..486c7c3c8 100644 --- a/library/axi_dmac/dest_fifo_inf.v +++ b/library/axi_dmac/dest_fifo_inf.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module dmac_dest_fifo_inf #( parameter ID_WIDTH = 3, diff --git a/library/axi_dmac/request_arb.v b/library/axi_dmac/request_arb.v index 9f277d7a3..3ae9cf18f 100644 --- a/library/axi_dmac/request_arb.v +++ b/library/axi_dmac/request_arb.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module dmac_request_arb #( parameter DMA_DATA_WIDTH_SRC = 64, parameter DMA_DATA_WIDTH_DEST = 64, diff --git a/library/axi_dmac/request_generator.v b/library/axi_dmac/request_generator.v index 1e3954dc5..75bd7774a 100644 --- a/library/axi_dmac/request_generator.v +++ b/library/axi_dmac/request_generator.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module dmac_request_generator #( parameter ID_WIDTH = 3, diff --git a/library/axi_dmac/response_generator.v b/library/axi_dmac/response_generator.v index 94b2fd376..4e7e87b72 100644 --- a/library/axi_dmac/response_generator.v +++ b/library/axi_dmac/response_generator.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module dmac_response_generator #( parameter ID_WIDTH = 3)( diff --git a/library/axi_dmac/response_handler.v b/library/axi_dmac/response_handler.v index cb1509d47..9dec16b7d 100644 --- a/library/axi_dmac/response_handler.v +++ b/library/axi_dmac/response_handler.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module dmac_response_handler #( parameter ID_WIDTH = 3)( diff --git a/library/axi_dmac/splitter.v b/library/axi_dmac/splitter.v index 68af398a3..04f1287d3 100644 --- a/library/axi_dmac/splitter.v +++ b/library/axi_dmac/splitter.v @@ -33,6 +33,7 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps module splitter #( diff --git a/library/axi_dmac/src_axi_mm.v b/library/axi_dmac/src_axi_mm.v index 4e1930b03..e813a01d2 100644 --- a/library/axi_dmac/src_axi_mm.v +++ b/library/axi_dmac/src_axi_mm.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module dmac_src_mm_axi #( parameter ID_WIDTH = 3, diff --git a/library/axi_dmac/src_axi_stream.v b/library/axi_dmac/src_axi_stream.v index 33173aab2..e9d59c061 100644 --- a/library/axi_dmac/src_axi_stream.v +++ b/library/axi_dmac/src_axi_stream.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module dmac_src_axi_stream #( parameter ID_WIDTH = 3, diff --git a/library/axi_dmac/src_fifo_inf.v b/library/axi_dmac/src_fifo_inf.v index 70d1b188b..a9e417bb9 100644 --- a/library/axi_dmac/src_fifo_inf.v +++ b/library/axi_dmac/src_fifo_inf.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module dmac_src_fifo_inf #( parameter ID_WIDTH = 3, diff --git a/library/axi_dmac/tb/axi_read_slave.v b/library/axi_dmac/tb/axi_read_slave.v index 214562cb2..281418bc3 100644 --- a/library/axi_dmac/tb/axi_read_slave.v +++ b/library/axi_dmac/tb/axi_read_slave.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module axi_read_slave #( parameter DATA_WIDTH = 32, parameter READ_ACCEPTANCE = 4, diff --git a/library/axi_dmac/tb/axi_slave.v b/library/axi_dmac/tb/axi_slave.v index 5a4e06e61..c60b225a8 100644 --- a/library/axi_dmac/tb/axi_slave.v +++ b/library/axi_dmac/tb/axi_slave.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module axi_slave #( parameter ACCEPTANCE = 3, parameter MIN_LATENCY = 16, diff --git a/library/axi_dmac/tb/axi_write_slave.v b/library/axi_dmac/tb/axi_write_slave.v index f82161ea2..06de2f188 100644 --- a/library/axi_dmac/tb/axi_write_slave.v +++ b/library/axi_dmac/tb/axi_write_slave.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module axi_write_slave #( parameter DATA_WIDTH = 32, parameter WRITE_ACCEPTANCE = 3 diff --git a/library/axi_dmac/tb/reset_manager_tb.v b/library/axi_dmac/tb/reset_manager_tb.v index 9fd656237..e113af59f 100644 --- a/library/axi_dmac/tb/reset_manager_tb.v +++ b/library/axi_dmac/tb/reset_manager_tb.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module dmac_reset_manager_tb; parameter VCD_FILE = {`__FILE__,"cd"}; diff --git a/library/axi_generic_adc/axi_generic_adc.v b/library/axi_generic_adc/axi_generic_adc.v index 90748d8bc..94150a755 100644 --- a/library/axi_generic_adc/axi_generic_adc.v +++ b/library/axi_generic_adc/axi_generic_adc.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module axi_generic_adc ( input adc_clk, output [NUM_OF_CHANNELS-1:0] adc_enable, diff --git a/library/axi_hdmi_rx/axi_hdmi_rx.v b/library/axi_hdmi_rx/axi_hdmi_rx.v index 996a5743c..790d7134e 100644 --- a/library/axi_hdmi_rx/axi_hdmi_rx.v +++ b/library/axi_hdmi_rx/axi_hdmi_rx.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module axi_hdmi_rx #( parameter ID = 0, diff --git a/library/axi_hdmi_rx/axi_hdmi_rx_core.v b/library/axi_hdmi_rx/axi_hdmi_rx_core.v index 89a9827f6..89f88a21f 100644 --- a/library/axi_hdmi_rx/axi_hdmi_rx_core.v +++ b/library/axi_hdmi_rx/axi_hdmi_rx_core.v @@ -34,6 +34,8 @@ // *************************************************************************** // Receive HDMI, hdmi embedded syncs data in, video dma data out. +`timescale 1ns/100ps + module axi_hdmi_rx_core #( parameter IO_INTERFACE = 1) ( diff --git a/library/axi_hdmi_rx/axi_hdmi_rx_es.v b/library/axi_hdmi_rx/axi_hdmi_rx_es.v index 9d5dc90ee..80567752f 100644 --- a/library/axi_hdmi_rx/axi_hdmi_rx_es.v +++ b/library/axi_hdmi_rx/axi_hdmi_rx_es.v @@ -34,6 +34,8 @@ // *************************************************************************** // Receive HDMI, hdmi embedded syncs data in, video dma data out. +`timescale 1ns/100ps + module axi_hdmi_rx_es #( parameter DATA_WIDTH = 32) ( diff --git a/library/axi_hdmi_rx/axi_hdmi_rx_tpm.v b/library/axi_hdmi_rx/axi_hdmi_rx_tpm.v index 32d499bf3..ebf7475c4 100644 --- a/library/axi_hdmi_rx/axi_hdmi_rx_tpm.v +++ b/library/axi_hdmi_rx/axi_hdmi_rx_tpm.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module axi_hdmi_rx_tpm ( input hdmi_clk, input hdmi_sof, diff --git a/library/axi_hdmi_tx/axi_hdmi_tx.v b/library/axi_hdmi_tx/axi_hdmi_tx.v index f6d6c05e6..6eb756996 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module axi_hdmi_tx #( parameter ID = 0, diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_core.v b/library/axi_hdmi_tx/axi_hdmi_tx_core.v index bf4074701..8191cf6b2 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx_core.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx_core.v @@ -34,6 +34,8 @@ // *************************************************************************** // Transmit HDMI, video dma data in, hdmi separate syncs data out. +`timescale 1ns/100ps + module axi_hdmi_tx_core #( parameter CR_CB_N = 0, diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_es.v b/library/axi_hdmi_tx/axi_hdmi_tx_es.v index 17c1c8b0a..feaae2cda 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx_es.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx_es.v @@ -34,6 +34,8 @@ // *************************************************************************** // Transmit HDMI, video dma data in, hdmi separate syncs data out. +`timescale 1ns/100ps + module axi_hdmi_tx_es #( parameter DATA_WIDTH = 32) ( diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_vdma.v b/library/axi_hdmi_tx/axi_hdmi_tx_vdma.v index 22c044728..4db00e13a 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx_vdma.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx_vdma.v @@ -34,6 +34,8 @@ // *************************************************************************** // Transmit HDMI, video dma data in, hdmi separate syncs data out. +`timescale 1ns/100ps + module axi_hdmi_tx_vdma ( // hdmi interface diff --git a/library/axi_mc_controller/control_registers.v b/library/axi_mc_controller/control_registers.v index ecee9bba2..258f7dffe 100644 --- a/library/axi_mc_controller/control_registers.v +++ b/library/axi_mc_controller/control_registers.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module control_registers ( diff --git a/library/axi_rd_wr_combiner/axi_rd_wr_combiner.v b/library/axi_rd_wr_combiner/axi_rd_wr_combiner.v index 653af787a..e9bc23e5f 100644 --- a/library/axi_rd_wr_combiner/axi_rd_wr_combiner.v +++ b/library/axi_rd_wr_combiner/axi_rd_wr_combiner.v @@ -38,6 +38,8 @@ * single read-write AXI interface. Only supports AXI3 at the moment. */ +`timescale 1ns/100ps + module axi_rd_wr_combiner ( input clk, diff --git a/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v b/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v index 274cc1f5c..5e432b9cb 100644 --- a/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v +++ b/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module cn0363_dma_sequencer ( input clk, input resetn, diff --git a/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v b/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v index 21ee2ff39..678002382 100644 --- a/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v +++ b/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v @@ -33,6 +33,7 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps module cn0363_phase_data_sync ( input clk, diff --git a/library/common/ad_csc_1.v b/library/common/ad_csc_1.v index d7fca742d..3cacf023b 100644 --- a/library/common/ad_csc_1.v +++ b/library/common/ad_csc_1.v @@ -34,6 +34,8 @@ // *************************************************************************** // csc = c1*d[23:16] + c2*d[15:8] + c3*d[7:0] + c4; +`timescale 1ns/100ps + module ad_csc_1 #( parameter DELAY_DATA_WIDTH = 16) ( diff --git a/library/common/ad_csc_CrYCb2RGB.v b/library/common/ad_csc_CrYCb2RGB.v index 983181641..12ec8c072 100644 --- a/library/common/ad_csc_CrYCb2RGB.v +++ b/library/common/ad_csc_CrYCb2RGB.v @@ -39,6 +39,8 @@ // G = (-208.120/256)*Cr + (+298.082/256)*Y + (-100.291/256)*Cb + (+135.576); // B = ( 000.000/256)*Cr + (+298.082/256)*Y + (+516.412/256)*Cb + (-276.836); +`timescale 1ns/100ps + module ad_csc_CrYCb2RGB #( parameter DELAY_DATA_WIDTH = 16) ( diff --git a/library/common/ad_csc_RGB2CrYCb.v b/library/common/ad_csc_RGB2CrYCb.v index 284e91ce0..4b7e90eec 100644 --- a/library/common/ad_csc_RGB2CrYCb.v +++ b/library/common/ad_csc_RGB2CrYCb.v @@ -39,6 +39,8 @@ // Y = (+065.738/256)*R + (+129.057/256)*G + (+025.064/256)*B + 16; // Cb = (-037.945/256)*R + (-074.494/256)*G + (+112.439/256)*B + 128; +`timescale 1ns/100ps + module ad_csc_RGB2CrYCb #( parameter DELAY_DATA_WIDTH = 16) ( diff --git a/library/common/ad_ss_422to444.v b/library/common/ad_ss_422to444.v index 12416e6ca..d408d9108 100644 --- a/library/common/ad_ss_422to444.v +++ b/library/common/ad_ss_422to444.v @@ -34,6 +34,8 @@ // *************************************************************************** // Input must be RGB or CrYCb in that order, output is CrY/CbY +`timescale 1ns/100ps + module ad_ss_422to444 #( parameter CR_CB_N = 0, diff --git a/library/common/ad_ss_444to422.v b/library/common/ad_ss_444to422.v index 9c4a228b4..542de95af 100644 --- a/library/common/ad_ss_444to422.v +++ b/library/common/ad_ss_444to422.v @@ -34,6 +34,8 @@ // *************************************************************************** // Input must be RGB or CrYCb in that order, output is CrY/CbY +`timescale 1ns/100ps + module ad_ss_444to422 #( parameter CR_CB_N = 0, diff --git a/library/common/up_hdmi_rx.v b/library/common/up_hdmi_rx.v index 5ced3ff2a..68955588d 100644 --- a/library/common/up_hdmi_rx.v +++ b/library/common/up_hdmi_rx.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module up_hdmi_rx #( parameter ID = 0) ( diff --git a/library/common/util_axis_upscale.v b/library/common/util_axis_upscale.v index c6fa63cf3..575070c84 100644 --- a/library/common/util_axis_upscale.v +++ b/library/common/util_axis_upscale.v @@ -38,6 +38,8 @@ // the data format inside a generic AXI converter core. // + Supports multiple channels. Contains a single register stage. +`timescale 1ns/100ps + module util_axis_upscale # ( parameter NUM_OF_CHANNELS = 4, diff --git a/library/cordic_demod/cordic_demod.v b/library/cordic_demod/cordic_demod.v index b78bf0586..71925aeb8 100644 --- a/library/cordic_demod/cordic_demod.v +++ b/library/cordic_demod/cordic_demod.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module cordic_demod ( input clk, input resetn, diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v index 76ef58298..8e6018147 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v @@ -21,7 +21,7 @@ // *************************************************************************** // *************************************************************************** - +`timescale 1ns/100ps module ad_ip_jesd204_tpl_adc_regmap #( parameter ID = 0, diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v index 9f6b56477..df6a806bb 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v +++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v @@ -21,6 +21,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module ad_ip_jesd204_tpl_dac_regmap #( parameter ID = 0, parameter NUM_CHANNELS = 2, diff --git a/library/jesd204/axi_jesd204_common/jesd204_up_common.v b/library/jesd204/axi_jesd204_common/jesd204_up_common.v index 5c5d571d2..720829d44 100644 --- a/library/jesd204/axi_jesd204_common/jesd204_up_common.v +++ b/library/jesd204/axi_jesd204_common/jesd204_up_common.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module jesd204_up_common # ( parameter PCORE_VERSION = 0, parameter PCORE_MAGIC = 0, diff --git a/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v b/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v index dc2ea2767..f0534ea60 100644 --- a/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v +++ b/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module jesd204_up_sysref ( input up_clk, input up_reset, diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v index 65b67114b..57b337b0d 100644 --- a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v +++ b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module axi_jesd204_rx #( parameter ID = 0, parameter NUM_LANES = 1, diff --git a/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v b/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v index 9abd52761..a2138cf51 100644 --- a/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v +++ b/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module jesd204_up_ilas_mem ( input up_clk, diff --git a/library/jesd204/axi_jesd204_rx/jesd204_up_rx.v b/library/jesd204/axi_jesd204_rx/jesd204_up_rx.v index 1d3371aa0..2d21171d9 100644 --- a/library/jesd204/axi_jesd204_rx/jesd204_up_rx.v +++ b/library/jesd204/axi_jesd204_rx/jesd204_up_rx.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module jesd204_up_rx # ( parameter NUM_LANES = 1 ) ( diff --git a/library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v b/library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v index 418e602d0..1429ae838 100644 --- a/library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v +++ b/library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module jesd204_up_rx_lane ( input up_clk, input up_reset_synchronizer, diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v index a6fec8840..006b62f3b 100644 --- a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v +++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v @@ -42,6 +42,7 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps module axi_jesd204_tx #( parameter ID = 0, diff --git a/library/jesd204/axi_jesd204_tx/jesd204_up_tx.v b/library/jesd204/axi_jesd204_tx/jesd204_up_tx.v index 41e4892b1..36843e86f 100644 --- a/library/jesd204/axi_jesd204_tx/jesd204_up_tx.v +++ b/library/jesd204/axi_jesd204_tx/jesd204_up_tx.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module jesd204_up_tx # ( parameter NUM_LANES = 1, parameter NUM_LINKS = 1 diff --git a/library/jesd204/jesd204_common/jesd204_eof_generator.v b/library/jesd204/jesd204_common/jesd204_eof_generator.v index 57e64b583..73c001cd3 100644 --- a/library/jesd204/jesd204_common/jesd204_eof_generator.v +++ b/library/jesd204/jesd204_common/jesd204_eof_generator.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module jesd204_eof_generator #( parameter DATA_PATH_WIDTH = 4, parameter MAX_OCTETS_PER_FRAME = 256 diff --git a/library/jesd204/jesd204_common/jesd204_lmfc.v b/library/jesd204/jesd204_common/jesd204_lmfc.v index 0ad79bde5..beef1ac6b 100644 --- a/library/jesd204/jesd204_common/jesd204_lmfc.v +++ b/library/jesd204/jesd204_common/jesd204_lmfc.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module jesd204_lmfc ( input clk, input reset, diff --git a/library/jesd204/jesd204_common/jesd204_scrambler.v b/library/jesd204/jesd204_common/jesd204_scrambler.v index 3d264ef5e..1d1096497 100644 --- a/library/jesd204/jesd204_common/jesd204_scrambler.v +++ b/library/jesd204/jesd204_common/jesd204_scrambler.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module jesd204_scrambler #( parameter WIDTH = 32, parameter DESCRAMBLE = 0 diff --git a/library/jesd204/jesd204_common/pipeline_stage.v b/library/jesd204/jesd204_common/pipeline_stage.v index 3a76872b6..b4afc025f 100644 --- a/library/jesd204/jesd204_common/pipeline_stage.v +++ b/library/jesd204/jesd204_common/pipeline_stage.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module pipeline_stage #( parameter REGISTERED = 1, parameter WIDTH = 1 diff --git a/library/jesd204/jesd204_rx/align_mux.v b/library/jesd204/jesd204_rx/align_mux.v index 44aa00364..b44bbf053 100644 --- a/library/jesd204/jesd204_rx/align_mux.v +++ b/library/jesd204/jesd204_rx/align_mux.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module align_mux #( parameter DATA_PATH_WIDTH = 4 ) ( diff --git a/library/jesd204/jesd204_rx/elastic_buffer.v b/library/jesd204/jesd204_rx/elastic_buffer.v index 928b5651c..b060d82b8 100644 --- a/library/jesd204/jesd204_rx/elastic_buffer.v +++ b/library/jesd204/jesd204_rx/elastic_buffer.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module elastic_buffer #( parameter WIDTH = 32, parameter SIZE = 256 diff --git a/library/jesd204/jesd204_rx/jesd204_ilas_monitor.v b/library/jesd204/jesd204_rx/jesd204_ilas_monitor.v index f3db40b14..f0769bda6 100644 --- a/library/jesd204/jesd204_rx/jesd204_ilas_monitor.v +++ b/library/jesd204/jesd204_rx/jesd204_ilas_monitor.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module jesd204_ilas_monitor #( parameter DATA_PATH_WIDTH = 4 ) ( diff --git a/library/jesd204/jesd204_rx/jesd204_lane_latency_monitor.v b/library/jesd204/jesd204_rx/jesd204_lane_latency_monitor.v index 4e46b61f5..3f27f6a95 100644 --- a/library/jesd204/jesd204_rx/jesd204_lane_latency_monitor.v +++ b/library/jesd204/jesd204_rx/jesd204_lane_latency_monitor.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module jesd204_lane_latency_monitor #( parameter NUM_LANES = 1 ) ( diff --git a/library/jesd204/jesd204_rx/jesd204_rx.v b/library/jesd204/jesd204_rx/jesd204_rx.v index 114b99a9e..2e74503f8 100644 --- a/library/jesd204/jesd204_rx/jesd204_rx.v +++ b/library/jesd204/jesd204_rx/jesd204_rx.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module jesd204_rx #( parameter NUM_LANES = 1, parameter NUM_LINKS = 1 diff --git a/library/jesd204/jesd204_rx/jesd204_rx_cgs.v b/library/jesd204/jesd204_rx/jesd204_rx_cgs.v index 8c7def4a5..2eeb036bc 100644 --- a/library/jesd204/jesd204_rx/jesd204_rx_cgs.v +++ b/library/jesd204/jesd204_rx/jesd204_rx_cgs.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module jesd204_rx_cgs #( parameter DATA_PATH_WIDTH = 4 ) ( diff --git a/library/jesd204/jesd204_rx/jesd204_rx_ctrl.v b/library/jesd204/jesd204_rx/jesd204_rx_ctrl.v index 8d5176272..de233112f 100644 --- a/library/jesd204/jesd204_rx/jesd204_rx_ctrl.v +++ b/library/jesd204/jesd204_rx/jesd204_rx_ctrl.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module jesd204_rx_ctrl #( parameter NUM_LANES = 1, parameter NUM_LINKS = 1 diff --git a/library/jesd204/jesd204_rx/jesd204_rx_lane.v b/library/jesd204/jesd204_rx/jesd204_rx_lane.v index d99fc965d..002458277 100644 --- a/library/jesd204/jesd204_rx/jesd204_rx_lane.v +++ b/library/jesd204/jesd204_rx/jesd204_rx_lane.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module jesd204_rx_lane #( parameter DATA_PATH_WIDTH = 4, parameter CHAR_INFO_REGISTERED = 0, diff --git a/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.v b/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.v index 3d8d26b55..e2f4367b1 100644 --- a/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.v +++ b/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module jesd204_rx_static_config #( parameter NUM_LANES = 1, parameter NUM_LINKS = 1, diff --git a/library/jesd204/jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v b/library/jesd204/jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v index 6746946b9..83c7a2428 100644 --- a/library/jesd204/jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v +++ b/library/jesd204/jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module jesd204_8b10b_decoder ( input in_disparity, input [9:0] in_char, diff --git a/library/jesd204/jesd204_soft_pcs_rx/jesd204_pattern_align.v b/library/jesd204/jesd204_soft_pcs_rx/jesd204_pattern_align.v index 05798b8f5..ed009b6b9 100644 --- a/library/jesd204/jesd204_soft_pcs_rx/jesd204_pattern_align.v +++ b/library/jesd204/jesd204_soft_pcs_rx/jesd204_pattern_align.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module jesd204_pattern_align #( parameter DATA_PATH_WIDTH = 4 ) ( diff --git a/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v b/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v index 09b20298a..571a2def1 100644 --- a/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v +++ b/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module jesd204_soft_pcs_rx #( parameter NUM_LANES = 1, parameter DATA_PATH_WIDTH = 4, diff --git a/library/jesd204/jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v b/library/jesd204/jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v index 11826e965..72d578260 100644 --- a/library/jesd204/jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v +++ b/library/jesd204/jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module jesd204_8b10b_encoder ( input in_disparity, input [7:0] in_char, diff --git a/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v b/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v index 4ab36ed36..6cb29ed94 100644 --- a/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v +++ b/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module jesd204_soft_pcs_tx #( parameter NUM_LANES = 1, parameter DATA_PATH_WIDTH = 4, diff --git a/library/jesd204/jesd204_tx/jesd204_tx.v b/library/jesd204/jesd204_tx/jesd204_tx.v index 5dcdc9a08..e3e4081c1 100644 --- a/library/jesd204/jesd204_tx/jesd204_tx.v +++ b/library/jesd204/jesd204_tx/jesd204_tx.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module jesd204_tx #( parameter NUM_LANES = 1, parameter NUM_LINKS = 1 diff --git a/library/jesd204/jesd204_tx/jesd204_tx_ctrl.v b/library/jesd204/jesd204_tx/jesd204_tx_ctrl.v index f561d979e..2ff2d19cb 100644 --- a/library/jesd204/jesd204_tx/jesd204_tx_ctrl.v +++ b/library/jesd204/jesd204_tx/jesd204_tx_ctrl.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module jesd204_tx_ctrl #( parameter NUM_LANES = 1, parameter NUM_LINKS = 1, diff --git a/library/jesd204/jesd204_tx/jesd204_tx_lane.v b/library/jesd204/jesd204_tx/jesd204_tx_lane.v index e26bb9085..240cbba1a 100644 --- a/library/jesd204/jesd204_tx/jesd204_tx_lane.v +++ b/library/jesd204/jesd204_tx/jesd204_tx_lane.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module jesd204_tx_lane #( parameter DATA_PATH_WIDTH = 4 ) ( diff --git a/library/jesd204/jesd204_tx_static_config/jesd204_ilas_cfg_static.v b/library/jesd204/jesd204_tx_static_config/jesd204_ilas_cfg_static.v index fdf1d233a..fe63f0ef4 100644 --- a/library/jesd204/jesd204_tx_static_config/jesd204_ilas_cfg_static.v +++ b/library/jesd204/jesd204_tx_static_config/jesd204_ilas_cfg_static.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module jesd204_ilas_config_static #( parameter DID = 8'h00, parameter BID = 4'h0, diff --git a/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.v b/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.v index 5caf6f92b..9aae38ad9 100644 --- a/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.v +++ b/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module jesd204_tx_static_config #( parameter NUM_LANES = 1, parameter NUM_LINKS = 1, diff --git a/library/jesd204/tb/axi_jesd204_rx_regmap_tb.v b/library/jesd204/tb/axi_jesd204_rx_regmap_tb.v index 4f948fc75..8641b2b1c 100644 --- a/library/jesd204/tb/axi_jesd204_rx_regmap_tb.v +++ b/library/jesd204/tb/axi_jesd204_rx_regmap_tb.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module axi_jesd204_rx_tb; parameter VCD_FILE = "axi_jesd204_rx_regmap_tb.vcd"; parameter NUM_LANES = 2; diff --git a/library/jesd204/tb/axi_jesd204_tx_regmap_tb.v b/library/jesd204/tb/axi_jesd204_tx_regmap_tb.v index 5bc567275..a2f8c86fd 100644 --- a/library/jesd204/tb/axi_jesd204_tx_regmap_tb.v +++ b/library/jesd204/tb/axi_jesd204_tx_regmap_tb.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module axi_jesd204_tx_tb; parameter VCD_FILE = "axi_jesd204_tx_regmap_tb.vcd"; parameter NUM_LANES = 2; diff --git a/library/jesd204/tb/loopback_tb.v b/library/jesd204/tb/loopback_tb.v index bf40e375c..43d6b022a 100644 --- a/library/jesd204/tb/loopback_tb.v +++ b/library/jesd204/tb/loopback_tb.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module loopback_tb; parameter VCD_FILE = "loopback_tb.vcd"; parameter NUM_LANES = 4; diff --git a/library/jesd204/tb/rx_cgs_tb.v b/library/jesd204/tb/rx_cgs_tb.v index 506101323..84aa7c43e 100644 --- a/library/jesd204/tb/rx_cgs_tb.v +++ b/library/jesd204/tb/rx_cgs_tb.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module rx_cgs_tb; parameter VCD_FILE = "rx_cgs_tb.vcd"; diff --git a/library/jesd204/tb/rx_ctrl_tb.v b/library/jesd204/tb/rx_ctrl_tb.v index 9fd132dc7..3261d613c 100644 --- a/library/jesd204/tb/rx_ctrl_tb.v +++ b/library/jesd204/tb/rx_ctrl_tb.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module rx_ctrl_tb; parameter VCD_FILE = "rx_ctrl_tb.vcd"; diff --git a/library/jesd204/tb/rx_lane_tb.v b/library/jesd204/tb/rx_lane_tb.v index 4c2bcc210..fee7f5fe3 100644 --- a/library/jesd204/tb/rx_lane_tb.v +++ b/library/jesd204/tb/rx_lane_tb.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module rx_lane_tb; parameter VCD_FILE = "rx_lane_tb.vcd"; diff --git a/library/jesd204/tb/rx_tb.v b/library/jesd204/tb/rx_tb.v index 22e0e2c57..b10f9f3b8 100644 --- a/library/jesd204/tb/rx_tb.v +++ b/library/jesd204/tb/rx_tb.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module rx_tb; parameter VCD_FILE = "rx_tb.vcd"; parameter NUM_LANES = 1; diff --git a/library/jesd204/tb/scrambler_tb.v b/library/jesd204/tb/scrambler_tb.v index 4f1f0a45e..47f1f5da1 100644 --- a/library/jesd204/tb/scrambler_tb.v +++ b/library/jesd204/tb/scrambler_tb.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module scrambler_tb; parameter VCD_FILE = "scrambler_tb.vcd"; diff --git a/library/jesd204/tb/soft_pcs_8b10b_sequence_tb.v b/library/jesd204/tb/soft_pcs_8b10b_sequence_tb.v index b57b2536d..f28d56e41 100644 --- a/library/jesd204/tb/soft_pcs_8b10b_sequence_tb.v +++ b/library/jesd204/tb/soft_pcs_8b10b_sequence_tb.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module soft_pcs_8b10b_sequence_tb; parameter VCD_FILE = "soft_pcs_8b10b_sequence_tb.vcd"; diff --git a/library/jesd204/tb/soft_pcs_8b10b_table_tb.v b/library/jesd204/tb/soft_pcs_8b10b_table_tb.v index 694d136de..5655b2b8c 100644 --- a/library/jesd204/tb/soft_pcs_8b10b_table_tb.v +++ b/library/jesd204/tb/soft_pcs_8b10b_table_tb.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module soft_pcs_8b10b_table_tb; parameter VCD_FILE = "soft_pcs_8b10b_table_tb.vcd"; diff --git a/library/jesd204/tb/soft_pcs_loopback_tb.v b/library/jesd204/tb/soft_pcs_loopback_tb.v index c2b38b0c0..14e0bdfd9 100644 --- a/library/jesd204/tb/soft_pcs_loopback_tb.v +++ b/library/jesd204/tb/soft_pcs_loopback_tb.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module soft_pcs_loopback_tb; parameter VCD_FILE = "soft_pcs_loopback_tb.vcd"; parameter DATA_PATH_WIDTH = 4; diff --git a/library/jesd204/tb/soft_pcs_pattern_align_tb.v b/library/jesd204/tb/soft_pcs_pattern_align_tb.v index d1969313c..bf6369d9c 100644 --- a/library/jesd204/tb/soft_pcs_pattern_align_tb.v +++ b/library/jesd204/tb/soft_pcs_pattern_align_tb.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module soft_pcs_pattern_align_tb; parameter VCD_FILE = "soft_pcs_pattern_align_tb.vcd"; diff --git a/library/jesd204/tb/tx_ctrl_phase_tb.v b/library/jesd204/tb/tx_ctrl_phase_tb.v index e7b9de474..0ed324e46 100644 --- a/library/jesd204/tb/tx_ctrl_phase_tb.v +++ b/library/jesd204/tb/tx_ctrl_phase_tb.v @@ -48,6 +48,8 @@ * cycle. */ +`timescale 1ns/100ps + module tx_ctrl_phase_tb; parameter VCD_FILE = "tx_ctrl_phase.vcd"; parameter NUM_LANES = 1; diff --git a/library/jesd204/tb/tx_tb.v b/library/jesd204/tb/tx_tb.v index 84bc009e3..81cd65441 100644 --- a/library/jesd204/tb/tx_tb.v +++ b/library/jesd204/tb/tx_tb.v @@ -42,6 +42,8 @@ // is copyright © 2016-2017, Analog Devices, Inc.” // +`timescale 1ns/100ps + module tx_tb; parameter VCD_FILE = "tx_tb.vcd"; parameter NUM_LANES = 4; @@ -57,6 +59,7 @@ module tx_tb; reg [31:0] tx_data = 'h00000000; wire tx_ready; + wire tx_valid = 1'b1; wire [NUM_LANES-1:0] cfg_lanes_disable; wire [NUM_LINKS-1:0] cfg_links_disable; wire [7:0] cfg_beats_per_multiframe; @@ -112,6 +115,8 @@ module tx_tb; .OCTETS_PER_FRAME(OCTETS_PER_FRAME), .FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME) ) i_cfg ( + .clk(clk), + .cfg_lanes_disable(cfg_lanes_disable), .cfg_links_disable(cfg_links_disable), .cfg_beats_per_multiframe(cfg_beats_per_multiframe), @@ -159,6 +164,7 @@ module tx_tb; .ctrl_manual_sync_request (1'b0), .tx_ready(tx_ready), + .tx_valid(tx_valid), .tx_data({NUM_LANES{tx_data}}), .sync(sync), diff --git a/library/spi_engine/spi_engine_execution/spi_engine_execution.v b/library/spi_engine/spi_engine_execution/spi_engine_execution.v index 79912c822..ee1596152 100644 --- a/library/spi_engine/spi_engine_execution/spi_engine_execution.v +++ b/library/spi_engine/spi_engine_execution/spi_engine_execution.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module spi_engine_execution #( parameter NUM_OF_CS = 1, diff --git a/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v b/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v index 6c5b2c233..15b7f356c 100644 --- a/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v +++ b/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v @@ -33,6 +33,7 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps module spi_engine_interconnect #( diff --git a/library/spi_engine/spi_engine_offload/spi_engine_offload.v b/library/spi_engine/spi_engine_offload/spi_engine_offload.v index cc589de5c..c7edb08d7 100644 --- a/library/spi_engine/spi_engine_offload/spi_engine_offload.v +++ b/library/spi_engine/spi_engine_offload/spi_engine_offload.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module spi_engine_offload #( parameter ASYNC_SPI_CLK = 0, diff --git a/library/util_axis_fifo/address_gray.v b/library/util_axis_fifo/address_gray.v index aec4fd901..a3eb5e25e 100644 --- a/library/util_axis_fifo/address_gray.v +++ b/library/util_axis_fifo/address_gray.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module fifo_address_gray #( parameter ADDRESS_WIDTH = 4 ) ( diff --git a/library/util_axis_fifo/address_gray_pipelined.v b/library/util_axis_fifo/address_gray_pipelined.v index ce5d1f337..1b255543a 100644 --- a/library/util_axis_fifo/address_gray_pipelined.v +++ b/library/util_axis_fifo/address_gray_pipelined.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module fifo_address_gray_pipelined #( parameter ADDRESS_WIDTH = 4 ) ( diff --git a/library/util_axis_fifo/address_sync.v b/library/util_axis_fifo/address_sync.v index 380751cb4..c6b074f25 100644 --- a/library/util_axis_fifo/address_sync.v +++ b/library/util_axis_fifo/address_sync.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module fifo_address_sync #( parameter ADDRESS_WIDTH = 4 ) ( diff --git a/library/util_axis_fifo/util_axis_fifo.v b/library/util_axis_fifo/util_axis_fifo.v index 99923faa9..203162072 100644 --- a/library/util_axis_fifo/util_axis_fifo.v +++ b/library/util_axis_fifo/util_axis_fifo.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module util_axis_fifo #( parameter DATA_WIDTH = 64, parameter ASYNC_CLK = 1, diff --git a/library/util_axis_resize/util_axis_resize.v b/library/util_axis_resize/util_axis_resize.v index 2f9b6cad9..619100a75 100644 --- a/library/util_axis_resize/util_axis_resize.v +++ b/library/util_axis_resize/util_axis_resize.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module util_axis_resize # ( parameter MASTER_DATA_WIDTH = 64, diff --git a/library/util_cdc/sync_bits.v b/library/util_cdc/sync_bits.v index e7e82d3e3..0fbcd053f 100644 --- a/library/util_cdc/sync_bits.v +++ b/library/util_cdc/sync_bits.v @@ -40,6 +40,9 @@ * only able to synchronize multi-bit signals where at max one bit changes per * clock cycle (e.g. a gray counter). */ + +`timescale 1ns/100ps + module sync_bits #( // Number of bits to synchronize diff --git a/library/util_cdc/sync_data.v b/library/util_cdc/sync_data.v index a5c532af5..ea5fd7e58 100644 --- a/library/util_cdc/sync_data.v +++ b/library/util_cdc/sync_data.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module sync_data #( parameter NUM_OF_BITS = 1, parameter ASYNC_CLK = 1 diff --git a/library/util_cdc/sync_event.v b/library/util_cdc/sync_event.v index dcdd0906e..4c72e8b47 100644 --- a/library/util_cdc/sync_event.v +++ b/library/util_cdc/sync_event.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module sync_event #( parameter NUM_OF_EVENTS = 1, parameter ASYNC_CLK = 1 diff --git a/library/util_cdc/sync_gray.v b/library/util_cdc/sync_gray.v index 53a02e6a6..9382d9ddd 100644 --- a/library/util_cdc/sync_gray.v +++ b/library/util_cdc/sync_gray.v @@ -39,6 +39,9 @@ * more than one in one clock cycle in the source domain. I.e. the value may * change by either -1, 0 or +1. */ + +`timescale 1ns/100ps + module sync_gray #( // Bit-width of the counter diff --git a/library/util_cic/cic_comb.v b/library/util_cic/cic_comb.v index c6068ef74..3db33c067 100644 --- a/library/util_cic/cic_comb.v +++ b/library/util_cic/cic_comb.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module cic_comb #( parameter DATA_WIDTH = 32, parameter SEQ = 1, diff --git a/library/util_cic/cic_int.v b/library/util_cic/cic_int.v index 218b39d9b..10d351f7e 100644 --- a/library/util_cic/cic_int.v +++ b/library/util_cic/cic_int.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module cic_int #( parameter DATA_WIDTH = 12, parameter STAGE_WIDTH = 1, diff --git a/library/util_gmii_to_rgmii/mdc_mdio.v b/library/util_gmii_to_rgmii/mdc_mdio.v index ffbf375a7..18cc412ce 100644 --- a/library/util_gmii_to_rgmii/mdc_mdio.v +++ b/library/util_gmii_to_rgmii/mdc_mdio.v @@ -1,3 +1,5 @@ +`timescale 1ns/100ps + // *************************************************************************** // *************************************************************************** // Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. diff --git a/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v b/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v index 918a60bce..24524e84a 100644 --- a/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v +++ b/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v @@ -36,6 +36,8 @@ // specific for MOTCON2 ADI board // works correctly if the PHY is set with Autonegotiation on +`timescale 1ns/100ps + module util_gmii_to_rgmii #( parameter PHY_AD = 5'b10000, diff --git a/library/util_sigma_delta_spi/util_sigma_delta_spi.v b/library/util_sigma_delta_spi/util_sigma_delta_spi.v index 826fb7c10..8244b30da 100644 --- a/library/util_sigma_delta_spi/util_sigma_delta_spi.v +++ b/library/util_sigma_delta_spi/util_sigma_delta_spi.v @@ -33,6 +33,8 @@ // *************************************************************************** // *************************************************************************** +`timescale 1ns/100ps + module util_sigma_delta_spi ( input clk, input resetn,