axi_jesd_gt: Added rx_jesd_rst and tx_jesd_rst.

Resets for both up clock domain and rx clock domain are needed in some projects

library/axi_jesd_gt/axi_jesd_gt.v

@@ -59,6 +59,7 @@ module axi_jesd_gt (
   // core interface
 
   rx_rst,
+  rx_jesd_rst,
   rx_clk_g,
   rx_clk,
   rx_data,
@@ -74,6 +75,7 @@ module axi_jesd_gt (
   rx_ip_data,
 
   tx_rst,
+  tx_jesd_rst,
   tx_clk_g,
   tx_clk,
   tx_data,
@@ -196,6 +198,7 @@ module axi_jesd_gt (
   // core interface
 
   output                                        rx_rst;
+  output                                        rx_jesd_rst;
   output                                        rx_clk_g;
   input                                         rx_clk;
   output  [((PCORE_NUM_OF_RX_LANES*32)-1):0]    rx_data;
@@ -211,6 +214,7 @@ module axi_jesd_gt (
   input   [((PCORE_NUM_OF_RX_LANES*32)-1):0]    rx_ip_data;
 
   output                                        tx_rst;
+  output                                        tx_jesd_rst;
   output                                        tx_clk_g;
   input                                         tx_clk;
   input   [((PCORE_NUM_OF_TX_LANES*32)-1):0]    tx_data;
@@ -743,7 +747,8 @@ module axi_jesd_gt (
     .up_tx_sys_clk_sel (up_tx_sys_clk_sel_s),
     .up_tx_out_clk_sel (up_tx_out_clk_sel_s),
     .rx_clk (rx_clk),
-    .jesd_rx_rst (rx_rst),
+    .rx_rst (rx_rst),
+    .rx_jesd_rst (rx_jesd_rst),
     .rx_ext_sysref (rx_ext_sysref),
     .rx_sysref (rx_sysref),
     .rx_ip_sync (rx_ip_sync),
@@ -754,6 +759,7 @@ module axi_jesd_gt (
     .rx_rst_done_up (rx_rst_done),
     .tx_clk (tx_clk),
     .tx_rst (tx_rst),
+    .tx_jesd_rst (tx_jesd_rst),
     .tx_ext_sysref (tx_ext_sysref),
     .tx_sysref (tx_sysref),
     .tx_sync (tx_sync),

library/axi_jesd_gt/axi_jesd_gt_constr.xdc

@@ -21,7 +21,8 @@ set_property ASYNC_REG TRUE \
   [get_cells -hier *tx_ip_sync_m2_reg*] \
   [get_cells -hier *up_rx_status_m1_reg*] \
   [get_cells -hier *up_tx_status_m1_reg*] \
-  [get_cells -hier *up_rx_rst_done_m1_reg*]
+  [get_cells -hier *up_rx_rst_done_m1_reg*] \
+  [get_cells -hier *up_tx_rst_done_m1_reg*]
 
 set_false_path \
   -from [get_cells -hier es_dma_req_toggle_reg* -filter {primitive_subgroup == flop}] \
@@ -80,5 +81,9 @@ set_false_path \
   -from [get_pins -hier *RXUSRCLK2* ] \
   -to [get_pins -hier up_rx_rst_done_m1_reg*/D ]
 
+set_false_path \
+  -from [get_pins -hier *TXUSRCLK2* ] \
+  -to [get_pins -hier up_tx_rst_done_m1_reg*/D ]
+
 set_false_path \
   -to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}]

library/common/up_gt.v

@@ -56,7 +56,8 @@ module up_gt (
   // receive interface
 
   rx_clk,
-  jesd_rx_rst,
+  rx_rst,
+  rx_jesd_rst,
   rx_ext_sysref,
   rx_sysref,
   rx_ip_sync,
@@ -70,6 +71,7 @@ module up_gt (
 
   tx_clk,
   tx_rst,
+  tx_jesd_rst,
   tx_ext_sysref,
   tx_sysref,
   tx_sync,
@@ -160,7 +162,8 @@ module up_gt (
   // receive interface
 
   input           rx_clk;
-  output          jesd_rx_rst;
+  output          rx_rst;
+  output          rx_jesd_rst;
   input           rx_ext_sysref;
   output          rx_sysref;
   input           rx_ip_sync;
@@ -174,6 +177,7 @@ module up_gt (
 
   input           tx_clk;
   output          tx_rst;
+  output          tx_jesd_rst;
   input           tx_ext_sysref;
   output          tx_sysref;
   input           tx_sync;
@@ -613,8 +617,9 @@ module up_gt (
   ad_rst i_gt_rx_rst_reg  (.preset(up_gt_rx_preset_s),  .clk(drp_clk),  .rst(gt_rx_rst));
   ad_rst i_gt_tx_rst_reg  (.preset(up_gt_tx_preset_s),  .clk(drp_clk),  .rst(gt_tx_rst));
   ad_rst i_rx_rst_reg     (.preset(up_rx_preset_s),     .clk(rx_clk),   .rst(rx_rst));
-  ad_rst i_j_rx_rst_reg   (.preset(up_rx_preset_s),     .clk(up_clk),   .rst(jesd_rx_rst));
+  ad_rst i_j_rx_rst_reg   (.preset(up_rx_preset_s),     .clk(up_clk),   .rst(rx_jesd_rst));
   ad_rst i_tx_rst_reg     (.preset(up_tx_preset_s),     .clk(tx_clk),   .rst(tx_rst));
+  ad_rst i_j_tx_rst_reg   (.preset(up_tx_preset_s),     .clk(up_clk),   .rst(tx_jesd_rst));
 
   // reset done & pll locked