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daq2: Add support for Arria10 SoC platform 

Add support for the AD-FMCDAQ2-EBZ on the Arria10 SoC development board platform.

In its default configuration the Arria10 SoC development board is not fully
compatible with the AD-FMCDAQ2-EBZ and a slight rework is necessary,
changing the position of four 0 Ohm resistors:

  R610: DNI -> R0
  R611: DNI -> R0
  R612: R0 -> DNI
  R613: R0 -> DNI
  R620: DNI -> R0
  R632: DNI -> R0
  R621: R0 -> DNI
  R633: R0 -> DNI

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-07-18 13:34:22 +02:00
parent 17d3e3c64b
commit d5eedf8356
6 changed files with 648 additions and 0 deletions
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3
projects/daq2/Makefile
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@ -8,6 +8,7 @@
.PHONY: all clean clean-all
all:
-make -C a10gx all
-make -C a10soc all
-make -C kc705 all
-make -C kcu105 all
-make -C vc707 all
@ -17,6 +18,7 @@ all:
clean:
make -C a10gx clean
make -C a10soc clean
make -C kc705 clean
make -C kcu105 clean
make -C vc707 clean
@ -26,6 +28,7 @@ clean:
clean-all:
make -C a10gx clean-all
make -C a10soc clean-all
make -C kc705 clean-all
make -C kcu105 clean-all
make -C vc707 clean-all

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projects/daq2/a10soc/Makefile Normal file
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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
ifeq ($(NIOS2_MMU),)
NIOS2_MMU := 1
endif
export ALT_NIOS_MMU_ENABLED := $(NIOS2_MMU)
M_DEPS += system_top.v
M_DEPS += system_qsys.tcl
M_DEPS += system_project.tcl
M_DEPS += system_constr.sdc
M_DEPS += ../common/daq2_spi.v
M_DEPS += ../common/daq2_qsys.tcl
M_DEPS += ../../scripts/adi_tquest.tcl
M_DEPS += ../../scripts/adi_project_alt.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../common/a10soc/a10soc_system_qsys.tcl
M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl
M_DEPS += ../../../library/altera/adi_jesd204/adi_jesd204_hw.tcl
M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v
M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_up.v
M_DEPS += ../../../library/altera/common/ad_mul.v
M_DEPS += ../../../library/altera/common/up_clock_mon_constr.sdc
M_DEPS += ../../../library/altera/common/up_rst_constr.sdc
M_DEPS += ../../../library/altera/common/up_xfer_cntrl_constr.sdc
M_DEPS += ../../../library/altera/common/up_xfer_status_constr.sdc
M_DEPS += ../../../library/altera/jesd204_phy/jesd204_phy_glue.v
M_DEPS += ../../../library/altera/jesd204_phy/jesd204_phy_glue_hw.tcl
M_DEPS += ../../../library/altera/jesd204_phy/jesd204_phy_hw.tcl
M_DEPS += ../../../library/axi_ad9144/axi_ad9144.v
M_DEPS += ../../../library/axi_ad9144/axi_ad9144_channel.v
M_DEPS += ../../../library/axi_ad9144/axi_ad9144_core.v
M_DEPS += ../../../library/axi_ad9144/axi_ad9144_hw.tcl
M_DEPS += ../../../library/axi_ad9144/axi_ad9144_if.v
M_DEPS += ../../../library/axi_ad9680/axi_ad9680.v
M_DEPS += ../../../library/axi_ad9680/axi_ad9680_channel.v
M_DEPS += ../../../library/axi_ad9680/axi_ad9680_hw.tcl
M_DEPS += ../../../library/axi_ad9680/axi_ad9680_if.v
M_DEPS += ../../../library/axi_ad9680/axi_ad9680_pnmon.v
M_DEPS += ../../../library/axi_dmac/2d_transfer.v
M_DEPS += ../../../library/axi_dmac/address_generator.v
M_DEPS += ../../../library/axi_dmac/axi_dmac.v
M_DEPS += ../../../library/axi_dmac/axi_dmac_constr.sdc
M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
M_DEPS += ../../../library/axi_dmac/data_mover.v
M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
M_DEPS += ../../../library/axi_dmac/inc_id.h
M_DEPS += ../../../library/axi_dmac/request_arb.v
M_DEPS += ../../../library/axi_dmac/request_generator.v
M_DEPS += ../../../library/axi_dmac/resp.h
M_DEPS += ../../../library/axi_dmac/response_generator.v
M_DEPS += ../../../library/axi_dmac/response_handler.v
M_DEPS += ../../../library/axi_dmac/splitter.v
M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
M_DEPS += ../../../library/common/ad_axis_inf_rx.v
M_DEPS += ../../../library/common/ad_datafmt.v
M_DEPS += ../../../library/common/ad_dds.v
M_DEPS += ../../../library/common/ad_dds_1.v
M_DEPS += ../../../library/common/ad_dds_sine.v
M_DEPS += ../../../library/common/ad_pnmon.v
M_DEPS += ../../../library/common/ad_rst.v
M_DEPS += ../../../library/common/ad_xcvr_rx_if.v
M_DEPS += ../../../library/common/up_adc_channel.v
M_DEPS += ../../../library/common/up_adc_common.v
M_DEPS += ../../../library/common/up_axi.v
M_DEPS += ../../../library/common/up_clock_mon.v
M_DEPS += ../../../library/common/up_dac_channel.v
M_DEPS += ../../../library/common/up_dac_common.v
M_DEPS += ../../../library/common/up_delay_cntrl.v
M_DEPS += ../../../library/common/up_xfer_cntrl.v
M_DEPS += ../../../library/common/up_xfer_status.v
M_DEPS += ../../../library/jesd204/axi_jesd204_common/jesd204_up_common.v
M_DEPS += ../../../library/jesd204/axi_jesd204_common/jesd204_up_sysref.v
M_DEPS += ../../../library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v
M_DEPS += ../../../library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.sdc
M_DEPS += ../../../library/jesd204/axi_jesd204_rx/axi_jesd204_rx_hw.tcl
M_DEPS += ../../../library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v
M_DEPS += ../../../library/jesd204/axi_jesd204_rx/jesd204_up_rx.v
M_DEPS += ../../../library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v
M_DEPS += ../../../library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v
M_DEPS += ../../../library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.sdc
M_DEPS += ../../../library/jesd204/axi_jesd204_tx/axi_jesd204_tx_hw.tcl
M_DEPS += ../../../library/jesd204/axi_jesd204_tx/jesd204_up_tx.v
M_DEPS += ../../../library/jesd204/jesd204_common/eof.v
M_DEPS += ../../../library/jesd204/jesd204_common/lmfc.v
M_DEPS += ../../../library/jesd204/jesd204_common/pipeline_stage.v
M_DEPS += ../../../library/jesd204/jesd204_common/scrambler.v
M_DEPS += ../../../library/jesd204/jesd204_rx/align_mux.v
M_DEPS += ../../../library/jesd204/jesd204_rx/elastic_buffer.v
M_DEPS += ../../../library/jesd204/jesd204_rx/ilas_monitor.v
M_DEPS += ../../../library/jesd204/jesd204_rx/jesd204_rx_constr.sdc
M_DEPS += ../../../library/jesd204/jesd204_rx/jesd204_rx_hw.tcl
M_DEPS += ../../../library/jesd204/jesd204_rx/lane_latency_monitor.v
M_DEPS += ../../../library/jesd204/jesd204_rx/rx.v
M_DEPS += ../../../library/jesd204/jesd204_rx/rx_cgs.v
M_DEPS += ../../../library/jesd204/jesd204_rx/rx_ctrl.v
M_DEPS += ../../../library/jesd204/jesd204_rx/rx_lane.v
M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/8b10b_decoder.v
M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v
M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl
M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/pattern_align.v
M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_tx/8b10b_encoder.v
M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v
M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl
M_DEPS += ../../../library/jesd204/jesd204_tx/jesd204_tx_constr.sdc
M_DEPS += ../../../library/jesd204/jesd204_tx/jesd204_tx_hw.tcl
M_DEPS += ../../../library/jesd204/jesd204_tx/tx.v
M_DEPS += ../../../library/jesd204/jesd204_tx/tx_ctrl.v
M_DEPS += ../../../library/jesd204/jesd204_tx/tx_lane.v
M_DEPS += ../../../library/scripts/adi_env.tcl
M_DEPS += ../../../library/scripts/adi_ip_alt.tcl
M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
M_DEPS += ../../../library/util_adcfifo/util_adcfifo_constr.sdc
M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
M_DEPS += ../../../library/util_axis_fifo/address_gray.v
M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
M_DEPS += ../../../library/util_axis_fifo/address_sync.v
M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
M_DEPS += ../../../library/util_cdc/sync_bits.v
M_DEPS += ../../../library/util_cdc/sync_data.v
M_DEPS += ../../../library/util_cdc/sync_event.v
M_DEPS += ../../../library/util_cdc/sync_gray.v
M_DEPS += ../../../library/util_cpack/util_cpack.v
M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
M_DEPS += ../../../library/util_upack/util_upack.v
M_DEPS += ../../../library/util_upack/util_upack_dmx.v
M_DEPS += ../../../library/util_upack/util_upack_dsf.v
M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
M_ALTERA := quartus_sh --64bit -t
M_FLIST += *.log
M_FLIST += *_INFO.txt
M_FLIST += *_dump.txt
M_FLIST += db
M_FLIST += *.asm.rpt
M_FLIST += *.done
M_FLIST += *.eda.rpt
M_FLIST += *.fit.*
M_FLIST += *.map.*
M_FLIST += *.sta.*
M_FLIST += *.qsf
M_FLIST += *.qpf
M_FLIST += *.qws
M_FLIST += *.sof
M_FLIST += *.cdf
M_FLIST += *.sld
M_FLIST += *.qdf
M_FLIST += hc_output
M_FLIST += system_bd
M_FLIST += hps_isw_handoff
M_FLIST += hps_sdram_*.csv
M_FLIST += *ddr3_*.csv
M_FLIST += incremental_db
M_FLIST += reconfig_mif
M_FLIST += *.sopcinfo
M_FLIST += *.jdi
M_FLIST += *.pin
M_FLIST += *_summary.csv
M_FLIST += *.dpf
.PHONY: all clean clean-all
all: daq2_a10soc.sof
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
daq2_a10soc.sof: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_ALTERA) system_project.tcl >> daq2_a10soc_quartus.log 2>&1
####################################################################################
####################################################################################

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projects/daq2/a10soc/system_constr.sdc Normal file
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
create_clock -period "3.000 ns" -name rx_ref_clk [get_ports {rx_ref_clk}]
create_clock -period "3.000 ns" -name tx_ref_clk [get_ports {tx_ref_clk}]
# Asynchronous GPIOs
foreach async_input {adc_fda adc_fdb clkd_status[*] dac_irq gpio_bd_i[*] trig} {
set_false_path -from [get_ports $async_input]
}
foreach async_output {adc_pd clkd_sync dac_reset dac_txen gpio_bd_o[*]} {
set_false_path -to [get_ports $async_output]
}
# We really only want to constrain the known good reset paths that are properly
# synchronized here to be able to spot bad paths when they get added.
set_false_path -from [get_ports sys_resetn] -to [get_registers *altera_reset_synchronizer_int_chain*]
set_false_path -from [get_ports sys_resetn] -to [get_keepers *altera_emif*]
derive_pll_clocks
derive_clock_uncertainty

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source ../../scripts/adi_env.tcl
source ../../scripts/adi_project_alt.tcl
adi_project_altera daq2_a10soc
source $ad_hdl_dir/projects/common/a10soc/a10soc_system_assign.tcl
# files
set_global_assignment -name VERILOG_FILE ../common/daq2_spi.v
# lane interface
# Note: This projects requires a hardware rework to function correctly.
# The rework connects FMC header pins directly to the FPGA so that they can be
# accessed by the fabric.
#
# Changes required:
# R610: DNI -> R0
# R611: DNI -> R0
# R612: R0 -> DNI
# R613: R0 -> DNI
# R620: DNI -> R0
# R632: DNI -> R0
# R621: R0 -> DNI
# R633: R0 -> DNI
set_location_assignment PIN_R29 -to rx_ref_clk ; ## B20 FMCA_HPC_GBTCLK1_M2C_P
set_location_assignment PIN_R28 -to "rx_ref_clk(n)" ; ## B21 FMCA_HPC_GBTCLK1_M2C_N
set_location_assignment PIN_P31 -to rx_serial_data[0] ; ## A10 FMCA_HPC_DP3_M2C_P
set_location_assignment PIN_P30 -to "rx_serial_data[0](n)"; ## A11 FMCA_HPC_DP3_M2C_N
set_location_assignment PIN_T31 -to rx_serial_data[1] ; ## C06 FMCA_HPC_DP0_M2C_P
set_location_assignment PIN_T30 -to "rx_serial_data[1](n)"; ## C07 FMCA_HPC_DP0_M2C_N
set_location_assignment PIN_P35 -to rx_serial_data[2] ; ## A06 FMCA_HPC_DP2_M2C_P
set_location_assignment PIN_P34 -to "rx_serial_data[2](n)"; ## A07 FMCA_HPC_DP2_M2C_N
set_location_assignment PIN_R33 -to rx_serial_data[3] ; ## A02 FMCA_HPC_DP1_M2C_P
set_location_assignment PIN_R32 -to "rx_serial_data[3](n)"; ## A03 FMCA_HPC_DP1_M2C_N
set_location_assignment PIN_E12 -to rx_sync ; ## D08 FMCA_HPC_LA01_CC_P
set_location_assignment PIN_E13 -to "rx_sync(n)" ; ## D09 FMCA_HPC_LA01_CC_N
set_location_assignment PIN_C14 -to rx_sysref ; ## G09 FMCA_HPC_LA03_P
set_location_assignment PIN_D14 -to "rx_sysref(n)" ; ## G10 FMCA_HPC_LA03_N
set_location_assignment PIN_N29 -to tx_ref_clk ; ## D04 FMCA_HPC_GBTCLK0_M2C_P
set_location_assignment PIN_N28 -to "tx_ref_clk(n)" ; ## D05 FMCA_HPC_GBTCLK0_M2C_N
set_location_assignment PIN_K39 -to tx_serial_data[0] ; ## A30 FMCA_HPC_DP3_C2M_P (tx_data_p[0])
set_location_assignment PIN_K38 -to "tx_serial_data[0](n)"; ## A31 FMCA_HPC_DP3_C2M_N (tx_data_n[0])
set_location_assignment PIN_N37 -to tx_serial_data[1] ; ## C02 FMCA_HPC_DP0_C2M_P (tx_data_p[3])
set_location_assignment PIN_N36 -to "tx_serial_data[1](n)"; ## C03 FMCA_HPC_DP0_C2M_N (tx_data_n[3])
set_location_assignment PIN_L37 -to tx_serial_data[2] ; ## A26 FMCA_HPC_DP2_C2M_P (tx_data_p[1])
set_location_assignment PIN_L36 -to "tx_serial_data[2](n)"; ## A27 FMCA_HPC_DP2_C2M_N (tx_data_n[1])
set_location_assignment PIN_M39 -to tx_serial_data[3] ; ## A22 FMCA_HPC_DP1_C2M_P (tx_data_p[2])
set_location_assignment PIN_M38 -to "tx_serial_data[3](n)"; ## A23 FMCA_HPC_DP1_C2M_N (tx_data_n[2])
set_location_assignment PIN_C13 -to tx_sync ; ## H07 FMCA_HPC_LA02_P
set_location_assignment PIN_D13 -to "tx_sync(n)" ; ## H08 FMCA_HPC_LA02_N
set_location_assignment PIN_H12 -to tx_sysref ; ## H10 FMCA_HPC_LA04_P
set_location_assignment PIN_H13 -to "tx_sysref(n)" ; ## H11 FMCA_HPC_LA04_N
set_instance_assignment -name IO_STANDARD LVDS -to rx_ref_clk
set_instance_assignment -name IO_STANDARD LVDS -to "rx_ref_clk(n)"
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_serial_data
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to rx_serial_data
set_instance_assignment -name IO_STANDARD LVDS -to rx_sync
set_instance_assignment -name IO_STANDARD LVDS -to "rx_sync(n)"
set_instance_assignment -name IO_STANDARD LVDS -to rx_sysref
set_instance_assignment -name IO_STANDARD LVDS -to "rx_sysref(n)"
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_sysref
set_instance_assignment -name IO_STANDARD LVDS -to tx_ref_clk
set_instance_assignment -name IO_STANDARD LVDS -to "tx_ref_clk(n)"
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_serial_data
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to tx_serial_data
set_instance_assignment -name IO_STANDARD LVDS -to tx_sync
set_instance_assignment -name IO_STANDARD LVDS -to "tx_sync(n)"
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "tx_sync(n)"
set_instance_assignment -name IO_STANDARD LVDS -to tx_sysref
set_instance_assignment -name IO_STANDARD LVDS -to "tx_sysref(n)"
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sysref
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "tx_sysref(n)"
# Merge RX and TX into single transceiver
for {set i 0} {$i < 4} {incr i} {
set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_${i} -to rx_serial_data[${i}]
set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_${i} -to tx_serial_data[${i}]
}
# gpio
set_location_assignment PIN_A9 -to trig ; ## H13 FMCA_LA07_P
set_location_assignment PIN_B9 -to "trig(n)" ; ## H14 FMCA_LA07_N
set_location_assignment PIN_D9 -to adc_fdb ; ## H17 FMCA_LA11_N
set_location_assignment PIN_C9 -to adc_fda ; ## H16 FMCA_LA11_P
set_location_assignment PIN_M12 -to dac_irq ; ## G15 FMCA_LA12_P
set_location_assignment PIN_K11 -to clkd_status[1] ; ## D18 FMCA_LA13_N
set_location_assignment PIN_J11 -to clkd_status[0] ; ## D17 FMCA_LA13_P
set_location_assignment PIN_A10 -to adc_pd ; ## C10 FMCA_LA06_P
set_location_assignment PIN_N13 -to dac_txen ; ## G16 FMCA_LA12_N
set_location_assignment PIN_A8 -to dac_reset ; ## C15 FMCA_LA10_N
set_location_assignment PIN_B11 -to clkd_sync ; ## G12 FMCA_LA08_P
set_instance_assignment -name IO_STANDARD LVDS -to trig
set_instance_assignment -name IO_STANDARD LVDS -to "trig(n)"
set_instance_assignment -name IO_STANDARD "1.8 V" -to adc_fdb
set_instance_assignment -name IO_STANDARD "1.8 V" -to adc_fda
set_instance_assignment -name IO_STANDARD "1.8 V" -to dac_irq
set_instance_assignment -name IO_STANDARD "1.8 V" -to clkd_status[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to clkd_status[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to adc_pd
set_instance_assignment -name IO_STANDARD "1.8 V" -to dac_txen
set_instance_assignment -name IO_STANDARD "1.8 V" -to dac_reset
set_instance_assignment -name IO_STANDARD "1.8 V" -to clkd_sync
# spi
set_location_assignment PIN_F13 -to spi_csn_clk ; ## D11 FMCA_LA05_P
set_location_assignment PIN_A7 -to spi_csn_dac ; ## C14 FMCA_LA10_P
set_location_assignment PIN_A13 -to spi_csn_adc ; ## D15 FMCA_LA09_N
set_location_assignment PIN_F14 -to spi_clk ; ## D12 FMCA_LA05_N
set_location_assignment PIN_A12 -to spi_sdio ; ## D14 FMCA_LA09_P
set_location_assignment PIN_B12 -to spi_dir ; ## G13 FMCA_LA08_N
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_clk
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_dac
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_adc
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_clk
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_sdio
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_dir
execute_flow -compile

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projects/daq2/a10soc/system_qsys.tcl Normal file
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source $ad_hdl_dir/projects/common/a10soc/a10soc_system_qsys.tcl
source ../common/daq2_qsys.tcl

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
// clock and resets
input sys_clk,
input sys_resetn,
// hps-ddr4 (32)
input hps_ddr_ref_clk,
output [ 0:0] hps_ddr_clk_p,
output [ 0:0] hps_ddr_clk_n,
output [ 16:0] hps_ddr_a,
output [ 1:0] hps_ddr_ba,
output [ 0:0] hps_ddr_bg,
output [ 0:0] hps_ddr_cke,
output [ 0:0] hps_ddr_cs_n,
output [ 0:0] hps_ddr_odt,
output [ 0:0] hps_ddr_reset_n,
output [ 0:0] hps_ddr_act_n,
output [ 0:0] hps_ddr_par,
input [ 0:0] hps_ddr_alert_n,
inout [ 3:0] hps_ddr_dqs_p,
inout [ 3:0] hps_ddr_dqs_n,
inout [ 31:0] hps_ddr_dq,
inout [ 3:0] hps_ddr_dbi_n,
input hps_ddr_rzq,
// hps-ethernet
input [ 0:0] hps_eth_rxclk,
input [ 0:0] hps_eth_rxctl,
input [ 3:0] hps_eth_rxd,
output [ 0:0] hps_eth_txclk,
output [ 0:0] hps_eth_txctl,
output [ 3:0] hps_eth_txd,
output [ 0:0] hps_eth_mdc,
inout [ 0:0] hps_eth_mdio,
// hps-sdio
output [ 0:0] hps_sdio_clk,
inout [ 0:0] hps_sdio_cmd,
inout [ 7:0] hps_sdio_d,
// hps-usb
input [ 0:0] hps_usb_clk,
input [ 0:0] hps_usb_dir,
input [ 0:0] hps_usb_nxt,
output [ 0:0] hps_usb_stp,
inout [ 7:0] hps_usb_d,
// hps-uart
input [ 0:0] hps_uart_rx,
output [ 0:0] hps_uart_tx,
// hps-i2c (shared w fmc-a, fmc-b)
inout [ 0:0] hps_i2c_sda,
inout [ 0:0] hps_i2c_scl,
// hps-gpio (max-v-u16)
inout [ 3:0] hps_gpio,
// gpio (max-v-u21)
input [ 7:0] gpio_bd_i,
output [ 3:0] gpio_bd_o,
// lane interface
input rx_ref_clk,
input rx_sysref,
output rx_sync,
input [ 3:0] rx_serial_data,
input tx_ref_clk,
input tx_sysref,
input tx_sync,
output [ 3:0] tx_serial_data,
// gpio
input trig,
input adc_fdb,
input adc_fda,
input dac_irq,
input [ 1:0] clkd_status,
output adc_pd,
output dac_txen,
output dac_reset,
output clkd_sync,
// spi
output spi_csn_clk,
output spi_csn_dac,
output spi_csn_adc,
output spi_clk,
inout spi_sdio,
output spi_dir);
// internal signals
wire sys_hps_resetn;
wire sys_resetn_s;
wire [ 63:0] gpio_i;
wire [ 63:0] gpio_o;
wire spi_miso_s;
wire spi_mosi_s;
wire [ 7:0] spi_csn_s;
// assignments
assign spi_csn_adc = spi_csn_s[2];
assign spi_csn_dac = spi_csn_s[1];
assign spi_csn_clk = spi_csn_s[0];
daq2_spi i_daq2_spi (
.spi_csn (spi_csn_s[2:0]),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi_s),
.spi_miso (spi_miso_s),
.spi_sdio (spi_sdio),
.spi_dir (spi_dir));
// gpio in & out are separate cores
assign gpio_i[63:44] = gpio_o[63:44];
assign gpio_i[43:43] = trig;
assign gpio_i[42:40] = gpio_o[42:40];
assign adc_pd = gpio_o[42];
assign dac_txen = gpio_o[41];
assign dac_reset = gpio_o[40];
assign gpio_i[39:39] = gpio_o[39];
assign gpio_i[38:38] = gpio_o[38];
assign clkd_sync = gpio_o[38];
assign gpio_i[37:37] = gpio_o[37];
assign gpio_i[36:36] = adc_fdb;
assign gpio_i[35:35] = adc_fda;
assign gpio_i[34:34] = dac_irq;
assign gpio_i[33:32] = clkd_status;
// board stuff (max-v-u21)
assign gpio_i[31:12] = gpio_o[31:12];
assign gpio_i[11: 4] = gpio_bd_i;
assign gpio_i[ 3: 0] = gpio_o[3:0];
assign gpio_bd_o = gpio_o[3:0];
// peripheral reset
assign sys_resetn_s = sys_resetn & sys_hps_resetn;
// instantiations
system_bd i_system_bd (
.sys_clk_clk (sys_clk),
.sys_gpio_bd_in_port (gpio_i[31:0]),
.sys_gpio_bd_out_port (gpio_o[31:0]),
.sys_gpio_in_export (gpio_i[63:32]),
.sys_gpio_out_export (gpio_o[63:32]),
.sys_hps_ddr_mem_ck (hps_ddr_clk_p),
.sys_hps_ddr_mem_ck_n (hps_ddr_clk_n),
.sys_hps_ddr_mem_a (hps_ddr_a),
.sys_hps_ddr_mem_act_n (hps_ddr_act_n),
.sys_hps_ddr_mem_ba (hps_ddr_ba),
.sys_hps_ddr_mem_bg (hps_ddr_bg),
.sys_hps_ddr_mem_cke (hps_ddr_cke),
.sys_hps_ddr_mem_cs_n (hps_ddr_cs_n),
.sys_hps_ddr_mem_odt (hps_ddr_odt),
.sys_hps_ddr_mem_reset_n (hps_ddr_reset_n),
.sys_hps_ddr_mem_par (hps_ddr_par),
.sys_hps_ddr_mem_alert_n (hps_ddr_alert_n),
.sys_hps_ddr_mem_dqs (hps_ddr_dqs_p),
.sys_hps_ddr_mem_dqs_n (hps_ddr_dqs_n),
.sys_hps_ddr_mem_dq (hps_ddr_dq),
.sys_hps_ddr_mem_dbi_n (hps_ddr_dbi_n),
.sys_hps_ddr_oct_oct_rzqin (hps_ddr_rzq),
.sys_hps_ddr_ref_clk_clk (hps_ddr_ref_clk),
.sys_hps_ddr_rstn_reset_n (sys_resetn),
.sys_hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk),
.sys_hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]),
.sys_hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]),
.sys_hps_io_hps_io_phery_emac0_TXD2 (hps_eth_txd[2]),
.sys_hps_io_hps_io_phery_emac0_TXD3 (hps_eth_txd[3]),
.sys_hps_io_hps_io_phery_emac0_RX_CTL (hps_eth_rxctl),
.sys_hps_io_hps_io_phery_emac0_TX_CTL (hps_eth_txctl),
.sys_hps_io_hps_io_phery_emac0_RX_CLK (hps_eth_rxclk),
.sys_hps_io_hps_io_phery_emac0_RXD0 (hps_eth_rxd[0]),
.sys_hps_io_hps_io_phery_emac0_RXD1 (hps_eth_rxd[1]),
.sys_hps_io_hps_io_phery_emac0_RXD2 (hps_eth_rxd[2]),
.sys_hps_io_hps_io_phery_emac0_RXD3 (hps_eth_rxd[3]),
.sys_hps_io_hps_io_phery_emac0_MDIO (hps_eth_mdio),
.sys_hps_io_hps_io_phery_emac0_MDC (hps_eth_mdc),
.sys_hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_cmd),
.sys_hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_d[0]),
.sys_hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_d[1]),
.sys_hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_d[2]),
.sys_hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_d[3]),
.sys_hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_d[4]),
.sys_hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_d[5]),
.sys_hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_d[6]),
.sys_hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_d[7]),
.sys_hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_clk),
.sys_hps_io_hps_io_phery_usb0_DATA0 (hps_usb_d[0]),
.sys_hps_io_hps_io_phery_usb0_DATA1 (hps_usb_d[1]),
.sys_hps_io_hps_io_phery_usb0_DATA2 (hps_usb_d[2]),
.sys_hps_io_hps_io_phery_usb0_DATA3 (hps_usb_d[3]),
.sys_hps_io_hps_io_phery_usb0_DATA4 (hps_usb_d[4]),
.sys_hps_io_hps_io_phery_usb0_DATA5 (hps_usb_d[5]),
.sys_hps_io_hps_io_phery_usb0_DATA6 (hps_usb_d[6]),
.sys_hps_io_hps_io_phery_usb0_DATA7 (hps_usb_d[7]),
.sys_hps_io_hps_io_phery_usb0_CLK (hps_usb_clk),
.sys_hps_io_hps_io_phery_usb0_STP (hps_usb_stp),
.sys_hps_io_hps_io_phery_usb0_DIR (hps_usb_dir),
.sys_hps_io_hps_io_phery_usb0_NXT (hps_usb_nxt),
.sys_hps_io_hps_io_phery_uart1_RX (hps_uart_rx),
.sys_hps_io_hps_io_phery_uart1_TX (hps_uart_tx),
.sys_hps_io_hps_io_phery_i2c1_SDA (hps_i2c_sda),
.sys_hps_io_hps_io_phery_i2c1_SCL (hps_i2c_scl),
.sys_hps_io_hps_io_gpio_gpio1_io5 (hps_gpio[0]),
.sys_hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]),
.sys_hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]),
.sys_hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]),
.sys_hps_out_rstn_reset_n (sys_hps_resetn),
.sys_hps_rstn_reset_n (sys_resetn),
.sys_rstn_reset_n (sys_resetn_s),
.sys_spi_MISO (spi_miso_s),
.sys_spi_MOSI (spi_mosi_s),
.sys_spi_SCLK (spi_clk),
.sys_spi_SS_n (spi_csn_s),
.tx_serial_data_tx_serial_data (tx_serial_data),
.tx_ref_clk_clk (tx_ref_clk),
.tx_sync_export (tx_sync),
.tx_sysref_export (tx_sysref),
.rx_serial_data_rx_serial_data (rx_serial_data),
.rx_ref_clk_clk (rx_ref_clk),
.rx_sync_export (rx_sync),
.rx_sysref_export (rx_sysref));
endmodule
// ***************************************************************************
// ***************************************************************************