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unused ip cores

main
Rejeesh Kutty 2015-08-20 11:37:00 -04:00
parent b0079e60bf
commit d59ec3b36d
10 changed files with 0 additions and 383 deletions
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44
library/util_jesd_align/Makefile
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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS := util_jesd_align_ip.tcl
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += ../common/ad_jesd_align.v
M_DEPS += util_jesd_align.v
M_DEPS += util_jesd_align_constr.xdc
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += .Xil
.PHONY: all clean clean-all
all: util_jesd_align.xpr
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
util_jesd_align.xpr: $(M_DEPS)
rm -rf $(M_FLIST)
$(M_VIVADO) util_jesd_align_ip.tcl >> util_jesd_align_ip.log 2>&1
####################################################################################
####################################################################################

87
library/util_jesd_align/util_jesd_align.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_jesd_align (
// xcvr interface
rx_clk,
rx_ip_sof,
rx_ip_sof_out,
rx_ip_data,
rx_sof,
rx_data);
// parameters
parameter NUM_OF_LANES = 2;
parameter ST_VALID_WIDTH = 1;
parameter ST_DATA_WIDTH = 128;
// xcvr interface
input rx_clk;
input [ 3:0] rx_ip_sof;
output [ 3:0] rx_ip_sof_out;
input [((NUM_OF_LANES*32)-1):0] rx_ip_data;
output [((NUM_OF_LANES* 1)-1):0] rx_sof;
output [((NUM_OF_LANES*32)-1):0] rx_data;
// qsys can not multi-cast.
assign rx_ip_sof_out = rx_ip_sof;
// only for altera, xcvr+jesd do not frame align
genvar n;
generate
for (n = 0; n < NUM_OF_LANES; n = n + 1) begin: g_lane
ad_jesd_align i_jesd_align (
.rx_clk (rx_clk),
.rx_ip_sof (rx_ip_sof),
.rx_ip_data (rx_ip_data[n*32+31:n*32]),
.rx_sof (rx_sof[n]),
.rx_data (rx_data[n*32+31:n*32]));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

0
library/util_jesd_align/util_jesd_align_constr.xdc
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53
library/util_jesd_align/util_jesd_align_hw.tcl
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package require -exact qsys 13.0
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
set_module_property NAME util_jesd_align
set_module_property DESCRIPTION "JESD Align Utility"
set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME util_jesd_align
set_module_property ELABORATION_CALLBACK p_util_jesd_align
# files
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL util_jesd_align
add_fileset_file ad_jesd_align.v VERILOG PATH $ad_hdl_dir/library/common/altera/ad_jesd_align.v
add_fileset_file util_jesd_align.v VERILOG PATH util_jesd_align.v TOP_LEVEL_FILE
# parameters
add_parameter NUM_OF_LANES INTEGER 0
set_parameter_property NUM_OF_LANES DEFAULT_VALUE 2
set_parameter_property NUM_OF_LANES DISPLAY_NAME NUM_OF_LANES
set_parameter_property NUM_OF_LANES TYPE INTEGER
set_parameter_property NUM_OF_LANES UNITS None
set_parameter_property NUM_OF_LANES HDL_PARAMETER true
# transceiver interface
add_interface if_rx_clk clock end
add_interface_port if_rx_clk rx_clk clk Input 1
add_interface if_rx_ip_data avalon_streaming end
add_interface_port if_rx_ip_data rx_ip_data data Input 32*NUM_OF_LANES
add_interface if_rx_data avalon_streaming start
add_interface_port if_rx_data rx_data data Output 32*NUM_OF_LANES
ad_alt_intf signal rx_ip_sof input 4 export
ad_alt_intf signal rx_ip_sof_out output 4 export
ad_alt_intf signal rx_sof output NUM_OF_LANES export
proc p_util_jesd_align {} {
set p_num_of_lanes [get_parameter_value "NUM_OF_LANES"]
set_interface_property if_rx_ip_data associatedClock if_rx_clk
set_interface_property if_rx_ip_data dataBitsPerSymbol [expr (32*$p_num_of_lanes)]
set_interface_property if_rx_data associatedClock if_rx_clk
set_interface_property if_rx_data dataBitsPerSymbol [expr (32*$p_num_of_lanes)]
}

18
library/util_jesd_align/util_jesd_align_ip.tcl
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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create util_jesd_align
adi_ip_files util_jesd_align [list \
"$ad_hdl_dir/library/common/ad_jesd_align.v" \
"util_jesd_align.v" \
"util_jesd_align_constr.xdc" ]
adi_ip_properties_lite util_jesd_align
adi_ip_constraints util_jesd_align [list \
"util_jesd_align_constr.xdc" ]
ipx::save_core [ipx::current_core]

43
library/util_jesd_xmit/Makefile
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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS := util_jesd_xmit_ip.tcl
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += util_jesd_xmit.v
M_DEPS += util_jesd_xmit_constr.xdc
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += .Xil
.PHONY: all clean clean-all
all: util_jesd_xmit.xpr
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
util_jesd_xmit.xpr: $(M_DEPS)
rm -rf $(M_FLIST)
$(M_VIVADO) util_jesd_xmit_ip.tcl >> util_jesd_xmit_ip.log 2>&1
####################################################################################
####################################################################################

73
library/util_jesd_xmit/util_jesd_xmit.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_jesd_xmit (
// xcvr interface
tx_clk,
tx_data,
tx_ip_data);
// parameters
parameter NUM_OF_LANES = 2;
// xcvr interface
input tx_clk;
input [((NUM_OF_LANES*32)-1):0] tx_data;
output [((NUM_OF_LANES*32)-1):0] tx_ip_data;
// only for altera, xcvr+jesd
genvar n;
generate
for (n = 0; n < NUM_OF_LANES; n = n + 1) begin: g_lane
assign tx_ip_data[((n*32) + 31):((n*32) + 24)] = tx_data[((n*32) + 7):((n*32) + 0)];
assign tx_ip_data[((n*32) + 23):((n*32) + 16)] = tx_data[((n*32) + 15):((n*32) + 8)];
assign tx_ip_data[((n*32) + 15):((n*32) + 8)] = tx_data[((n*32) + 23):((n*32) + 16)];
assign tx_ip_data[((n*32) + 7):((n*32) + 0)] = tx_data[((n*32) + 31):((n*32) + 24)];
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

0
library/util_jesd_xmit/util_jesd_xmit_constr.xdc
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48
library/util_jesd_xmit/util_jesd_xmit_hw.tcl
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package require -exact qsys 13.0
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
set_module_property NAME util_jesd_xmit
set_module_property DESCRIPTION "JESD Xmit Utility"
set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME util_jesd_xmit
set_module_property ELABORATION_CALLBACK p_util_jesd_xmit
# files
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL util_jesd_xmit
add_fileset_file util_jesd_xmit.v VERILOG PATH util_jesd_xmit.v TOP_LEVEL_FILE
# parameters
add_parameter NUM_OF_LANES INTEGER 0
set_parameter_property NUM_OF_LANES DEFAULT_VALUE 2
set_parameter_property NUM_OF_LANES DISPLAY_NAME NUM_OF_LANES
set_parameter_property NUM_OF_LANES TYPE INTEGER
set_parameter_property NUM_OF_LANES UNITS None
set_parameter_property NUM_OF_LANES HDL_PARAMETER true
# transceiver interface
add_interface if_tx_clk clock end
add_interface_port if_tx_clk tx_clk clk Input 1
add_interface if_tx_ip_data avalon_streaming start
add_interface_port if_tx_ip_data tx_ip_data data Output 32*NUM_OF_LANES
add_interface if_tx_data avalon_streaming end
add_interface_port if_tx_data tx_data data Input 32*NUM_OF_LANES
proc p_util_jesd_xmit {} {
set p_num_of_lanes [get_parameter_value "NUM_OF_LANES"]
set_interface_property if_tx_ip_data associatedClock if_tx_clk
set_interface_property if_tx_ip_data dataBitsPerSymbol [expr (32*$p_num_of_lanes)]
set_interface_property if_tx_data associatedClock if_tx_clk
set_interface_property if_tx_data dataBitsPerSymbol [expr (32*$p_num_of_lanes)]
}

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library/util_jesd_xmit/util_jesd_xmit_ip.tcl
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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create util_jesd_xmit
adi_ip_files util_jesd_xmit [list \
"util_jesd_xmit.v" \
"util_jesd_xmit_constr.xdc" ]
adi_ip_properties_lite util_jesd_xmit
adi_ip_constraints util_jesd_xmit [list \
"util_jesd_xmit_constr.xdc" ]
ipx::save_core [ipx::current_core]