From d4fb7062d914ce5af981cab17921523964337852 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Mon, 14 Feb 2022 10:54:42 +0000 Subject: [PATCH] vcu128/vcu128_system_constr: Enable internal diff term for Ethernet clock There are no external termination resistors on the VCU118 and VCU128 for the SGMII clock lines. The board files of the VCU118 enables them, but this was not reflected in the constraint files. For VCU128 the clocking is similar, even if diff terms are not set in the board files we should have a consistent approach with the VCU118. --- projects/common/vcu128/vcu128_system_constr.xdc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/common/vcu128/vcu128_system_constr.xdc b/projects/common/vcu128/vcu128_system_constr.xdc index 8e17fa43a..78cd85904 100644 --- a/projects/common/vcu128/vcu128_system_constr.xdc +++ b/projects/common/vcu128/vcu128_system_constr.xdc @@ -16,8 +16,8 @@ set_property PACKAGE_PIN BH22 [get_ports phy_tx_n] set_property PACKAGE_PIN BJ22 [get_ports phy_rx_p] set_property PACKAGE_PIN BK21 [get_ports phy_rx_n] -set_property -dict {PACKAGE_PIN BH27 IOSTANDARD LVDS} [get_ports phy_clk_p] -set_property -dict {PACKAGE_PIN BJ27 IOSTANDARD LVDS} [get_ports phy_clk_n] +set_property -dict {PACKAGE_PIN BH27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports phy_clk_p] +set_property -dict {PACKAGE_PIN BJ27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports phy_clk_n] set_property -dict {PACKAGE_PIN BN27 IOSTANDARD LVCMOS18} [get_ports mdio_mdc] set_property -dict {PACKAGE_PIN BG23 IOSTANDARD LVCMOS18} [get_ports mdio_mdio]