From d4820dd55a87d63bb8ea11f39d375e4f676623f9 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Wed, 26 Jul 2017 10:20:39 -0400 Subject: [PATCH] library- remove ad_cmos_* --- library/xilinx/common/ad_cmos_clk.v | 82 -------------- library/xilinx/common/ad_cmos_in.v | 170 ---------------------------- library/xilinx/common/ad_cmos_out.v | 140 ----------------------- projects/ad77681evb/zed/Makefile | 2 +- 4 files changed, 1 insertion(+), 393 deletions(-) delete mode 100644 library/xilinx/common/ad_cmos_clk.v delete mode 100644 library/xilinx/common/ad_cmos_in.v delete mode 100644 library/xilinx/common/ad_cmos_out.v diff --git a/library/xilinx/common/ad_cmos_clk.v b/library/xilinx/common/ad_cmos_clk.v deleted file mode 100644 index 622b58481..000000000 --- a/library/xilinx/common/ad_cmos_clk.v +++ /dev/null @@ -1,82 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module ad_cmos_clk #( - - parameter DEVICE_TYPE = 0) ( - - input rst, - output locked, - - input clk_in, - output clk); - - localparam SERIES7 = 0; - localparam VIRTEX6 = 1; - - // wires - - wire clk_ibuf_s; - - // defaults - - assign locked = 1'b1; - - // instantiations - - IBUFG i_rx_clk_ibuf ( - .I (clk_in), - .O (clk_ibuf_s)); - - generate - if (DEVICE_TYPE == VIRTEX6) begin - BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_rbuf ( - .CLR (1'b0), - .CE (1'b1), - .I (clk_ibuf_s), - .O (clk)); - end else begin - BUFG i_clk_gbuf ( - .I (clk_ibuf_s), - .O (clk)); - end - endgenerate - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/xilinx/common/ad_cmos_in.v b/library/xilinx/common/ad_cmos_in.v deleted file mode 100644 index e84c7e69d..000000000 --- a/library/xilinx/common/ad_cmos_in.v +++ /dev/null @@ -1,170 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module ad_cmos_in #( - - parameter DEVICE_TYPE = 0, - parameter IODELAY_CTRL = 0, - parameter IODELAY_GROUP = "dev_if_delay_group") ( - - // data interface - - input rx_clk, - input rx_data_in, - output rx_data_p, - output reg rx_data_n, - - // delay-data interface - - input up_clk, - input up_dld, - input [ 4:0] up_dwdata, - output [ 4:0] up_drdata, - - // delay-cntrl interface - - input delay_clk, - input delay_rst, - output delay_locked); - - localparam SERIES7 = 0; - localparam VIRTEX6 = 1; - - // internal registers - - // internal signals - - wire rx_data_n_s; - wire rx_data_ibuf_s; - wire rx_data_idelay_s; - - // delay controller - - generate - if (IODELAY_CTRL == 1) begin - (* IODELAY_GROUP = IODELAY_GROUP *) - IDELAYCTRL i_delay_ctrl ( - .RST (delay_rst), - .REFCLK (delay_clk), - .RDY (delay_locked)); - end else begin - assign delay_locked = 1'b1; - end - endgenerate - - // receive data interface, ibuf -> idelay -> iddr - - IBUF i_rx_data_ibuf ( - .I (rx_data_in), - .O (rx_data_ibuf_s)); - - generate - if (DEVICE_TYPE == VIRTEX6) begin - (* IODELAY_GROUP = IODELAY_GROUP *) - IODELAYE1 #( - .CINVCTRL_SEL ("FALSE"), - .DELAY_SRC ("I"), - .HIGH_PERFORMANCE_MODE ("TRUE"), - .IDELAY_TYPE ("VAR_LOADABLE"), - .IDELAY_VALUE (0), - .ODELAY_TYPE ("FIXED"), - .ODELAY_VALUE (0), - .REFCLK_FREQUENCY (200.0), - .SIGNAL_PATTERN ("DATA")) - i_rx_data_idelay ( - .T (1'b1), - .CE (1'b0), - .INC (1'b0), - .CLKIN (1'b0), - .DATAIN (1'b0), - .ODATAIN (1'b0), - .CINVCTRL (1'b0), - .C (up_clk), - .IDATAIN (rx_data_ibuf_s), - .DATAOUT (rx_data_idelay_s), - .RST (up_dld), - .CNTVALUEIN (up_dwdata), - .CNTVALUEOUT (up_drdata)); - end else begin - (* IODELAY_GROUP = IODELAY_GROUP *) - IDELAYE2 #( - .CINVCTRL_SEL ("FALSE"), - .DELAY_SRC ("IDATAIN"), - .HIGH_PERFORMANCE_MODE ("FALSE"), - .IDELAY_TYPE ("VAR_LOAD"), - .IDELAY_VALUE (0), - .REFCLK_FREQUENCY (200.0), - .PIPE_SEL ("FALSE"), - .SIGNAL_PATTERN ("DATA")) - i_rx_data_idelay ( - .CE (1'b0), - .INC (1'b0), - .DATAIN (1'b0), - .LDPIPEEN (1'b0), - .CINVCTRL (1'b0), - .REGRST (1'b0), - .C (up_clk), - .IDATAIN (rx_data_ibuf_s), - .DATAOUT (rx_data_idelay_s), - .LD (up_dld), - .CNTVALUEIN (up_dwdata), - .CNTVALUEOUT (up_drdata)); - end - endgenerate - - IDDR #( - .DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"), - .INIT_Q1 (1'b0), - .INIT_Q2 (1'b0), - .SRTYPE ("ASYNC")) - i_rx_data_iddr ( - .CE (1'b1), - .R (1'b0), - .S (1'b0), - .C (rx_clk), - .D (rx_data_idelay_s), - .Q1 (rx_data_p), - .Q2 (rx_data_n_s)); - - always @(posedge rx_clk) begin - rx_data_n <= rx_data_n_s; - end - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/xilinx/common/ad_cmos_out.v b/library/xilinx/common/ad_cmos_out.v deleted file mode 100644 index 21142c689..000000000 --- a/library/xilinx/common/ad_cmos_out.v +++ /dev/null @@ -1,140 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module ad_cmos_out #( - - parameter DEVICE_TYPE = 0, - parameter IODELAY_ENABLE = 0, - parameter IODELAY_CTRL = 0, - parameter IODELAY_GROUP = "dev_if_delay_group") ( - - // data interface - - input tx_clk, - input tx_data_p, - input tx_data_n, - output tx_data_out, - - // delay-data interface - - input up_clk, - input up_dld, - input [ 4:0] up_dwdata, - output [ 4:0] up_drdata, - - // delay-cntrl interface - - input delay_clk, - input delay_rst, - output delay_locked); - - localparam SERIES7 = 0; - localparam VIRTEX6 = 1; - - // internal signals - - wire tx_data_oddr_s; - wire tx_data_odelay_s; - - // delay controller - - generate - if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == SERIES7) && (IODELAY_CTRL == 1)) begin - (* IODELAY_GROUP = IODELAY_GROUP *) - IDELAYCTRL i_delay_ctrl ( - .RST (delay_rst), - .REFCLK (delay_clk), - .RDY (delay_locked)); - end else begin - assign delay_locked = 1'b1; - end - endgenerate - - // transmit data interface, oddr -> odelay -> obuf - - ODDR #( - .DDR_CLK_EDGE ("SAME_EDGE"), - .INIT (1'b0), - .SRTYPE ("ASYNC")) - i_tx_data_oddr ( - .CE (1'b1), - .R (1'b0), - .S (1'b0), - .C (tx_clk), - .D1 (tx_data_p), - .D2 (tx_data_n), - .Q (tx_data_oddr_s)); - - generate - if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == SERIES7)) begin - (* IODELAY_GROUP = IODELAY_GROUP *) - ODELAYE2 #( - .CINVCTRL_SEL ("FALSE"), - .DELAY_SRC ("ODATAIN"), - .HIGH_PERFORMANCE_MODE ("FALSE"), - .ODELAY_TYPE ("VAR_LOAD"), - .ODELAY_VALUE (0), - .REFCLK_FREQUENCY (200.0), - .PIPE_SEL ("FALSE"), - .SIGNAL_PATTERN ("DATA")) - i_tx_data_odelay ( - .CE (1'b0), - .CLKIN (1'b0), - .INC (1'b0), - .LDPIPEEN (1'b0), - .CINVCTRL (1'b0), - .REGRST (1'b0), - .C (up_clk), - .ODATAIN (tx_data_oddr_s), - .DATAOUT (tx_data_odelay_s), - .LD (up_dld), - .CNTVALUEIN (up_dwdata), - .CNTVALUEOUT (up_drdata)); - end else begin - assign up_drdata = 5'd0; - assign tx_data_odelay_s = tx_data_oddr_s; - end - endgenerate - - OBUF i_tx_data_obuf ( - .I (tx_data_odelay_s), - .O (tx_data_out)); - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/projects/ad77681evb/zed/Makefile b/projects/ad77681evb/zed/Makefile index 922fc497c..aecf741bf 100644 --- a/projects/ad77681evb/zed/Makefile +++ b/projects/ad77681evb/zed/Makefile @@ -16,7 +16,7 @@ M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_bd.tcl M_DEPS += ../../../library/xilinx/common/ad_iobuf.v -M_DEPS += ../../../library/xilinx/common/ad_cmos_clk.v +M_DEPS += ../../../library/xilinx/common/ad_data_clk.v M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr