From d47776a4a0984cfb6ae7ef45bdeff498b8606206 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Fri, 3 Oct 2014 11:05:09 -0400 Subject: [PATCH] ad9152: 9144 copy --- library/axi_ad9152/axi_ad9152.v | 290 +++++++++++ library/axi_ad9152/axi_ad9152_channel.v | 602 +++++++++++++++++++++++ library/axi_ad9152/axi_ad9152_constr.xdc | 9 + library/axi_ad9152/axi_ad9152_core.v | 326 ++++++++++++ library/axi_ad9152/axi_ad9152_if.v | 150 ++++++ library/axi_ad9152/axi_ad9152_ip.tcl | 30 ++ 6 files changed, 1407 insertions(+) create mode 100644 library/axi_ad9152/axi_ad9152.v create mode 100644 library/axi_ad9152/axi_ad9152_channel.v create mode 100644 library/axi_ad9152/axi_ad9152_constr.xdc create mode 100644 library/axi_ad9152/axi_ad9152_core.v create mode 100644 library/axi_ad9152/axi_ad9152_if.v create mode 100644 library/axi_ad9152/axi_ad9152_ip.tcl diff --git a/library/axi_ad9152/axi_ad9152.v b/library/axi_ad9152/axi_ad9152.v new file mode 100644 index 000000000..c6f7426a2 --- /dev/null +++ b/library/axi_ad9152/axi_ad9152.v @@ -0,0 +1,290 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9144 ( + + // jesd interface + // tx_clk is (line-rate/40) + + tx_clk, + tx_data, + + // dma interface + + dac_clk, + dac_valid_0, + dac_enable_0, + dac_ddata_0, + dac_valid_1, + dac_enable_1, + dac_ddata_1, + dac_valid_2, + dac_enable_2, + dac_ddata_2, + dac_valid_3, + dac_enable_3, + dac_ddata_3, + dac_dovf, + dac_dunf, + + // axi interface + + s_axi_aclk, + s_axi_aresetn, + s_axi_awvalid, + s_axi_awaddr, + s_axi_awready, + s_axi_wvalid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wready, + s_axi_bvalid, + s_axi_bresp, + s_axi_bready, + s_axi_arvalid, + s_axi_araddr, + s_axi_arready, + s_axi_rvalid, + s_axi_rdata, + s_axi_rresp, + s_axi_rready); + + // parameters + + parameter PCORE_ID = 0; + parameter PCORE_QUAD_DUAL_N = 1; + parameter PCORE_DAC_DP_DISABLE = 0; + parameter C_S_AXI_MIN_SIZE = 32'hffff; + + // jesd interface + // tx_clk is (line-rate/40) + + input tx_clk; + output [(128*PCORE_QUAD_DUAL_N)+127:0] tx_data; + + // dma interface + + output dac_clk; + output dac_valid_0; + output dac_enable_0; + input [63:0] dac_ddata_0; + output dac_valid_1; + output dac_enable_1; + input [63:0] dac_ddata_1; + output dac_valid_2; + output dac_enable_2; + input [63:0] dac_ddata_2; + output dac_valid_3; + output dac_enable_3; + input [63:0] dac_ddata_3; + input dac_dovf; + input dac_dunf; + + // axi interface + + input s_axi_aclk; + input s_axi_aresetn; + input s_axi_awvalid; + input [ 31:0] s_axi_awaddr; + output s_axi_awready; + input s_axi_wvalid; + input [ 31:0] s_axi_wdata; + input [ 3:0] s_axi_wstrb; + output s_axi_wready; + output s_axi_bvalid; + output [ 1:0] s_axi_bresp; + input s_axi_bready; + input s_axi_arvalid; + input [ 31:0] s_axi_araddr; + output s_axi_arready; + output s_axi_rvalid; + output [ 31:0] s_axi_rdata; + output [ 1:0] s_axi_rresp; + input s_axi_rready; + + // internal clocks and resets + + wire dac_rst; + wire up_clk; + wire up_rstn; + + // internal signals + + wire [255:0] tx_data_s; + wire [ 15:0] dac_data_0_0_s; + wire [ 15:0] dac_data_0_1_s; + wire [ 15:0] dac_data_0_2_s; + wire [ 15:0] dac_data_0_3_s; + wire [ 15:0] dac_data_1_0_s; + wire [ 15:0] dac_data_1_1_s; + wire [ 15:0] dac_data_1_2_s; + wire [ 15:0] dac_data_1_3_s; + wire [ 15:0] dac_data_2_0_s; + wire [ 15:0] dac_data_2_1_s; + wire [ 15:0] dac_data_2_2_s; + wire [ 15:0] dac_data_2_3_s; + wire [ 15:0] dac_data_3_0_s; + wire [ 15:0] dac_data_3_1_s; + wire [ 15:0] dac_data_3_2_s; + wire [ 15:0] dac_data_3_3_s; + wire up_wreq_s; + wire [ 13:0] up_waddr_s; + wire [ 31:0] up_wdata_s; + wire up_wack_s; + wire up_rreq_s; + wire [ 13:0] up_raddr_s; + wire [ 31:0] up_rdata_s; + wire up_rack_s; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // dual/quad cores + + assign tx_data = (PCORE_QUAD_DUAL_N == 1) ? tx_data_s : tx_data_s[127:0]; + + // device interface + + axi_ad9144_if i_if ( + .tx_clk (tx_clk), + .tx_data (tx_data_s), + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_data_0_0 (dac_data_0_0_s), + .dac_data_0_1 (dac_data_0_1_s), + .dac_data_0_2 (dac_data_0_2_s), + .dac_data_0_3 (dac_data_0_3_s), + .dac_data_1_0 (dac_data_1_0_s), + .dac_data_1_1 (dac_data_1_1_s), + .dac_data_1_2 (dac_data_1_2_s), + .dac_data_1_3 (dac_data_1_3_s), + .dac_data_2_0 (dac_data_2_0_s), + .dac_data_2_1 (dac_data_2_1_s), + .dac_data_2_2 (dac_data_2_2_s), + .dac_data_2_3 (dac_data_2_3_s), + .dac_data_3_0 (dac_data_3_0_s), + .dac_data_3_1 (dac_data_3_1_s), + .dac_data_3_2 (dac_data_3_2_s), + .dac_data_3_3 (dac_data_3_3_s)); + + // core + + axi_ad9144_core #(.PCORE_ID(PCORE_ID), .DP_DISABLE(PCORE_DAC_DP_DISABLE)) i_core ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_data_0_0 (dac_data_0_0_s), + .dac_data_0_1 (dac_data_0_1_s), + .dac_data_0_2 (dac_data_0_2_s), + .dac_data_0_3 (dac_data_0_3_s), + .dac_data_1_0 (dac_data_1_0_s), + .dac_data_1_1 (dac_data_1_1_s), + .dac_data_1_2 (dac_data_1_2_s), + .dac_data_1_3 (dac_data_1_3_s), + .dac_data_2_0 (dac_data_2_0_s), + .dac_data_2_1 (dac_data_2_1_s), + .dac_data_2_2 (dac_data_2_2_s), + .dac_data_2_3 (dac_data_2_3_s), + .dac_data_3_0 (dac_data_3_0_s), + .dac_data_3_1 (dac_data_3_1_s), + .dac_data_3_2 (dac_data_3_2_s), + .dac_data_3_3 (dac_data_3_3_s), + .dac_valid_0 (dac_valid_0), + .dac_enable_0 (dac_enable_0), + .dac_ddata_0 (dac_ddata_0), + .dac_valid_1 (dac_valid_1), + .dac_enable_1 (dac_enable_1), + .dac_ddata_1 (dac_ddata_1), + .dac_valid_2 (dac_valid_2), + .dac_enable_2 (dac_enable_2), + .dac_ddata_2 (dac_ddata_2), + .dac_valid_3 (dac_valid_3), + .dac_enable_3 (dac_enable_3), + .dac_ddata_3 (dac_ddata_3), + .dac_dovf (dac_dovf), + .dac_dunf (dac_dunf), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + + // up bus interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9152/axi_ad9152_channel.v b/library/axi_ad9152/axi_ad9152_channel.v new file mode 100644 index 000000000..bddc4fc5a --- /dev/null +++ b/library/axi_ad9152/axi_ad9152_channel.v @@ -0,0 +1,602 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9144_channel ( + + // dac interface + + dac_clk, + dac_rst, + dac_enable, + dac_data, + dma_data, + + // processor interface + + dac_data_sync, + dac_dds_format, + + // bus interface + + up_rstn, + up_clk, + up_wreq, + up_waddr, + up_wdata, + up_wack, + up_rreq, + up_raddr, + up_rdata, + up_rack); + + // parameters + + parameter CHID = 32'h0; + parameter DP_DISABLE = 0; + + // dac interface + + input dac_clk; + input dac_rst; + output dac_enable; + output [63:0] dac_data; + input [63:0] dma_data; + + // processor interface + + input dac_data_sync; + input dac_dds_format; + + // bus interface + + input up_rstn; + input up_clk; + input up_wreq; + input [13:0] up_waddr; + input [31:0] up_wdata; + output up_wack; + input up_rreq; + input [13:0] up_raddr; + output [31:0] up_rdata; + output up_rack; + + // internal registers + + reg dac_enable = 'd0; + reg [63:0] dac_data = 'd0; + reg [63:0] dac_pn7_data = 'd0; + reg [63:0] dac_pn15_data = 'd0; + reg [63:0] dac_pn23_data = 'd0; + reg [63:0] dac_pn31_data = 'd0; + reg [15:0] dac_dds_phase_0_0 = 'd0; + reg [15:0] dac_dds_phase_0_1 = 'd0; + reg [15:0] dac_dds_phase_1_0 = 'd0; + reg [15:0] dac_dds_phase_1_1 = 'd0; + reg [15:0] dac_dds_phase_2_0 = 'd0; + reg [15:0] dac_dds_phase_2_1 = 'd0; + reg [15:0] dac_dds_phase_3_0 = 'd0; + reg [15:0] dac_dds_phase_3_1 = 'd0; + reg [15:0] dac_dds_incr_0 = 'd0; + reg [15:0] dac_dds_incr_1 = 'd0; + reg [63:0] dac_dds_data = 'd0; + + // internal signals + + wire [15:0] dac_dds_data_0_s; + wire [15:0] dac_dds_data_1_s; + wire [15:0] dac_dds_data_2_s; + wire [15:0] dac_dds_data_3_s; + wire [15:0] dac_dds_scale_1_s; + wire [15:0] dac_dds_init_1_s; + wire [15:0] dac_dds_incr_1_s; + wire [15:0] dac_dds_scale_2_s; + wire [15:0] dac_dds_init_2_s; + wire [15:0] dac_dds_incr_2_s; + wire [15:0] dac_pat_data_1_s; + wire [15:0] dac_pat_data_2_s; + wire [ 3:0] dac_data_sel_s; + + // pn7 function + + function [63:0] pn7; + input [63:0] din; + reg [63:0] dout; + begin + dout[63] = din[ 7] ^ din[ 6]; + dout[62] = din[ 6] ^ din[ 5]; + dout[61] = din[ 5] ^ din[ 4]; + dout[60] = din[ 4] ^ din[ 3]; + dout[59] = din[ 3] ^ din[ 2]; + dout[58] = din[ 2] ^ din[ 1]; + dout[57] = din[ 1] ^ din[ 0]; + dout[56] = din[ 0] ^ din[ 7] ^ din[ 6]; + dout[55] = din[ 7] ^ din[ 5]; + dout[54] = din[ 6] ^ din[ 4]; + dout[53] = din[ 5] ^ din[ 3]; + dout[52] = din[ 4] ^ din[ 2]; + dout[51] = din[ 3] ^ din[ 1]; + dout[50] = din[ 2] ^ din[ 0]; + dout[49] = din[ 1] ^ din[ 7] ^ din[ 6]; + dout[48] = din[ 0] ^ din[ 6] ^ din[ 5]; + dout[47] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4]; + dout[46] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3]; + dout[45] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2]; + dout[44] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1]; + dout[43] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0]; + dout[42] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[ 7] ^ din[ 6]; + dout[41] = din[ 1] ^ din[ 7] ^ din[ 0] ^ din[ 5]; + dout[40] = din[ 0] ^ din[ 7] ^ din[ 4]; + dout[39] = din[ 7] ^ din[ 3]; + dout[38] = din[ 6] ^ din[ 2]; + dout[37] = din[ 5] ^ din[ 1]; + dout[36] = din[ 4] ^ din[ 0]; + dout[35] = din[ 3] ^ din[ 7] ^ din[ 6]; + dout[34] = din[ 2] ^ din[ 6] ^ din[ 5]; + dout[33] = din[ 1] ^ din[ 5] ^ din[ 4]; + dout[32] = din[ 0] ^ din[ 4] ^ din[ 3]; + dout[31] = din[ 7] ^ din[ 3] ^ din[ 6] ^ din[ 2]; + dout[30] = din[ 6] ^ din[ 2] ^ din[ 5] ^ din[ 1]; + dout[29] = din[ 5] ^ din[ 1] ^ din[ 4] ^ din[ 0]; + dout[28] = din[ 4] ^ din[ 0] ^ din[ 3] ^ din[ 7] ^ din[ 6]; + dout[27] = din[ 3] ^ din[ 7] ^ din[ 2] ^ din[ 5]; + dout[26] = din[ 2] ^ din[ 6] ^ din[ 1] ^ din[ 4]; + dout[25] = din[ 1] ^ din[ 5] ^ din[ 0] ^ din[ 3]; + dout[24] = din[ 0] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 2]; + dout[23] = din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1]; + dout[22] = din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0]; + dout[21] = din[ 5] ^ din[ 1] ^ din[ 3] ^ din[ 7] ^ din[ 6]; + dout[20] = din[ 4] ^ din[ 0] ^ din[ 6] ^ din[ 2] ^ din[ 5]; + dout[19] = din[ 3] ^ din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 4]; + dout[18] = din[ 2] ^ din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 3]; + dout[17] = din[ 1] ^ din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 2]; + dout[16] = din[ 0] ^ din[ 4] ^ din[ 6] ^ din[ 2] ^ din[ 3] ^ din[ 5] ^ din[ 1]; + dout[15] = din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1] ^ din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0]; + dout[14] = din[ 2] ^ din[ 4] ^ din[ 0] ^ din[ 5] ^ din[ 1] ^ din[ 3] ^ din[ 7]; + dout[13] = din[ 1] ^ din[ 3] ^ din[ 7] ^ din[ 4] ^ din[ 0] ^ din[ 2]; + dout[12] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 7] ^ din[ 1]; + dout[11] = din[ 7] ^ din[ 1] ^ din[ 2] ^ din[ 0]; + dout[10] = din[ 0] ^ din[ 1] ^ din[ 7]; + dout[ 9] = din[ 7] ^ din[ 0]; + dout[ 8] = din[ 7]; + dout[ 7] = din[ 6]; + dout[ 6] = din[ 5]; + dout[ 5] = din[ 4]; + dout[ 4] = din[ 3]; + dout[ 3] = din[ 2]; + dout[ 2] = din[ 1]; + dout[ 1] = din[ 0]; + dout[ 0] = din[ 7] ^ din[ 6]; + pn7 = dout; + end + endfunction + + // pn15 function + + function [63:0] pn15; + input [63:0] din; + reg [63:0] dout; + begin + dout[63] = din[15] ^ din[14]; + dout[62] = din[14] ^ din[13]; + dout[61] = din[13] ^ din[12]; + dout[60] = din[12] ^ din[11]; + dout[59] = din[11] ^ din[10]; + dout[58] = din[10] ^ din[ 9]; + dout[57] = din[ 9] ^ din[ 8]; + dout[56] = din[ 8] ^ din[ 7]; + dout[55] = din[ 7] ^ din[ 6]; + dout[54] = din[ 6] ^ din[ 5]; + dout[53] = din[ 5] ^ din[ 4]; + dout[52] = din[ 4] ^ din[ 3]; + dout[51] = din[ 3] ^ din[ 2]; + dout[50] = din[ 2] ^ din[ 1]; + dout[49] = din[ 1] ^ din[ 0]; + dout[48] = din[ 0] ^ din[15] ^ din[14]; + dout[47] = din[15] ^ din[13]; + dout[46] = din[14] ^ din[12]; + dout[45] = din[13] ^ din[11]; + dout[44] = din[12] ^ din[10]; + dout[43] = din[11] ^ din[ 9]; + dout[42] = din[10] ^ din[ 8]; + dout[41] = din[ 9] ^ din[ 7]; + dout[40] = din[ 8] ^ din[ 6]; + dout[39] = din[ 7] ^ din[ 5]; + dout[38] = din[ 6] ^ din[ 4]; + dout[37] = din[ 5] ^ din[ 3]; + dout[36] = din[ 4] ^ din[ 2]; + dout[35] = din[ 3] ^ din[ 1]; + dout[34] = din[ 2] ^ din[ 0]; + dout[33] = din[ 1] ^ din[15] ^ din[14]; + dout[32] = din[ 0] ^ din[14] ^ din[13]; + dout[31] = din[15] ^ din[13] ^ din[14] ^ din[12]; + dout[30] = din[14] ^ din[12] ^ din[13] ^ din[11]; + dout[29] = din[13] ^ din[11] ^ din[12] ^ din[10]; + dout[28] = din[12] ^ din[10] ^ din[11] ^ din[ 9]; + dout[27] = din[11] ^ din[ 9] ^ din[10] ^ din[ 8]; + dout[26] = din[10] ^ din[ 8] ^ din[ 9] ^ din[ 7]; + dout[25] = din[ 9] ^ din[ 7] ^ din[ 8] ^ din[ 6]; + dout[24] = din[ 8] ^ din[ 6] ^ din[ 7] ^ din[ 5]; + dout[23] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4]; + dout[22] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3]; + dout[21] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2]; + dout[20] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1]; + dout[19] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0]; + dout[18] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[15] ^ din[14]; + dout[17] = din[ 1] ^ din[15] ^ din[ 0] ^ din[13]; + dout[16] = din[ 0] ^ din[15] ^ din[12]; + dout[15] = din[15] ^ din[11]; + dout[14] = din[14] ^ din[10]; + dout[13] = din[13] ^ din[ 9]; + dout[12] = din[12] ^ din[ 8]; + dout[11] = din[11] ^ din[ 7]; + dout[10] = din[10] ^ din[ 6]; + dout[ 9] = din[ 9] ^ din[ 5]; + dout[ 8] = din[ 8] ^ din[ 4]; + dout[ 7] = din[ 7] ^ din[ 3]; + dout[ 6] = din[ 6] ^ din[ 2]; + dout[ 5] = din[ 5] ^ din[ 1]; + dout[ 4] = din[ 4] ^ din[ 0]; + dout[ 3] = din[ 3] ^ din[15] ^ din[14]; + dout[ 2] = din[ 2] ^ din[14] ^ din[13]; + dout[ 1] = din[ 1] ^ din[13] ^ din[12]; + dout[ 0] = din[ 0] ^ din[12] ^ din[11]; + pn15 = dout; + end + endfunction + + // pn23 function + + function [63:0] pn23; + input [63:0] din; + reg [63:0] dout; + begin + dout[63] = din[23] ^ din[18]; + dout[62] = din[22] ^ din[17]; + dout[61] = din[21] ^ din[16]; + dout[60] = din[20] ^ din[15]; + dout[59] = din[19] ^ din[14]; + dout[58] = din[18] ^ din[13]; + dout[57] = din[17] ^ din[12]; + dout[56] = din[16] ^ din[11]; + dout[55] = din[15] ^ din[10]; + dout[54] = din[14] ^ din[ 9]; + dout[53] = din[13] ^ din[ 8]; + dout[52] = din[12] ^ din[ 7]; + dout[51] = din[11] ^ din[ 6]; + dout[50] = din[10] ^ din[ 5]; + dout[49] = din[ 9] ^ din[ 4]; + dout[48] = din[ 8] ^ din[ 3]; + dout[47] = din[ 7] ^ din[ 2]; + dout[46] = din[ 6] ^ din[ 1]; + dout[45] = din[ 5] ^ din[ 0]; + dout[44] = din[ 4] ^ din[23] ^ din[18]; + dout[43] = din[ 3] ^ din[22] ^ din[17]; + dout[42] = din[ 2] ^ din[21] ^ din[16]; + dout[41] = din[ 1] ^ din[20] ^ din[15]; + dout[40] = din[ 0] ^ din[19] ^ din[14]; + dout[39] = din[23] ^ din[13]; + dout[38] = din[22] ^ din[12]; + dout[37] = din[21] ^ din[11]; + dout[36] = din[20] ^ din[10]; + dout[35] = din[19] ^ din[ 9]; + dout[34] = din[18] ^ din[ 8]; + dout[33] = din[17] ^ din[ 7]; + dout[32] = din[16] ^ din[ 6]; + dout[31] = din[15] ^ din[ 5]; + dout[30] = din[14] ^ din[ 4]; + dout[29] = din[13] ^ din[ 3]; + dout[28] = din[12] ^ din[ 2]; + dout[27] = din[11] ^ din[ 1]; + dout[26] = din[10] ^ din[ 0]; + dout[25] = din[ 9] ^ din[23] ^ din[18]; + dout[24] = din[ 8] ^ din[22] ^ din[17]; + dout[23] = din[ 7] ^ din[21] ^ din[16]; + dout[22] = din[ 6] ^ din[20] ^ din[15]; + dout[21] = din[ 5] ^ din[19] ^ din[14]; + dout[20] = din[ 4] ^ din[18] ^ din[13]; + dout[19] = din[ 3] ^ din[17] ^ din[12]; + dout[18] = din[ 2] ^ din[16] ^ din[11]; + dout[17] = din[ 1] ^ din[15] ^ din[10]; + dout[16] = din[ 0] ^ din[14] ^ din[ 9]; + dout[15] = din[23] ^ din[13] ^ din[18] ^ din[ 8]; + dout[14] = din[22] ^ din[12] ^ din[17] ^ din[ 7]; + dout[13] = din[21] ^ din[11] ^ din[16] ^ din[ 6]; + dout[12] = din[20] ^ din[10] ^ din[15] ^ din[ 5]; + dout[11] = din[19] ^ din[ 9] ^ din[14] ^ din[ 4]; + dout[10] = din[18] ^ din[ 8] ^ din[13] ^ din[ 3]; + dout[ 9] = din[17] ^ din[ 7] ^ din[12] ^ din[ 2]; + dout[ 8] = din[16] ^ din[ 6] ^ din[11] ^ din[ 1]; + dout[ 7] = din[15] ^ din[ 5] ^ din[10] ^ din[ 0]; + dout[ 6] = din[14] ^ din[ 4] ^ din[ 9] ^ din[23] ^ din[18]; + dout[ 5] = din[13] ^ din[ 3] ^ din[ 8] ^ din[22] ^ din[17]; + dout[ 4] = din[12] ^ din[ 2] ^ din[ 7] ^ din[21] ^ din[16]; + dout[ 3] = din[11] ^ din[ 1] ^ din[ 6] ^ din[20] ^ din[15]; + dout[ 2] = din[10] ^ din[ 0] ^ din[ 5] ^ din[19] ^ din[14]; + dout[ 1] = din[ 9] ^ din[23] ^ din[ 4] ^ din[13]; + dout[ 0] = din[ 8] ^ din[22] ^ din[ 3] ^ din[12]; + pn23 = dout; + end + endfunction + + // pn31 function + + function [63:0] pn31; + input [63:0] din; + reg [63:0] dout; + begin + dout[63] = din[31] ^ din[28]; + dout[62] = din[30] ^ din[27]; + dout[61] = din[29] ^ din[26]; + dout[60] = din[28] ^ din[25]; + dout[59] = din[27] ^ din[24]; + dout[58] = din[26] ^ din[23]; + dout[57] = din[25] ^ din[22]; + dout[56] = din[24] ^ din[21]; + dout[55] = din[23] ^ din[20]; + dout[54] = din[22] ^ din[19]; + dout[53] = din[21] ^ din[18]; + dout[52] = din[20] ^ din[17]; + dout[51] = din[19] ^ din[16]; + dout[50] = din[18] ^ din[15]; + dout[49] = din[17] ^ din[14]; + dout[48] = din[16] ^ din[13]; + dout[47] = din[15] ^ din[12]; + dout[46] = din[14] ^ din[11]; + dout[45] = din[13] ^ din[10]; + dout[44] = din[12] ^ din[ 9]; + dout[43] = din[11] ^ din[ 8]; + dout[42] = din[10] ^ din[ 7]; + dout[41] = din[ 9] ^ din[ 6]; + dout[40] = din[ 8] ^ din[ 5]; + dout[39] = din[ 7] ^ din[ 4]; + dout[38] = din[ 6] ^ din[ 3]; + dout[37] = din[ 5] ^ din[ 2]; + dout[36] = din[ 4] ^ din[ 1]; + dout[35] = din[ 3] ^ din[ 0]; + dout[34] = din[ 2] ^ din[31] ^ din[28]; + dout[33] = din[ 1] ^ din[30] ^ din[27]; + dout[32] = din[ 0] ^ din[29] ^ din[26]; + dout[31] = din[31] ^ din[25]; + dout[30] = din[30] ^ din[24]; + dout[29] = din[29] ^ din[23]; + dout[28] = din[28] ^ din[22]; + dout[27] = din[27] ^ din[21]; + dout[26] = din[26] ^ din[20]; + dout[25] = din[25] ^ din[19]; + dout[24] = din[24] ^ din[18]; + dout[23] = din[23] ^ din[17]; + dout[22] = din[22] ^ din[16]; + dout[21] = din[21] ^ din[15]; + dout[20] = din[20] ^ din[14]; + dout[19] = din[19] ^ din[13]; + dout[18] = din[18] ^ din[12]; + dout[17] = din[17] ^ din[11]; + dout[16] = din[16] ^ din[10]; + dout[15] = din[15] ^ din[ 9]; + dout[14] = din[14] ^ din[ 8]; + dout[13] = din[13] ^ din[ 7]; + dout[12] = din[12] ^ din[ 6]; + dout[11] = din[11] ^ din[ 5]; + dout[10] = din[10] ^ din[ 4]; + dout[ 9] = din[ 9] ^ din[ 3]; + dout[ 8] = din[ 8] ^ din[ 2]; + dout[ 7] = din[ 7] ^ din[ 1]; + dout[ 6] = din[ 6] ^ din[ 0]; + dout[ 5] = din[ 5] ^ din[31] ^ din[28]; + dout[ 4] = din[ 4] ^ din[30] ^ din[27]; + dout[ 3] = din[ 3] ^ din[29] ^ din[26]; + dout[ 2] = din[ 2] ^ din[28] ^ din[25]; + dout[ 1] = din[ 1] ^ din[27] ^ din[24]; + dout[ 0] = din[ 0] ^ din[26] ^ din[23]; + pn31 = dout; + end + endfunction + + // dac data select + + always @(posedge dac_clk) begin + dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0; + case (dac_data_sel_s) + 4'h7: dac_data <= dac_pn31_data; + 4'h6: dac_data <= dac_pn23_data; + 4'h5: dac_data <= dac_pn15_data; + 4'h4: dac_data <= dac_pn7_data; + 4'h3: dac_data <= 64'd0; + 4'h2: dac_data <= dma_data; + 4'h1: dac_data <= { dac_pat_data_2_s, dac_pat_data_1_s, + dac_pat_data_2_s, dac_pat_data_1_s}; + default: dac_data <= dac_dds_data; + endcase + end + + // pn registers + + always @(posedge dac_clk) begin + if (dac_data_sync == 1'b1) begin + dac_pn7_data <= {64{1'd1}}; + dac_pn15_data <= {64{1'd1}}; + dac_pn23_data <= {64{1'd1}}; + dac_pn31_data <= {64{1'd1}}; + end else begin + dac_pn7_data <= pn7(dac_pn7_data); + dac_pn15_data <= pn15(dac_pn15_data); + dac_pn23_data <= pn23(dac_pn23_data); + dac_pn31_data <= pn31(dac_pn31_data); + end + end + + // dds + + always @(posedge dac_clk) begin + if (dac_data_sync == 1'b1) begin + dac_dds_phase_0_0 <= dac_dds_init_1_s; + dac_dds_phase_0_1 <= dac_dds_init_2_s; + dac_dds_phase_1_0 <= dac_dds_phase_0_0 + dac_dds_incr_1_s; + dac_dds_phase_1_1 <= dac_dds_phase_0_1 + dac_dds_incr_2_s; + dac_dds_phase_2_0 <= dac_dds_phase_1_0 + dac_dds_incr_1_s; + dac_dds_phase_2_1 <= dac_dds_phase_1_1 + dac_dds_incr_2_s; + dac_dds_phase_3_0 <= dac_dds_phase_2_0 + dac_dds_incr_1_s; + dac_dds_phase_3_1 <= dac_dds_phase_2_1 + dac_dds_incr_2_s; + dac_dds_incr_0 <= {dac_dds_incr_1_s[13:0], 2'd0}; + dac_dds_incr_1 <= {dac_dds_incr_2_s[13:0], 2'd0}; + dac_dds_data <= 64'd0; + end else begin + dac_dds_phase_0_0 <= dac_dds_phase_0_0 + dac_dds_incr_0; + dac_dds_phase_0_1 <= dac_dds_phase_0_1 + dac_dds_incr_1; + dac_dds_phase_1_0 <= dac_dds_phase_1_0 + dac_dds_incr_0; + dac_dds_phase_1_1 <= dac_dds_phase_1_1 + dac_dds_incr_1; + dac_dds_phase_2_0 <= dac_dds_phase_2_0 + dac_dds_incr_0; + dac_dds_phase_2_1 <= dac_dds_phase_2_1 + dac_dds_incr_1; + dac_dds_phase_3_0 <= dac_dds_phase_3_0 + dac_dds_incr_0; + dac_dds_phase_3_1 <= dac_dds_phase_3_1 + dac_dds_incr_1; + dac_dds_incr_0 <= dac_dds_incr_0; + dac_dds_incr_1 <= dac_dds_incr_1; + dac_dds_data <= { dac_dds_data_3_s, dac_dds_data_2_s, + dac_dds_data_1_s, dac_dds_data_0_s}; + end + end + + generate + if (DP_DISABLE == 1) begin + assign dac_dds_data_0_s = 16'd0; + end else begin + ad_dds i_dds_0 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_0_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_0_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_0_s)); + end + endgenerate + + generate + if (DP_DISABLE == 1) begin + assign dac_dds_data_1_s = 16'd0; + end else begin + ad_dds i_dds_1 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_1_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_1_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_1_s)); + end + endgenerate + + generate + if (DP_DISABLE == 1) begin + assign dac_dds_data_2_s = 16'd0; + end else begin + ad_dds i_dds_2 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_2_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_2_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_2_s)); + end + endgenerate + + generate + if (DP_DISABLE == 1) begin + assign dac_dds_data_3_s = 16'd0; + end else begin + ad_dds i_dds_3 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_3_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_3_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_3_s)); + end + endgenerate + + // single channel processor + + up_dac_channel #(.PCORE_DAC_CHID(CHID)) i_up_dac_channel ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_dds_scale_1 (dac_dds_scale_1_s), + .dac_dds_init_1 (dac_dds_init_1_s), + .dac_dds_incr_1 (dac_dds_incr_1_s), + .dac_dds_scale_2 (dac_dds_scale_2_s), + .dac_dds_init_2 (dac_dds_init_2_s), + .dac_dds_incr_2 (dac_dds_incr_2_s), + .dac_pat_data_1 (dac_pat_data_1_s), + .dac_pat_data_2 (dac_pat_data_2_s), + .dac_data_sel (dac_data_sel_s), + .dac_iqcor_enb (), + .dac_iqcor_coeff_1 (), + .dac_iqcor_coeff_2 (), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_interpolation_m (), + .up_usr_interpolation_n (), + .dac_usr_datatype_be (1'b0), + .dac_usr_datatype_signed (1'b1), + .dac_usr_datatype_shift (8'd0), + .dac_usr_datatype_total_bits (8'd16), + .dac_usr_datatype_bits (8'd16), + .dac_usr_interpolation_m (16'd1), + .dac_usr_interpolation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9152/axi_ad9152_constr.xdc b/library/axi_ad9152/axi_ad9152_constr.xdc new file mode 100644 index 000000000..5b2d31978 --- /dev/null +++ b/library/axi_ad9152/axi_ad9152_constr.xdc @@ -0,0 +1,9 @@ + +create_clock -period [expr 1000/250] -name tx_clk [get_ports tx_clk] +create_clock -period [expr 1000/100] -name s_axi_aclk [get_ports s_axi_aclk] + +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports tx_clk]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]] + + + diff --git a/library/axi_ad9152/axi_ad9152_core.v b/library/axi_ad9152/axi_ad9152_core.v new file mode 100644 index 000000000..1c3e4a838 --- /dev/null +++ b/library/axi_ad9152/axi_ad9152_core.v @@ -0,0 +1,326 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9144_core ( + + // dac interface + + dac_clk, + dac_rst, + dac_data_0_0, + dac_data_0_1, + dac_data_0_2, + dac_data_0_3, + dac_data_1_0, + dac_data_1_1, + dac_data_1_2, + dac_data_1_3, + dac_data_2_0, + dac_data_2_1, + dac_data_2_2, + dac_data_2_3, + dac_data_3_0, + dac_data_3_1, + dac_data_3_2, + dac_data_3_3, + + // dma interface + + dac_valid_0, + dac_enable_0, + dac_ddata_0, + dac_valid_1, + dac_enable_1, + dac_ddata_1, + dac_valid_2, + dac_enable_2, + dac_ddata_2, + dac_valid_3, + dac_enable_3, + dac_ddata_3, + dac_dovf, + dac_dunf, + + // processor interface + + up_rstn, + up_clk, + up_wreq, + up_waddr, + up_wdata, + up_wack, + up_rreq, + up_raddr, + up_rdata, + up_rack); + + // parameters + + parameter PCORE_ID = 0; + parameter DP_DISABLE = 0; + + // dac interface + + input dac_clk; + output dac_rst; + output [15:0] dac_data_0_0; + output [15:0] dac_data_0_1; + output [15:0] dac_data_0_2; + output [15:0] dac_data_0_3; + output [15:0] dac_data_1_0; + output [15:0] dac_data_1_1; + output [15:0] dac_data_1_2; + output [15:0] dac_data_1_3; + output [15:0] dac_data_2_0; + output [15:0] dac_data_2_1; + output [15:0] dac_data_2_2; + output [15:0] dac_data_2_3; + output [15:0] dac_data_3_0; + output [15:0] dac_data_3_1; + output [15:0] dac_data_3_2; + output [15:0] dac_data_3_3; + + // dma interface + + output dac_valid_0; + output dac_enable_0; + input [63:0] dac_ddata_0; + output dac_valid_1; + output dac_enable_1; + input [63:0] dac_ddata_1; + output dac_valid_2; + output dac_enable_2; + input [63:0] dac_ddata_2; + output dac_valid_3; + output dac_enable_3; + input [63:0] dac_ddata_3; + input dac_dovf; + input dac_dunf; + + // processor interface + + input up_rstn; + input up_clk; + input up_wreq; + input [13:0] up_waddr; + input [31:0] up_wdata; + output up_wack; + input up_rreq; + input [13:0] up_raddr; + output [31:0] up_rdata; + output up_rack; + + // internal registers + + reg [31:0] up_rdata = 'd0; + reg up_rack = 'd0; + reg up_wack = 'd0; + + // internal signals + + wire dac_sync_s; + wire dac_datafmt_s; + wire [31:0] up_rdata_0_s; + wire up_rack_0_s; + wire up_wack_0_s; + wire [31:0] up_rdata_1_s; + wire up_rack_1_s; + wire up_wack_1_s; + wire [31:0] up_rdata_2_s; + wire up_rack_2_s; + wire up_wack_2_s; + wire [31:0] up_rdata_3_s; + wire up_rack_3_s; + wire up_wack_3_s; + wire [31:0] up_rdata_s; + wire up_rack_s; + wire up_wack_s; + + // dac valid + + assign dac_valid_0 = 1'b1; + assign dac_valid_1 = 1'b1; + assign dac_valid_2 = 1'b1; + assign dac_valid_3 = 1'b1; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_rdata <= up_rdata_s | up_rdata_0_s | up_rdata_1_s | up_rdata_2_s | up_rdata_3_s; + up_rack <= up_rack_s | up_rack_0_s | up_rack_1_s | up_rack_2_s | up_rack_3_s; + up_wack <= up_wack_s | up_wack_0_s | up_wack_1_s | up_wack_2_s | up_wack_3_s; + end + end + + // dac channel + + axi_ad9144_channel #(.CHID(0), .DP_DISABLE(DP_DISABLE)) i_channel_0 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_enable (dac_enable_0), + .dac_data ({dac_data_0_3, dac_data_0_2, dac_data_0_1, dac_data_0_0}), + .dma_data (dac_ddata_0), + .dac_data_sync (dac_sync_s), + .dac_dds_format (dac_datafmt_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_0_s), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_0_s), + .up_rack (up_rack_0_s)); + + // dac channel + + axi_ad9144_channel #(.CHID(1), .DP_DISABLE(DP_DISABLE)) i_channel_1 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_enable (dac_enable_1), + .dac_data ({dac_data_1_3, dac_data_1_2, dac_data_1_1, dac_data_1_0}), + .dma_data (dac_ddata_1), + .dac_data_sync (dac_sync_s), + .dac_dds_format (dac_datafmt_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_1_s), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_1_s), + .up_rack (up_rack_1_s)); + + // dac channel + + axi_ad9144_channel #(.CHID(2), .DP_DISABLE(DP_DISABLE)) i_channel_2 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_enable (dac_enable_2), + .dac_data ({dac_data_2_3, dac_data_2_2, dac_data_2_1, dac_data_2_0}), + .dma_data (dac_ddata_2), + .dac_data_sync (dac_sync_s), + .dac_dds_format (dac_datafmt_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_2_s), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_2_s), + .up_rack (up_rack_2_s)); + + // dac channel + + axi_ad9144_channel #(.CHID(3), .DP_DISABLE(DP_DISABLE)) i_channel_3 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_enable (dac_enable_3), + .dac_data ({dac_data_3_3, dac_data_3_2, dac_data_3_1, dac_data_3_0}), + .dma_data (dac_ddata_3), + .dac_data_sync (dac_sync_s), + .dac_dds_format (dac_datafmt_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_3_s), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_3_s), + .up_rack (up_rack_3_s)); + + // dac common processor interface + + up_dac_common #(.PCORE_ID(PCORE_ID)) i_up_dac_common ( + .mmcm_rst (), + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_sync (dac_sync_s), + .dac_frame (), + .dac_par_type (), + .dac_par_enb (), + .dac_r1_mode (), + .dac_datafmt (dac_datafmt_s), + .dac_datarate (), + .dac_status (1'b1), + .dac_status_ovf (dac_dovf), + .dac_status_unf (dac_dunf), + .dac_clk_ratio (32'd40), + .drp_clk (up_clk), + .drp_rst (), + .drp_sel (), + .drp_wr (), + .drp_addr (), + .drp_wdata (), + .drp_rdata (16'd0), + .drp_ready (1'd0), + .drp_locked (1'd1), + .up_usr_chanmax (), + .dac_usr_chanmax (8'd3), + .up_dac_gpio_in (32'd0), + .up_dac_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9152/axi_ad9152_if.v b/library/axi_ad9152/axi_ad9152_if.v new file mode 100644 index 000000000..9f7015019 --- /dev/null +++ b/library/axi_ad9152/axi_ad9152_if.v @@ -0,0 +1,150 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// This is the dac physical interface (drives samples from the low speed clock to the +// dac clock domain. + +`timescale 1ns/100ps + +module axi_ad9144_if ( + + // jesd interface + // tx_clk is (line-rate/40) + + tx_clk, + tx_data, + + // dac interface + + dac_clk, + dac_rst, + dac_data_0_0, + dac_data_0_1, + dac_data_0_2, + dac_data_0_3, + dac_data_1_0, + dac_data_1_1, + dac_data_1_2, + dac_data_1_3, + dac_data_2_0, + dac_data_2_1, + dac_data_2_2, + dac_data_2_3, + dac_data_3_0, + dac_data_3_1, + dac_data_3_2, + dac_data_3_3); + + // jesd interface + // tx_clk is (line-rate/40) + + input tx_clk; + output [255:0] tx_data; + + // dac interface + + output dac_clk; + input dac_rst; + input [15:0] dac_data_0_0; + input [15:0] dac_data_0_1; + input [15:0] dac_data_0_2; + input [15:0] dac_data_0_3; + input [15:0] dac_data_1_0; + input [15:0] dac_data_1_1; + input [15:0] dac_data_1_2; + input [15:0] dac_data_1_3; + input [15:0] dac_data_2_0; + input [15:0] dac_data_2_1; + input [15:0] dac_data_2_2; + input [15:0] dac_data_2_3; + input [15:0] dac_data_3_0; + input [15:0] dac_data_3_1; + input [15:0] dac_data_3_2; + input [15:0] dac_data_3_3; + + // internal registers + + reg [255:0] tx_data = 'd0; + + // reorder data for the jesd links + + assign dac_clk = tx_clk; + + always @(posedge dac_clk) begin + if (dac_rst == 1'b1) begin + tx_data <= 256'd0; + end else begin + tx_data[255:248] <= dac_data_3_3[ 7: 0]; + tx_data[247:240] <= dac_data_3_2[ 7: 0]; + tx_data[239:232] <= dac_data_3_1[ 7: 0]; + tx_data[231:224] <= dac_data_3_0[ 7: 0]; + tx_data[223:216] <= dac_data_3_3[15: 8]; + tx_data[215:208] <= dac_data_3_2[15: 8]; + tx_data[207:200] <= dac_data_3_1[15: 8]; + tx_data[199:192] <= dac_data_3_0[15: 8]; + tx_data[191:184] <= dac_data_2_3[ 7: 0]; + tx_data[183:176] <= dac_data_2_2[ 7: 0]; + tx_data[175:168] <= dac_data_2_1[ 7: 0]; + tx_data[167:160] <= dac_data_2_0[ 7: 0]; + tx_data[159:152] <= dac_data_2_3[15: 8]; + tx_data[151:144] <= dac_data_2_2[15: 8]; + tx_data[143:136] <= dac_data_2_1[15: 8]; + tx_data[135:128] <= dac_data_2_0[15: 8]; + tx_data[127:120] <= dac_data_1_3[ 7: 0]; + tx_data[119:112] <= dac_data_1_2[ 7: 0]; + tx_data[111:104] <= dac_data_1_1[ 7: 0]; + tx_data[103: 96] <= dac_data_1_0[ 7: 0]; + tx_data[ 95: 88] <= dac_data_1_3[15: 8]; + tx_data[ 87: 80] <= dac_data_1_2[15: 8]; + tx_data[ 79: 72] <= dac_data_1_1[15: 8]; + tx_data[ 71: 64] <= dac_data_1_0[15: 8]; + tx_data[ 63: 56] <= dac_data_0_3[ 7: 0]; + tx_data[ 55: 48] <= dac_data_0_2[ 7: 0]; + tx_data[ 47: 40] <= dac_data_0_1[ 7: 0]; + tx_data[ 39: 32] <= dac_data_0_0[ 7: 0]; + tx_data[ 31: 24] <= dac_data_0_3[15: 8]; + tx_data[ 23: 16] <= dac_data_0_2[15: 8]; + tx_data[ 15: 8] <= dac_data_0_1[15: 8]; + tx_data[ 7: 0] <= dac_data_0_0[15: 8]; + end + end + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9152/axi_ad9152_ip.tcl b/library/axi_ad9152/axi_ad9152_ip.tcl new file mode 100644 index 000000000..715eb8a72 --- /dev/null +++ b/library/axi_ad9152/axi_ad9152_ip.tcl @@ -0,0 +1,30 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_ad9144 +adi_ip_files axi_ad9144 [list \ + "$ad_hdl_dir/library/common/ad_mul.v" \ + "$ad_hdl_dir/library/common/ad_dds_sine.v" \ + "$ad_hdl_dir/library/common/ad_dds_1.v" \ + "$ad_hdl_dir/library/common/ad_dds.v" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_drp_cntrl.v" \ + "$ad_hdl_dir/library/common/up_dac_common.v" \ + "$ad_hdl_dir/library/common/up_dac_channel.v" \ + "axi_ad9144_channel.v" \ + "axi_ad9144_core.v" \ + "axi_ad9144_if.v" \ + "axi_ad9144.v" ] + +adi_ip_properties axi_ad9144 +adi_ip_constraints axi_ad9144 [list \ + "axi_ad9144_constr.xdc" ] + +ipx::save_core [ipx::current_core] +