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SPI Engine: edge-based trigger 

Previous level-based trigger could cause issues in some low
sampling rate setups. This commit changes it to edge-based.

Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
main
Laez Barbosa 2024-01-12 11:10:18 -03:00 committed by LBFFilho
parent b45e7a7313
commit d45be68ac4
1 changed files with 15 additions and 2 deletions
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17
library/spi_engine/spi_engine_offload/spi_engine_offload.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -96,9 +96,12 @@ module spi_engine_offload #(
reg [15:0] cmd_mem[0:2**CMD_MEM_ADDRESS_WIDTH-1];
reg [(DATA_WIDTH-1):0] sdo_mem[0:2**SDO_MEM_ADDRESS_WIDTH-1];
reg trigger_last_reg;
wire [15:0] cmd_int_s;
wire [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr_next;
wire spi_enable;
wire trigger_posedge;
assign cmd_valid = spi_active;
assign sdo_data_valid = spi_active;
@ -246,6 +249,16 @@ module spi_engine_offload #(
.out_resetn(1'b1),
.out_bits(trigger_s));
always @(posedge spi_clk) begin
if (!spi_resetn) begin
trigger_last_reg <= 1'b0;
end else begin
trigger_last_reg <= trigger_s;
end
end
assign trigger_posedge = trigger_s && !trigger_last_reg;
always @(posedge spi_clk) begin
if (spi_resetn == 1'b0) begin
spi_active <= 1'b0;
@ -253,7 +266,7 @@ module spi_engine_offload #(
if (spi_active == 1'b0) begin
// start offload when we have a valid trigger, offload is enabled and
// the DMA is enabled
if (trigger_s == 1'b1 && spi_enable == 1'b1 && offload_sdi_ready == 1'b1)
if (trigger_posedge == 1'b1 && spi_enable == 1'b1 && offload_sdi_ready == 1'b1)
spi_active <= 1'b1;
end else if (cmd_ready == 1'b1 && spi_cmd_rd_addr_next == ctrl_cmd_wr_addr) begin
spi_active <= 1'b0;