axi_laser_driver: TIA's are controlled individually in manual mode
Update the sequencer, so the TIA channel selection can be controlled separately for each TIA, when the sequencer runs in manual mode.main
parent
ea158ee42b
commit
d43e6ee239
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@ -72,7 +72,7 @@ module axi_laser_driver #(
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output driver_pulse,
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output driver_pulse,
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input driver_otw_n,
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input driver_otw_n,
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output driver_dp_reset,
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output driver_dp_reset,
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output reg [ 1:0] tia_chsel,
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output reg [ 7:0] tia_chsel,
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// interrupt
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// interrupt
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@ -116,7 +116,7 @@ module axi_laser_driver #(
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wire [ 1:0] auto_seq1_s;
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wire [ 1:0] auto_seq1_s;
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wire [ 1:0] auto_seq2_s;
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wire [ 1:0] auto_seq2_s;
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wire [ 1:0] auto_seq3_s;
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wire [ 1:0] auto_seq3_s;
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wire [ 1:0] manual_select_s;
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wire [ 7:0] manual_select_s;
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// local parameters
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// local parameters
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@ -247,16 +247,16 @@ module axi_laser_driver #(
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (sequence_en_s == 1'b0) begin
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if (sequence_en_s == 1'b0) begin
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tia_chsel <= 2'b0;
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tia_chsel <= 8'h00;
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end else begin
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end else begin
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if (pulse_counter_s == sequence_offset_s) begin
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if (pulse_counter_s == sequence_offset_s) begin
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if (auto_sequence_s) begin
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if (auto_sequence_s) begin
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case (sequence_counter)
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case (sequence_counter)
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2'b00 : tia_chsel <= auto_seq0_s;
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2'b00 : tia_chsel <= {auto_seq0_s, auto_seq0_s, auto_seq0_s, auto_seq0_s};
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2'b01 : tia_chsel <= auto_seq1_s;
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2'b01 : tia_chsel <= {auto_seq1_s, auto_seq1_s, auto_seq1_s, auto_seq1_s};
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2'b10 : tia_chsel <= auto_seq2_s;
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2'b10 : tia_chsel <= {auto_seq2_s, auto_seq2_s, auto_seq2_s, auto_seq2_s};
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2'b11 : tia_chsel <= auto_seq3_s;
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2'b11 : tia_chsel <= {auto_seq3_s, auto_seq3_s, auto_seq3_s, auto_seq3_s};
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default : tia_chsel <= 2'b00;
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default : tia_chsel <= 8'h00;
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endcase
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endcase
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end else begin
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end else begin
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tia_chsel <= manual_select_s;
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tia_chsel <= manual_select_s;
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@ -61,7 +61,7 @@ module axi_laser_driver_regmap #(
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output [ 1:0] auto_seq2,
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output [ 1:0] auto_seq2,
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output [ 1:0] auto_seq3,
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output [ 1:0] auto_seq3,
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output [ 1:0] manual_select,
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output [ 7:0] manual_select,
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// processor interface
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// processor interface
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@ -91,7 +91,7 @@ module axi_laser_driver_regmap #(
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reg [ 1:0] up_auto_seq1 = 2'b01;
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reg [ 1:0] up_auto_seq1 = 2'b01;
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reg [ 1:0] up_auto_seq2 = 2'b10;
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reg [ 1:0] up_auto_seq2 = 2'b10;
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reg [ 1:0] up_auto_seq3 = 2'b11;
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reg [ 1:0] up_auto_seq3 = 2'b11;
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reg [ 1:0] up_manual_select = 2'b00;
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reg [ 7:0] up_manual_select = 8'h00;
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// internal signals
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// internal signals
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@ -122,7 +122,7 @@ module axi_laser_driver_regmap #(
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up_auto_seq1 <= 2'b01;
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up_auto_seq1 <= 2'b01;
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up_auto_seq2 <= 2'b10;
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up_auto_seq2 <= 2'b10;
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up_auto_seq3 <= 2'b11;
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up_auto_seq3 <= 2'b11;
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up_manual_select <= 2'b00;
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up_manual_select <= 8'h00;
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end else begin
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end else begin
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up_wack <= up_wreq_int_s;
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up_wack <= up_wreq_int_s;
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if ((up_wreq_int_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
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if ((up_wreq_int_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
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@ -145,7 +145,10 @@ module axi_laser_driver_regmap #(
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up_auto_seq3 <= up_wdata[13:12];
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up_auto_seq3 <= up_wdata[13:12];
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end
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end
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if ((up_wreq_int_s == 1'b1) && (up_waddr[3:0] == 4'hE)) begin
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if ((up_wreq_int_s == 1'b1) && (up_waddr[3:0] == 4'hE)) begin
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up_sequence_offset <= up_wdata[1:0];
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up_manual_select <= {up_wdata[13:12],
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up_wdata[9:8],
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up_wdata[5:4],
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up_wdata[1:0]};
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end
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end
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end
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end
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end
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end
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@ -166,8 +169,14 @@ module axi_laser_driver_regmap #(
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5'h0A: up_rdata <= {29'h0, up_irq_pending_s};
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5'h0A: up_rdata <= {29'h0, up_irq_pending_s};
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5'h0B: up_rdata <= {30'h0, up_auto_sequence, up_sequence_en};
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5'h0B: up_rdata <= {30'h0, up_auto_sequence, up_sequence_en};
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5'h0C: up_rdata <= up_sequence_offset;
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5'h0C: up_rdata <= up_sequence_offset;
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5'h0D: up_rdata <= {16'h0, up_auto_seq3, 2'b0, up_auto_seq2, 2'b0, up_auto_seq1, 2'b0, up_auto_seq0};
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5'h0D: up_rdata <= {18'h0, up_auto_seq3,
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5'h0E: up_rdata <= {30'h0, up_manual_select};
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2'h0, up_auto_seq2,
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2'h0, up_auto_seq1,
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2'h0, up_auto_seq0};
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5'h0E: up_rdata <= {18'h0, up_manual_select[7:6],
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2'h0, up_manual_select[5:4],
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2'h0, up_manual_select[3:2],
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2'h0, up_manual_select[1:0]};
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default: up_rdata <= 0;
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default: up_rdata <= 0;
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endcase
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endcase
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@ -240,7 +249,7 @@ module axi_laser_driver_regmap #(
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.out_bits ({auto_sequence, sequence_en}));
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.out_bits ({auto_sequence, sequence_en}));
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sync_bits #(
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sync_bits #(
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.NUM_OF_BITS (10),
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.NUM_OF_BITS (16),
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.ASYNC_CLK (1))
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.ASYNC_CLK (1))
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i_sequencer_sync (
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i_sequencer_sync (
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.in_bits ({up_auto_seq3,
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.in_bits ({up_auto_seq3,
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@ -21,7 +21,7 @@ create_bd_port -dir I spi_afe_adc_sdi_i
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create_bd_port -dir O laser_driver
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create_bd_port -dir O laser_driver
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create_bd_port -dir O laser_driver_en_n
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create_bd_port -dir O laser_driver_en_n
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create_bd_port -dir I laser_driver_otw_n
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create_bd_port -dir I laser_driver_otw_n
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create_bd_port -dir O -from 1 -to 0 tia_chsel
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create_bd_port -dir O -from 7 -to 0 tia_chsel
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# adc peripherals - controlled by PS7/SPI0
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# adc peripherals - controlled by PS7/SPI0
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@ -44,7 +44,7 @@ module util_tia_chsel #(
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input adc_tia_chsel_en,
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input adc_tia_chsel_en,
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output [DATA_WIDTH-1:0] adc_data_tia_chsel,
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output [DATA_WIDTH-1:0] adc_data_tia_chsel,
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input [ 1:0] tia_chsel);
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input [ 7:0] tia_chsel);
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(* keep = "TRUE" *)reg [DATA_WIDTH-1:0] adc_data_tia_chsel_int;
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(* keep = "TRUE" *)reg [DATA_WIDTH-1:0] adc_data_tia_chsel_int;
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@ -53,7 +53,7 @@ module util_tia_chsel #(
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for (i=0; i<DATA_WIDTH/16; i=i+1) begin
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for (i=0; i<DATA_WIDTH/16; i=i+1) begin
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (adc_tia_chsel_en)
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if (adc_tia_chsel_en)
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adc_data_tia_chsel_int[i*16+:16] <= {14'h0, tia_chsel};
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adc_data_tia_chsel_int[i*16+:16] <= {8'h0, tia_chsel};
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end
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end
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end
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end
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endgenerate
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endgenerate
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@ -68,22 +68,22 @@ set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS25} [get_ports laser_gp
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set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS25} [get_ports laser_gpio[12]] ; ## G33 FMC_HPC_LA31_P
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set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS25} [get_ports laser_gpio[12]] ; ## G33 FMC_HPC_LA31_P
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set_property -dict {PACKAGE_PIN P29 IOSTANDARD LVCMOS25} [get_ports laser_gpio[13]] ; ## G34 FMC_HPC_LA31_N
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set_property -dict {PACKAGE_PIN P29 IOSTANDARD LVCMOS25} [get_ports laser_gpio[13]] ; ## G34 FMC_HPC_LA31_N
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# AFE vref selection
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# TIA channel selection
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set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports afe_sel[0]] ; ## afe_sel0_1 C11 FMC_HPC_LA06_N
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set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports tia_chsel[0]] ; ## afe_sel0_1 C11 FMC_HPC_LA06_N
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set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports afe_sel[1]] ; ## afe_sel1_1 C14 FMC_HPC_LA10_P
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set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports tia_chsel[1]] ; ## afe_sel1_1 C14 FMC_HPC_LA10_P
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set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports afe_sel[2]] ; ## afe_sel0_2 C15 FMC_HPC_LA10_N
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set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports tia_chsel[2]] ; ## afe_sel0_2 C15 FMC_HPC_LA10_N
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set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports afe_sel[3]] ; ## afe_sel1_2 C18 FMC_HPC_LA14_P
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set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports tia_chsel[3]] ; ## afe_sel1_2 C18 FMC_HPC_LA14_P
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set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports afe_sel[4]] ; ## afe_sel0_3 C19 FMC_HPC_LA14_N
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set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports tia_chsel[4]] ; ## afe_sel0_3 C19 FMC_HPC_LA14_N
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set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports afe_sel[5]] ; ## afe_sel1_3 D11 FMC_HPC_LA05_P
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set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports tia_chsel[5]] ; ## afe_sel1_3 D11 FMC_HPC_LA05_P
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set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports afe_sel[6]] ; ## afe_sel0_4 D12 FMC_HPC_LA05_N
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set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports tia_chsel[6]] ; ## afe_sel0_4 D12 FMC_HPC_LA05_N
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set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports afe_sel[7]] ; ## afe_sel1_4 D14 FMC_HPC_LA09_P
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set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports tia_chsel[7]] ; ## afe_sel1_4 D14 FMC_HPC_LA09_P
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# AFE DAC I2C and control
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# AFE DAC I2C and control
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set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports afe_dac_sda] ; ## D15 FMC_HPC_LA09_N
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set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports afe_dac_sda] ; ## D15 FMC_HPC_LA09_N
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set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports afe_dac_scl] ; ## D17 FMC_HPC_LA13_P
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set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports afe_dac_scl] ; ## D17 FMC_HPC_LA13_P
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set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports afe_dac_clr_n] ; ## D18 FMC_HPC_LA13_N
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set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports afe_dac_clr_n] ; ## D18 FMC_HPC_LA13_N
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set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports afe_dac_load] ; ## G06 FMC_HPC_LA00_CC_P
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set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports afe_dac_load] ; ## G06 FMC_HPC_LA00_CC_P
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# AFE ADC SPI and control
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# AFE ADC SPI and control
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@ -138,7 +138,7 @@ module system_top (
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// Vref selects for AFE board
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// Vref selects for AFE board
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output [ 7:0] afe_sel
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output [ 7:0] tia_chsel
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);
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);
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@ -152,7 +152,6 @@ module system_top (
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wire rx_sysref;
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wire rx_sysref;
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wire rx_device_clk;
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wire rx_device_clk;
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wire laser_driver;
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wire laser_driver;
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wire [ 1:0] tia_chsel_s;
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// instantiations
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// instantiations
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@ -217,13 +216,6 @@ module system_top (
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.dio_o (gpio_i[14:0]),
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.dio_o (gpio_i[14:0]),
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.dio_p (gpio_bd));
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.dio_p (gpio_bd));
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// TIA multiplexer selection bits
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assign afe_sel[1:0] = tia_chsel_s;
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assign afe_sel[3:2] = tia_chsel_s;
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assign afe_sel[5:4] = tia_chsel_s;
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assign afe_sel[7:6] = tia_chsel_s;
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// block design instance
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// block design instance
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system_wrapper i_system_wrapper (
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system_wrapper i_system_wrapper (
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@ -274,7 +266,7 @@ module system_top (
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.laser_driver (laser_driver),
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.laser_driver (laser_driver),
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.laser_driver_en_n (laser_driver_en_n),
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.laser_driver_en_n (laser_driver_en_n),
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.laser_driver_otw_n (laser_driver_otw_n),
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.laser_driver_otw_n (laser_driver_otw_n),
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.tia_chsel (tia_chsel_s),
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.tia_chsel (tia_chsel),
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.iic_dac_scl_io (afe_dac_scl),
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.iic_dac_scl_io (afe_dac_scl),
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.iic_dac_sda_io (afe_dac_sda),
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.iic_dac_sda_io (afe_dac_sda),
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.spi0_clk_i (spi_adc_clk),
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.spi0_clk_i (spi_adc_clk),
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