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axi_laser_driver: TIA's are controlled individually in manual mode 

Update the sequencer, so the TIA channel selection can be controlled separately
for each TIA, when the sequencer runs in manual mode.
main
Istvan Csomortani 2019-07-18 14:02:35 +01:00 committed by István Csomortáni
parent ea158ee42b
commit d43e6ee239
6 changed files with 39 additions and 38 deletions
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16
library/axi_laser_driver/axi_laser_driver.v
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@ -72,7 +72,7 @@ module axi_laser_driver #(
output driver_pulse,
input driver_otw_n,
output driver_dp_reset,
output reg [ 1:0] tia_chsel,
output reg [ 7:0] tia_chsel,
// interrupt
@ -116,7 +116,7 @@ module axi_laser_driver #(
wire [ 1:0] auto_seq1_s;
wire [ 1:0] auto_seq2_s;
wire [ 1:0] auto_seq3_s;
wire [ 1:0] manual_select_s;
wire [ 7:0] manual_select_s;
// local parameters
@ -247,16 +247,16 @@ module axi_laser_driver #(
always @(posedge clk) begin
if (sequence_en_s == 1'b0) begin
tia_chsel <= 2'b0;
tia_chsel <= 8'h00;
end else begin
if (pulse_counter_s == sequence_offset_s) begin
if (auto_sequence_s) begin
case (sequence_counter)
2'b00 : tia_chsel <= auto_seq0_s;
2'b01 : tia_chsel <= auto_seq1_s;
2'b10 : tia_chsel <= auto_seq2_s;
2'b11 : tia_chsel <= auto_seq3_s;
default : tia_chsel <= 2'b00;
2'b00 : tia_chsel <= {auto_seq0_s, auto_seq0_s, auto_seq0_s, auto_seq0_s};
2'b01 : tia_chsel <= {auto_seq1_s, auto_seq1_s, auto_seq1_s, auto_seq1_s};
2'b10 : tia_chsel <= {auto_seq2_s, auto_seq2_s, auto_seq2_s, auto_seq2_s};
2'b11 : tia_chsel <= {auto_seq3_s, auto_seq3_s, auto_seq3_s, auto_seq3_s};
default : tia_chsel <= 8'h00;
endcase
end else begin
tia_chsel <= manual_select_s;

23
library/axi_laser_driver/axi_laser_driver_regmap.v
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@ -61,7 +61,7 @@ module axi_laser_driver_regmap #(
output [ 1:0] auto_seq2,
output [ 1:0] auto_seq3,
output [ 1:0] manual_select,
output [ 7:0] manual_select,
// processor interface
@ -91,7 +91,7 @@ module axi_laser_driver_regmap #(
reg [ 1:0] up_auto_seq1 = 2'b01;
reg [ 1:0] up_auto_seq2 = 2'b10;
reg [ 1:0] up_auto_seq3 = 2'b11;
reg [ 1:0] up_manual_select = 2'b00;
reg [ 7:0] up_manual_select = 8'h00;
// internal signals
@ -122,7 +122,7 @@ module axi_laser_driver_regmap #(
up_auto_seq1 <= 2'b01;
up_auto_seq2 <= 2'b10;
up_auto_seq3 <= 2'b11;
up_manual_select <= 2'b00;
up_manual_select <= 8'h00;
end else begin
up_wack <= up_wreq_int_s;
if ((up_wreq_int_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
@ -145,7 +145,10 @@ module axi_laser_driver_regmap #(
up_auto_seq3 <= up_wdata[13:12];
end
if ((up_wreq_int_s == 1'b1) && (up_waddr[3:0] == 4'hE)) begin
up_sequence_offset <= up_wdata[1:0];
up_manual_select <= {up_wdata[13:12],
up_wdata[9:8],
up_wdata[5:4],
up_wdata[1:0]};
end
end
end
@ -166,8 +169,14 @@ module axi_laser_driver_regmap #(
5'h0A: up_rdata <= {29'h0, up_irq_pending_s};
5'h0B: up_rdata <= {30'h0, up_auto_sequence, up_sequence_en};
5'h0C: up_rdata <= up_sequence_offset;
5'h0D: up_rdata <= {16'h0, up_auto_seq3, 2'b0, up_auto_seq2, 2'b0, up_auto_seq1, 2'b0, up_auto_seq0};
5'h0E: up_rdata <= {30'h0, up_manual_select};
5'h0D: up_rdata <= {18'h0, up_auto_seq3,
2'h0, up_auto_seq2,
2'h0, up_auto_seq1,
2'h0, up_auto_seq0};
5'h0E: up_rdata <= {18'h0, up_manual_select[7:6],
2'h0, up_manual_select[5:4],
2'h0, up_manual_select[3:2],
2'h0, up_manual_select[1:0]};
default: up_rdata <= 0;
endcase
@ -240,7 +249,7 @@ module axi_laser_driver_regmap #(
.out_bits ({auto_sequence, sequence_en}));
sync_bits #(
.NUM_OF_BITS (10),
.NUM_OF_BITS (16),
.ASYNC_CLK (1))
i_sequencer_sync (
.in_bits ({up_auto_seq3,

2
projects/ad_fmclidar1_ebz/common/ad_fmclidar1_ebz_bd.tcl
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@ -21,7 +21,7 @@ create_bd_port -dir I spi_afe_adc_sdi_i
create_bd_port -dir O laser_driver
create_bd_port -dir O laser_driver_en_n
create_bd_port -dir I laser_driver_otw_n
create_bd_port -dir O -from 1 -to 0 tia_chsel
create_bd_port -dir O -from 7 -to 0 tia_chsel
# adc peripherals - controlled by PS7/SPI0

4
projects/ad_fmclidar1_ebz/common/util_tia_chsel.v
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@ -44,7 +44,7 @@ module util_tia_chsel #(
input adc_tia_chsel_en,
output [DATA_WIDTH-1:0] adc_data_tia_chsel,
input [ 1:0] tia_chsel);
input [ 7:0] tia_chsel);
(* keep = "TRUE" *)reg [DATA_WIDTH-1:0] adc_data_tia_chsel_int;
@ -53,7 +53,7 @@ module util_tia_chsel #(
for (i=0; i<DATA_WIDTH/16; i=i+1) begin
always @(posedge clk) begin
if (adc_tia_chsel_en)
adc_data_tia_chsel_int[i*16+:16] <= {14'h0, tia_chsel};
adc_data_tia_chsel_int[i*16+:16] <= {8'h0, tia_chsel};
end
end
endgenerate

20
projects/ad_fmclidar1_ebz/zc706/system_constr.xdc
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@ -68,22 +68,22 @@ set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS25} [get_ports laser_gp
set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS25} [get_ports laser_gpio[12]] ; ## G33 FMC_HPC_LA31_P
set_property -dict {PACKAGE_PIN P29 IOSTANDARD LVCMOS25} [get_ports laser_gpio[13]] ; ## G34 FMC_HPC_LA31_N
# AFE vref selection
# TIA channel selection
set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports afe_sel[0]] ; ## afe_sel0_1 C11 FMC_HPC_LA06_N
set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports afe_sel[1]] ; ## afe_sel1_1 C14 FMC_HPC_LA10_P
set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports afe_sel[2]] ; ## afe_sel0_2 C15 FMC_HPC_LA10_N
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports afe_sel[3]] ; ## afe_sel1_2 C18 FMC_HPC_LA14_P
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports afe_sel[4]] ; ## afe_sel0_3 C19 FMC_HPC_LA14_N
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports afe_sel[5]] ; ## afe_sel1_3 D11 FMC_HPC_LA05_P
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports afe_sel[6]] ; ## afe_sel0_4 D12 FMC_HPC_LA05_N
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports afe_sel[7]] ; ## afe_sel1_4 D14 FMC_HPC_LA09_P
set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports tia_chsel[0]] ; ## afe_sel0_1 C11 FMC_HPC_LA06_N
set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports tia_chsel[1]] ; ## afe_sel1_1 C14 FMC_HPC_LA10_P
set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports tia_chsel[2]] ; ## afe_sel0_2 C15 FMC_HPC_LA10_N
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports tia_chsel[3]] ; ## afe_sel1_2 C18 FMC_HPC_LA14_P
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports tia_chsel[4]] ; ## afe_sel0_3 C19 FMC_HPC_LA14_N
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports tia_chsel[5]] ; ## afe_sel1_3 D11 FMC_HPC_LA05_P
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports tia_chsel[6]] ; ## afe_sel0_4 D12 FMC_HPC_LA05_N
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports tia_chsel[7]] ; ## afe_sel1_4 D14 FMC_HPC_LA09_P
# AFE DAC I2C and control
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports afe_dac_sda] ; ## D15 FMC_HPC_LA09_N
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports afe_dac_scl] ; ## D17 FMC_HPC_LA13_P
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports afe_dac_clr_n] ; ## D18 FMC_HPC_LA13_N
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports afe_dac_clr_n] ; ## D18 FMC_HPC_LA13_N
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports afe_dac_load] ; ## G06 FMC_HPC_LA00_CC_P
# AFE ADC SPI and control

12
projects/ad_fmclidar1_ebz/zc706/system_top.v
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@ -138,7 +138,7 @@ module system_top (
// Vref selects for AFE board
output [ 7:0] afe_sel
output [ 7:0] tia_chsel
);
@ -152,7 +152,6 @@ module system_top (
wire rx_sysref;
wire rx_device_clk;
wire laser_driver;
wire [ 1:0] tia_chsel_s;
// instantiations
@ -217,13 +216,6 @@ module system_top (
.dio_o (gpio_i[14:0]),
.dio_p (gpio_bd));
// TIA multiplexer selection bits
assign afe_sel[1:0] = tia_chsel_s;
assign afe_sel[3:2] = tia_chsel_s;
assign afe_sel[5:4] = tia_chsel_s;
assign afe_sel[7:6] = tia_chsel_s;
// block design instance
system_wrapper i_system_wrapper (
@ -274,7 +266,7 @@ module system_top (
.laser_driver (laser_driver),
.laser_driver_en_n (laser_driver_en_n),
.laser_driver_otw_n (laser_driver_otw_n),
.tia_chsel (tia_chsel_s),
.tia_chsel (tia_chsel),
.iic_dac_scl_io (afe_dac_scl),
.iic_dac_sda_io (afe_dac_sda),
.spi0_clk_i (spi_adc_clk),