fmcjesdadc1: Updated project to new flow. Updated ZC706 design
Adrian Costina
parent
58a5e0142c
commit
d418c9f9b1
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@ -1,57 +1,42 @@
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# ad9250
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set spi_csn_o [create_bd_port -dir O spi_csn_o]
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set spi_csn_i [create_bd_port -dir I spi_csn_i]
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set spi_clk_i [create_bd_port -dir I spi_clk_i]
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set spi_clk_o [create_bd_port -dir O spi_clk_o]
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set spi_sdo_i [create_bd_port -dir I spi_sdo_i]
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set spi_sdo_o [create_bd_port -dir O spi_sdo_o]
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set spi_sdi_i [create_bd_port -dir I spi_sdi_i]
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create_bd_port -dir I rx_ref_clk
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create_bd_port -dir O rx_sync
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create_bd_port -dir O rx_sysref
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create_bd_port -dir I -from 3 -to 0 rx_data_p
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create_bd_port -dir I -from 3 -to 0 rx_data_n
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set rx_ref_clk [create_bd_port -dir I rx_ref_clk]
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set rx_sync [create_bd_port -dir O rx_sync]
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set rx_sysref [create_bd_port -dir O rx_sysref]
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set rx_data_p [create_bd_port -dir I -from 3 -to 0 rx_data_p]
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set rx_data_n [create_bd_port -dir I -from 3 -to 0 rx_data_n]
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create_bd_port -dir O -from 127 -to 0 rx_gt_data
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create_bd_port -dir I -from 63 -to 0 rx_gt_data_0
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create_bd_port -dir I -from 63 -to 0 rx_gt_data_1
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set rx_gt_data [create_bd_port -dir O -from 127 -to 0 rx_gt_data]
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set rx_gt_data_0 [create_bd_port -dir I -from 63 -to 0 rx_gt_data_0]
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set rx_gt_data_1 [create_bd_port -dir I -from 63 -to 0 rx_gt_data_1]
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set adc_clk [create_bd_port -dir O adc_clk]
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set adc_0_enable_a [create_bd_port -dir O adc_0_enable_a]
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set adc_0_valid_a [create_bd_port -dir O adc_0_valid_a]
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set adc_0_data_a [create_bd_port -dir O -from 31 -to 0 adc_0_data_a]
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set adc_0_enable_b [create_bd_port -dir O adc_0_enable_b]
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set adc_0_valid_b [create_bd_port -dir O adc_0_valid_b]
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set adc_0_data_b [create_bd_port -dir O -from 31 -to 0 adc_0_data_b]
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set adc_1_enable_a [create_bd_port -dir O adc_1_enable_a]
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set adc_1_valid_a [create_bd_port -dir O adc_1_valid_a]
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set adc_1_data_a [create_bd_port -dir O -from 31 -to 0 adc_1_data_a]
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set adc_1_enable_b [create_bd_port -dir O adc_1_enable_b]
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set adc_1_valid_b [create_bd_port -dir O adc_1_valid_b]
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set adc_1_data_b [create_bd_port -dir O -from 31 -to 0 adc_1_data_b]
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set dma_0_wr [create_bd_port -dir I dma_0_wr]
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set dma_0_sync [create_bd_port -dir I dma_0_sync]
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set dma_0_data [create_bd_port -dir I -from 63 -to 0 dma_0_data]
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set dma_1_wr [create_bd_port -dir I dma_1_wr]
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set dma_1_sync [create_bd_port -dir I dma_1_sync]
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set dma_1_data [create_bd_port -dir I -from 63 -to 0 dma_1_data]
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#interrupts
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set ad9250_0_dma_intr [create_bd_port -dir O ad9250_0_dma_intr]
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set ad9250_1_dma_intr [create_bd_port -dir O ad9250_1_dma_intr]
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if { $sys_zynq == 0 } {
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set ad9250_spi_intr [create_bd_port -dir O ad9250_spi_intr]
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}
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create_bd_port -dir O adc_clk
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create_bd_port -dir O adc_0_enable_a
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create_bd_port -dir O adc_0_valid_a
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create_bd_port -dir O -from 31 -to 0 adc_0_data_a
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create_bd_port -dir O adc_0_enable_b
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create_bd_port -dir O adc_0_valid_b
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create_bd_port -dir O -from 31 -to 0 adc_0_data_b
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create_bd_port -dir O adc_1_enable_a
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create_bd_port -dir O adc_1_valid_a
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create_bd_port -dir O -from 31 -to 0 adc_1_data_a
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create_bd_port -dir O adc_1_enable_b
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create_bd_port -dir O adc_1_valid_b
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create_bd_port -dir O -from 31 -to 0 adc_1_data_b
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create_bd_port -dir I dma_0_wr
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create_bd_port -dir I dma_0_sync
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create_bd_port -dir I -from 63 -to 0 dma_0_data
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create_bd_port -dir I dma_1_wr
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create_bd_port -dir I dma_1_sync
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create_bd_port -dir I -from 63 -to 0 dma_1_data
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# adc peripherals
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set axi_ad9250_0_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_0_core]
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set axi_ad9250_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_1_core]
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set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.2 axi_ad9250_jesd]
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set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.0 axi_ad9250_jesd]
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9250_jesd
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set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9250_jesd
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@ -93,245 +78,113 @@ set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9250_1_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9250_1_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9250_1_dma
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if {$sys_zynq == 1} {
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set axi_ad9250_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9250_gt_interconnect]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9250_gt_interconnect
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set axi_ad9250_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9250_dma_interconnect]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9250_dma_interconnect
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set_property -dict [list CONFIG.NUM_SI {2}] $axi_ad9250_dma_interconnect
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}
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# spi
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if {$sys_zynq == 0} {
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set axi_ad9250_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_ad9250_spi]
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set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_ad9250_spi
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set_property -dict [list CONFIG.C_NUM_SS_BITS {1}] $axi_ad9250_spi
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set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_ad9250_spi
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}
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# additions to default configuration
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if {$sys_zynq == 1} {
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set_property -dict [list CONFIG.NUM_MI {13}] $axi_cpu_interconnect
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {15}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
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} else {
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set_property -dict [list CONFIG.NUM_MI {14}] $axi_cpu_interconnect
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set_property -dict [list CONFIG.NUM_SI {11}] $axi_mem_interconnect
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}
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# connections (spi and gpio)
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if {$sys_zynq == 1 } {
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connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins sys_ps7/SPI0_SS_O]
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connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I]
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connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I]
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connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O]
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connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I]
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connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O]
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connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I]
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} else {
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connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_ad9250_spi/ss_i]
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connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_ad9250_spi/ss_o]
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connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_ad9250_spi/sck_i]
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connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_ad9250_spi/sck_o]
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connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_ad9250_spi/io0_i]
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connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_ad9250_spi/io0_o]
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connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_ad9250_spi/io1_i]
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connect_bd_net -net axi_ad9250_spi_irq [get_bd_pins axi_ad9250_spi/ip2intc_irpt] [get_bd_ports ad9250_spi_intr]
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}
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# connections (gt)
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connect_bd_net -net axi_ad9250_gt_ref_clk_c [get_bd_pins axi_ad9250_gt/ref_clk_c] [get_bd_ports rx_ref_clk]
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connect_bd_net -net axi_ad9250_gt_rx_data_p [get_bd_pins axi_ad9250_gt/rx_data_p] [get_bd_ports rx_data_p]
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connect_bd_net -net axi_ad9250_gt_rx_data_n [get_bd_pins axi_ad9250_gt/rx_data_n] [get_bd_ports rx_data_n]
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connect_bd_net -net axi_ad9250_gt_rx_sync [get_bd_pins axi_ad9250_gt/rx_sync] [get_bd_ports rx_sync]
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connect_bd_net -net axi_ad9250_gt_rx_sysref [get_bd_pins axi_ad9250_gt/rx_sysref] [get_bd_ports rx_sysref]
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ad_connect axi_ad9250_gt/ref_clk_c rx_ref_clk
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ad_connect axi_ad9250_gt/rx_data_p rx_data_p
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ad_connect axi_ad9250_gt/rx_data_n rx_data_n
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ad_connect axi_ad9250_gt/rx_sync rx_sync
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ad_connect axi_ad9250_gt/rx_sysref rx_sysref
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# connections (adc)
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connect_bd_net -net axi_ad9250_gt_rx_clk [get_bd_pins axi_ad9250_gt/rx_clk_g]
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connect_bd_net -net axi_ad9250_gt_rx_clk [get_bd_pins axi_ad9250_gt/rx_clk]
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connect_bd_net -net axi_ad9250_gt_rx_clk [get_bd_pins axi_ad9250_0_core/rx_clk]
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connect_bd_net -net axi_ad9250_gt_rx_clk [get_bd_pins axi_ad9250_1_core/rx_clk]
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connect_bd_net -net axi_ad9250_gt_rx_clk [get_bd_pins axi_ad9250_jesd/rx_core_clk]
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connect_bd_net -net axi_ad9250_gt_rx_clk [get_bd_ports adc_clk]
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connect_bd_net -net axi_ad9250_gt_rx_rst [get_bd_pins axi_ad9250_gt/rx_rst]
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connect_bd_net -net axi_ad9250_gt_rx_rst [get_bd_pins axi_ad9250_jesd/rx_reset]
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ad_connect axi_ad9250_gt_rx_clk axi_ad9250_gt/rx_clk_g
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ad_connect axi_ad9250_gt_rx_clk axi_ad9250_gt/rx_clk
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ad_connect axi_ad9250_gt_rx_clk axi_ad9250_gt/tx_clk
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ad_connect axi_ad9250_gt_rx_clk axi_ad9250_0_core/rx_clk
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ad_connect axi_ad9250_gt_rx_clk axi_ad9250_1_core/rx_clk
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ad_connect axi_ad9250_gt_rx_clk axi_ad9250_jesd/rx_core_clk
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ad_connect axi_ad9250_gt_rx_clk adc_clk
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ad_connect axi_ad9250_gt_rx_rst axi_ad9250_gt/rx_rst
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ad_connect axi_ad9250_gt_rx_rst axi_ad9250_jesd/rx_reset
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connect_bd_net -net axi_ad9250_gt_rx_sysref [get_bd_pins axi_ad9250_jesd/rx_sysref]
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connect_bd_net -net axi_ad9250_gt_rx_gt_charisk [get_bd_pins axi_ad9250_gt/rx_gt_charisk] [get_bd_pins axi_ad9250_jesd/gt_rxcharisk_in]
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connect_bd_net -net axi_ad9250_gt_rx_gt_disperr [get_bd_pins axi_ad9250_gt/rx_gt_disperr] [get_bd_pins axi_ad9250_jesd/gt_rxdisperr_in]
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connect_bd_net -net axi_ad9250_gt_rx_gt_notintable [get_bd_pins axi_ad9250_gt/rx_gt_notintable] [get_bd_pins axi_ad9250_jesd/gt_rxnotintable_in]
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connect_bd_net -net axi_ad9250_gt_rx_gt_data [get_bd_pins axi_ad9250_gt/rx_gt_data] [get_bd_pins axi_ad9250_jesd/gt_rxdata_in]
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connect_bd_net -net axi_ad9250_gt_rx_rst_done [get_bd_pins axi_ad9250_gt/rx_rst_done] [get_bd_pins axi_ad9250_jesd/rx_reset_done]
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connect_bd_net -net axi_ad9250_gt_rx_ip_comma_align [get_bd_pins axi_ad9250_gt/rx_ip_comma_align] [get_bd_pins axi_ad9250_jesd/rxencommaalign_out]
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connect_bd_net -net axi_ad9250_gt_rx_ip_sync [get_bd_pins axi_ad9250_gt/rx_ip_sync] [get_bd_pins axi_ad9250_jesd/rx_sync]
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connect_bd_net -net axi_ad9250_gt_rx_ip_sof [get_bd_pins axi_ad9250_gt/rx_ip_sof] [get_bd_pins axi_ad9250_jesd/rx_start_of_frame]
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connect_bd_net -net axi_ad9250_gt_rx_ip_data [get_bd_pins axi_ad9250_gt/rx_ip_data] [get_bd_pins axi_ad9250_jesd/rx_tdata]
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ad_connect axi_ad9250_gt_rx_sysref axi_ad9250_jesd/rx_sysref
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connect_bd_net -net axi_ad9250_gt_rx_data [get_bd_pins axi_ad9250_gt/rx_data] [get_bd_ports rx_gt_data]
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connect_bd_net -net axi_ad9250_0_gt_rx_data [get_bd_pins axi_ad9250_0_core/rx_data] [get_bd_ports rx_gt_data_0]
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connect_bd_net -net axi_ad9250_1_gt_rx_data [get_bd_pins axi_ad9250_1_core/rx_data] [get_bd_ports rx_gt_data_1]
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create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_charisk
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set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_charisk]
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set_property -dict [list CONFIG.CH_CNT {4}] [get_bd_cells util_bsplit_rx_gt_charisk]
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connect_bd_net -net axi_ad9250_0_adc_clk [get_bd_pins axi_ad9250_0_core/adc_clk] [get_bd_pins axi_ad9250_0_dma/fifo_wr_clk]
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connect_bd_net -net axi_ad9250_1_adc_clk [get_bd_pins axi_ad9250_1_core/adc_clk] [get_bd_pins axi_ad9250_1_dma/fifo_wr_clk]
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ad_connect util_bsplit_rx_gt_charisk/data axi_ad9250_gt/rx_gt_charisk
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ad_connect util_bsplit_rx_gt_charisk/split_data_0 axi_ad9250_jesd/gt0_rxcharisk
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ad_connect util_bsplit_rx_gt_charisk/split_data_1 axi_ad9250_jesd/gt1_rxcharisk
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ad_connect util_bsplit_rx_gt_charisk/split_data_2 axi_ad9250_jesd/gt2_rxcharisk
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ad_connect util_bsplit_rx_gt_charisk/split_data_3 axi_ad9250_jesd/gt3_rxcharisk
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connect_bd_net -net axi_ad9250_0_adc_enable_a [get_bd_pins axi_ad9250_0_core/adc_enable_a] [get_bd_ports adc_0_enable_a]
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connect_bd_net -net axi_ad9250_0_adc_valid_a [get_bd_pins axi_ad9250_0_core/adc_valid_a] [get_bd_ports adc_0_valid_a]
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connect_bd_net -net axi_ad9250_0_adc_data_a [get_bd_pins axi_ad9250_0_core/adc_data_a] [get_bd_ports adc_0_data_a]
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connect_bd_net -net axi_ad9250_0_adc_enable_b [get_bd_pins axi_ad9250_0_core/adc_enable_b] [get_bd_ports adc_0_enable_b]
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connect_bd_net -net axi_ad9250_0_adc_valid_b [get_bd_pins axi_ad9250_0_core/adc_valid_b] [get_bd_ports adc_0_valid_b]
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connect_bd_net -net axi_ad9250_0_adc_data_b [get_bd_pins axi_ad9250_0_core/adc_data_b] [get_bd_ports adc_0_data_b]
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connect_bd_net -net axi_ad9250_1_adc_enable_a [get_bd_pins axi_ad9250_1_core/adc_enable_a] [get_bd_ports adc_1_enable_a]
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connect_bd_net -net axi_ad9250_1_adc_valid_a [get_bd_pins axi_ad9250_1_core/adc_valid_a] [get_bd_ports adc_1_valid_a]
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connect_bd_net -net axi_ad9250_1_adc_data_a [get_bd_pins axi_ad9250_1_core/adc_data_a] [get_bd_ports adc_1_data_a]
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connect_bd_net -net axi_ad9250_1_adc_enable_b [get_bd_pins axi_ad9250_1_core/adc_enable_b] [get_bd_ports adc_1_enable_b]
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connect_bd_net -net axi_ad9250_1_adc_valid_b [get_bd_pins axi_ad9250_1_core/adc_valid_b] [get_bd_ports adc_1_valid_b]
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connect_bd_net -net axi_ad9250_1_adc_data_b [get_bd_pins axi_ad9250_1_core/adc_data_b] [get_bd_ports adc_1_data_b]
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#ad_connect axi_ad9250_gt/rx_gt_charisk axi_ad9250_jesd/gt_rxcharisk_in
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create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_disperr
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set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_disperr]
|
||||
set_property -dict [list CONFIG.CH_CNT {4}] [get_bd_cells util_bsplit_rx_gt_disperr]
|
||||
|
||||
connect_bd_net -net axi_ad9250_0_dma_wr [get_bd_pins axi_ad9250_0_dma/fifo_wr_en] [get_bd_ports dma_0_wr]
|
||||
connect_bd_net -net axi_ad9250_0_dma_sync [get_bd_pins axi_ad9250_0_dma/fifo_wr_sync] [get_bd_ports dma_0_sync]
|
||||
connect_bd_net -net axi_ad9250_0_dma_data [get_bd_pins axi_ad9250_0_dma/fifo_wr_din] [get_bd_ports dma_0_data]
|
||||
connect_bd_net -net axi_ad9250_1_dma_wr [get_bd_pins axi_ad9250_1_dma/fifo_wr_en] [get_bd_ports dma_1_wr]
|
||||
connect_bd_net -net axi_ad9250_1_dma_sync [get_bd_pins axi_ad9250_1_dma/fifo_wr_sync] [get_bd_ports dma_1_sync]
|
||||
connect_bd_net -net axi_ad9250_1_dma_data [get_bd_pins axi_ad9250_1_dma/fifo_wr_din] [get_bd_ports dma_1_data]
|
||||
ad_connect util_bsplit_rx_gt_disperr/data axi_ad9250_gt/rx_gt_disperr
|
||||
ad_connect util_bsplit_rx_gt_disperr/split_data_0 axi_ad9250_jesd/gt0_rxdisperr
|
||||
ad_connect util_bsplit_rx_gt_disperr/split_data_1 axi_ad9250_jesd/gt1_rxdisperr
|
||||
ad_connect util_bsplit_rx_gt_disperr/split_data_2 axi_ad9250_jesd/gt2_rxdisperr
|
||||
ad_connect util_bsplit_rx_gt_disperr/split_data_3 axi_ad9250_jesd/gt3_rxdisperr
|
||||
|
||||
connect_bd_net -net axi_ad9250_0_adc_dovf [get_bd_pins axi_ad9250_0_core/adc_dovf] [get_bd_pins axi_ad9250_0_dma/fifo_wr_overflow]
|
||||
connect_bd_net -net axi_ad9250_1_adc_dovf [get_bd_pins axi_ad9250_1_core/adc_dovf] [get_bd_pins axi_ad9250_1_dma/fifo_wr_overflow]
|
||||
connect_bd_net -net axi_ad9250_0_dma_irq [get_bd_pins axi_ad9250_0_dma/irq] [get_bd_ports ad9250_0_dma_intr]
|
||||
connect_bd_net -net axi_ad9250_1_dma_irq [get_bd_pins axi_ad9250_1_dma/irq] [get_bd_ports ad9250_1_dma_intr]
|
||||
#ad_connect axi_ad9250_gt/rx_gt_disperr axi_ad9250_jesd/gt_rxdisperr_in
|
||||
create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_notintable
|
||||
set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_notintable]
|
||||
set_property -dict [list CONFIG.CH_CNT {4}] [get_bd_cells util_bsplit_rx_gt_notintable]
|
||||
|
||||
# interconnect (cpu)
|
||||
ad_connect util_bsplit_rx_gt_notintable/data axi_ad9250_gt/rx_gt_notintable
|
||||
ad_connect util_bsplit_rx_gt_notintable/split_data_0 axi_ad9250_jesd/gt0_rxnotintable
|
||||
ad_connect util_bsplit_rx_gt_notintable/split_data_1 axi_ad9250_jesd/gt1_rxnotintable
|
||||
ad_connect util_bsplit_rx_gt_notintable/split_data_2 axi_ad9250_jesd/gt2_rxnotintable
|
||||
ad_connect util_bsplit_rx_gt_notintable/split_data_3 axi_ad9250_jesd/gt3_rxnotintable
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9250_0_dma/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9250_0_core/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9250_jesd/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9250_gt/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_ad9250_1_dma/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_ad9250_1_core/s_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_gt/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_0_core/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_1_core/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_jesd/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_0_dma/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_1_dma/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9250_gt/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9250_0_core/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9250_1_core/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9250_jesd/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9250_0_dma/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9250_1_dma/s_axi_aresetn]
|
||||
#ad_connect axi_ad9250_gt/rx_gt_notintable axi_ad9250_jesd/gt_rxnotintable_in
|
||||
|
||||
if {$sys_zynq == 0} {
|
||||
create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_data
|
||||
set_property -dict [list CONFIG.CH_DW {32}] [get_bd_cells util_bsplit_rx_gt_data]
|
||||
set_property -dict [list CONFIG.CH_CNT {4}] [get_bd_cells util_bsplit_rx_gt_data]
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_ad9250_spi/axi_lite]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_spi/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_spi/ext_spi_clk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9250_spi/s_axi_aresetn]
|
||||
}
|
||||
ad_connect util_bsplit_rx_gt_data/data axi_ad9250_gt/rx_gt_data
|
||||
ad_connect util_bsplit_rx_gt_data/split_data_0 axi_ad9250_jesd/gt0_rxdata
|
||||
ad_connect util_bsplit_rx_gt_data/split_data_1 axi_ad9250_jesd/gt1_rxdata
|
||||
ad_connect util_bsplit_rx_gt_data/split_data_2 axi_ad9250_jesd/gt2_rxdata
|
||||
ad_connect util_bsplit_rx_gt_data/split_data_3 axi_ad9250_jesd/gt3_rxdata
|
||||
|
||||
# interconnect (gt es)
|
||||
#ad_connect axi_ad9250_gt/rx_gt_data axi_ad9250_jesd/gt_rxdata_in
|
||||
|
||||
if {$sys_zynq == 1} {
|
||||
ad_connect axi_ad9250_gt/rx_rst_done axi_ad9250_jesd/rx_reset_done
|
||||
ad_connect axi_ad9250_gt/rx_ip_comma_align axi_ad9250_jesd/rxencommaalign_out
|
||||
ad_connect axi_ad9250_gt/rx_ip_sync axi_ad9250_jesd/rx_sync
|
||||
ad_connect axi_ad9250_gt/rx_ip_sof axi_ad9250_jesd/rx_start_of_frame
|
||||
ad_connect axi_ad9250_gt/rx_ip_data axi_ad9250_jesd/rx_tdata
|
||||
|
||||
connect_bd_intf_net -intf_net axi_ad9250_gt_interconnect_s00_axi [get_bd_intf_pins axi_ad9250_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9250_gt/m_axi]
|
||||
connect_bd_intf_net -intf_net axi_ad9250_gt_interconnect_m00_axi [get_bd_intf_pins axi_ad9250_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_gt_interconnect/ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_gt_interconnect/M00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_gt_interconnect/S00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9250_gt_interconnect/ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9250_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9250_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source
|
||||
ad_connect axi_ad9250_gt/rx_data rx_gt_data
|
||||
ad_connect axi_ad9250_0_core/rx_data rx_gt_data_0
|
||||
ad_connect axi_ad9250_1_core/rx_data rx_gt_data_1
|
||||
|
||||
} else {
|
||||
ad_connect axi_ad9250_0_core/adc_clk axi_ad9250_0_dma/fifo_wr_clk
|
||||
ad_connect axi_ad9250_1_core/adc_clk axi_ad9250_1_dma/fifo_wr_clk
|
||||
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_ad9250_gt/m_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_100m_resetn_source
|
||||
}
|
||||
ad_connect adc_0_enable_a axi_ad9250_0_core/adc_enable_a
|
||||
ad_connect adc_0_valid_a axi_ad9250_0_core/adc_valid_a
|
||||
ad_connect adc_0_data_a axi_ad9250_0_core/adc_data_a
|
||||
ad_connect adc_0_enable_b axi_ad9250_0_core/adc_enable_b
|
||||
ad_connect adc_0_valid_b axi_ad9250_0_core/adc_valid_b
|
||||
ad_connect adc_0_data_b axi_ad9250_0_core/adc_data_b
|
||||
ad_connect adc_1_enable_a axi_ad9250_1_core/adc_enable_a
|
||||
ad_connect adc_1_valid_a axi_ad9250_1_core/adc_valid_a
|
||||
ad_connect adc_1_data_a axi_ad9250_1_core/adc_data_a
|
||||
ad_connect adc_1_enable_b axi_ad9250_1_core/adc_enable_b
|
||||
ad_connect adc_1_valid_b axi_ad9250_1_core/adc_valid_b
|
||||
ad_connect adc_1_data_b axi_ad9250_1_core/adc_data_b
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_gt/m_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_gt/drp_clk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9250_gt/m_axi_aresetn]
|
||||
ad_connect axi_ad9250_0_dma/fifo_wr_en dma_0_wr
|
||||
ad_connect axi_ad9250_0_dma/fifo_wr_sync dma_0_sync
|
||||
ad_connect axi_ad9250_0_dma/fifo_wr_din dma_0_data
|
||||
ad_connect axi_ad9250_1_dma/fifo_wr_en dma_1_wr
|
||||
ad_connect axi_ad9250_1_dma/fifo_wr_sync dma_1_sync
|
||||
ad_connect axi_ad9250_1_dma/fifo_wr_din dma_1_data
|
||||
|
||||
# interconnect (dma)
|
||||
|
||||
if {$sys_zynq == 1} {
|
||||
|
||||
set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2]
|
||||
set sys_fmc_dma_resetn_source [get_bd_pins sys_ps7/FCLK_RESET2_N]
|
||||
|
||||
connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source
|
||||
connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source
|
||||
|
||||
connect_bd_intf_net -intf_net axi_ad9250_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9250_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2]
|
||||
connect_bd_intf_net -intf_net axi_ad9250_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9250_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9250_0_dma/m_dest_axi]
|
||||
connect_bd_intf_net -intf_net axi_ad9250_dma_interconnect_s01_axi [get_bd_intf_pins axi_ad9250_dma_interconnect/S01_AXI] [get_bd_intf_pins axi_ad9250_1_dma/m_dest_axi]
|
||||
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9250_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
|
||||
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9250_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
|
||||
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9250_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
|
||||
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9250_dma_interconnect/S01_ACLK] $sys_fmc_dma_clk_source
|
||||
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK]
|
||||
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9250_0_dma/m_dest_axi_aclk]
|
||||
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9250_1_dma/m_dest_axi_aclk]
|
||||
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9250_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source
|
||||
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9250_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source
|
||||
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9250_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source
|
||||
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9250_dma_interconnect/S01_ARESETN] $sys_fmc_dma_resetn_source
|
||||
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9250_0_dma/m_dest_axi_aresetn]
|
||||
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9250_1_dma/m_dest_axi_aresetn]
|
||||
|
||||
} else {
|
||||
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9250_0_dma/m_dest_axi]
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s10_axi [get_bd_intf_pins axi_mem_interconnect/S10_AXI] [get_bd_intf_pins axi_ad9250_1_dma/m_dest_axi]
|
||||
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_200m_clk_source
|
||||
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S10_ACLK] $sys_200m_clk_source
|
||||
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9250_0_dma/m_dest_axi_aclk]
|
||||
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9250_1_dma/m_dest_axi_aclk]
|
||||
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_200m_resetn_source
|
||||
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S10_ARESETN] $sys_200m_resetn_source
|
||||
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9250_0_dma/m_dest_axi_aresetn]
|
||||
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9250_1_dma/m_dest_axi_aresetn]
|
||||
}
|
||||
ad_connect axi_ad9250_0_core/adc_dovf axi_ad9250_0_dma/fifo_wr_overflow
|
||||
ad_connect axi_ad9250_1_core/adc_dovf axi_ad9250_1_dma/fifo_wr_overflow
|
||||
|
||||
# ila
|
||||
|
||||
set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_rx_mon]
|
||||
set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_jesd_rx_mon]
|
||||
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_NUM_OF_PROBES {7}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE0_WIDTH {334}] $ila_jesd_rx_mon
|
||||
|
|
@ -342,39 +195,39 @@ set_property -dict [list CONFIG.C_PROBE4_WIDTH {32}] $ila_jesd_rx_mon
|
|||
set_property -dict [list CONFIG.C_PROBE5_WIDTH {32}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE6_WIDTH {32}] $ila_jesd_rx_mon
|
||||
|
||||
connect_bd_net -net axi_ad9250_gt_rx_mon_data [get_bd_pins axi_ad9250_gt/rx_mon_data]
|
||||
connect_bd_net -net axi_ad9250_gt_rx_mon_trigger [get_bd_pins axi_ad9250_gt/rx_mon_trigger]
|
||||
connect_bd_net -net axi_ad9250_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK]
|
||||
connect_bd_net -net axi_ad9250_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0]
|
||||
connect_bd_net -net axi_ad9250_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1]
|
||||
connect_bd_net -net axi_ad9250_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2]
|
||||
connect_bd_net -net axi_ad9250_0_adc_data_a [get_bd_pins ila_jesd_rx_mon/PROBE3]
|
||||
connect_bd_net -net axi_ad9250_0_adc_data_b [get_bd_pins ila_jesd_rx_mon/PROBE4]
|
||||
connect_bd_net -net axi_ad9250_1_adc_data_a [get_bd_pins ila_jesd_rx_mon/PROBE5]
|
||||
connect_bd_net -net axi_ad9250_1_adc_data_b [get_bd_pins ila_jesd_rx_mon/PROBE6]
|
||||
ad_connect axi_ad9250_gt_rx_mon_data axi_ad9250_gt/rx_mon_data
|
||||
ad_connect axi_ad9250_gt_rx_mon_trigger axi_ad9250_gt/rx_mon_trigger
|
||||
ad_connect axi_ad9250_gt_rx_clk ila_jesd_rx_mon/CLK
|
||||
ad_connect axi_ad9250_gt_rx_mon_data ila_jesd_rx_mon/PROBE0
|
||||
ad_connect axi_ad9250_gt_rx_mon_trigger ila_jesd_rx_mon/PROBE1
|
||||
ad_connect axi_ad9250_gt_rx_data ila_jesd_rx_mon/PROBE2
|
||||
ad_connect axi_ad9250_0_adc_data_a ila_jesd_rx_mon/PROBE3
|
||||
ad_connect axi_ad9250_0_adc_data_b ila_jesd_rx_mon/PROBE4
|
||||
ad_connect axi_ad9250_1_adc_data_a ila_jesd_rx_mon/PROBE5
|
||||
ad_connect axi_ad9250_1_adc_data_b ila_jesd_rx_mon/PROBE6
|
||||
|
||||
# address map
|
||||
# interconnects
|
||||
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9250_0_core/s_axi/axi_lite] SEG_data_ad9250_0_core
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A20000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9250_1_core/s_axi/axi_lite] SEG_data_ad9250_1_core
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9250_gt/s_axi/axi_lite] SEG_data_ad9250_gt
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9250_jesd/s_axi/Reg] SEG_data_ad9250_jesd
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9250_0_dma/s_axi/axi_lite] SEG_data_ad9250_0_dma
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x7c430000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9250_1_dma/s_axi/axi_lite] SEG_data_ad9250_1_dma
|
||||
ad_cpu_interconnect 0x44A10000 axi_ad9250_0_core
|
||||
ad_cpu_interconnect 0x44A20000 axi_ad9250_1_core
|
||||
ad_cpu_interconnect 0x44A60000 axi_ad9250_gt
|
||||
ad_cpu_interconnect 0x44A91000 axi_ad9250_jesd
|
||||
ad_cpu_interconnect 0x7c420000 axi_ad9250_0_dma
|
||||
ad_cpu_interconnect 0x7c430000 axi_ad9250_1_dma
|
||||
|
||||
if {$sys_zynq == 0} {
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9250_spi/axi_lite/Reg] SEG_data_ad9250_spi
|
||||
}
|
||||
ad_mem_hp2_interconnect sys_200m_clk sys_ps7/S_AXI_HP2
|
||||
ad_mem_hp2_interconnect sys_200m_clk axi_ad9250_0_dma/m_dest_axi
|
||||
ad_mem_hp2_interconnect sys_200m_clk axi_ad9250_1_dma/m_dest_axi
|
||||
ad_connect sys_cpu_resetn axi_ad9250_0_dma/m_dest_axi_aresetn
|
||||
ad_connect sys_cpu_resetn axi_ad9250_1_dma/m_dest_axi_aresetn
|
||||
|
||||
if {$sys_zynq == 1} {
|
||||
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
|
||||
ad_mem_hp3_interconnect sys_cpu_clk axi_ad9250_gt/m_axi
|
||||
ad_connect sys_cpu_clk axi_ad9250_gt/drp_clk
|
||||
ad_connect sys_cpu_resetn axi_ad9250_gt/m_axi_aresetn
|
||||
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9250_0_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9250_1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9250_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm
|
||||
#interrupts
|
||||
|
||||
} else {
|
||||
ad_cpu_interrupt ps-13 mb-10 axi_ad9250_0_dma/irq
|
||||
ad_cpu_interrupt ps-12 mb-11 axi_ad9250_1_dma/irq
|
||||
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9250_0_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9250_1_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9250_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||
}
|
||||
|
|
|
|||
|
|
@ -22,10 +22,8 @@ set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports spi_sdio
|
|||
|
||||
create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p]
|
||||
create_clock -name rx_div_clk -period 8.80 [get_nets i_system_wrapper/system_i/axi_ad9250_gt_rx_clk]
|
||||
create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
|
||||
|
||||
set_clock_groups -asynchronous -group {rx_div_clk}
|
||||
set_clock_groups -asynchronous -group {fmc_dma_clk}
|
||||
|
||||
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9250_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE]
|
||||
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9250_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE]
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@
|
|||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_project.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_board.tcl
|
||||
|
||||
adi_project_create fmcjesdadc1_zc706
|
||||
adi_project_files fmcjesdadc1_zc706 [list \
|
||||
|
|
|
|||
|
|
@ -41,28 +41,28 @@
|
|||
|
||||
module system_top (
|
||||
|
||||
DDR_addr,
|
||||
DDR_ba,
|
||||
DDR_cas_n,
|
||||
DDR_ck_n,
|
||||
DDR_ck_p,
|
||||
DDR_cke,
|
||||
DDR_cs_n,
|
||||
DDR_dm,
|
||||
DDR_dq,
|
||||
DDR_dqs_n,
|
||||
DDR_dqs_p,
|
||||
DDR_odt,
|
||||
DDR_ras_n,
|
||||
DDR_reset_n,
|
||||
DDR_we_n,
|
||||
ddr_addr,
|
||||
ddr_ba,
|
||||
ddr_cas_n,
|
||||
ddr_ck_n,
|
||||
ddr_ck_p,
|
||||
ddr_cke,
|
||||
ddr_cs_n,
|
||||
ddr_dm,
|
||||
ddr_dq,
|
||||
ddr_dqs_n,
|
||||
ddr_dqs_p,
|
||||
ddr_odt,
|
||||
ddr_ras_n,
|
||||
ddr_reset_n,
|
||||
ddr_we_n,
|
||||
|
||||
FIXED_IO_ddr_vrn,
|
||||
FIXED_IO_ddr_vrp,
|
||||
FIXED_IO_mio,
|
||||
FIXED_IO_ps_clk,
|
||||
FIXED_IO_ps_porb,
|
||||
FIXED_IO_ps_srstb,
|
||||
fixed_io_ddr_vrn,
|
||||
fixed_io_ddr_vrp,
|
||||
fixed_io_mio,
|
||||
fixed_io_ps_clk,
|
||||
fixed_io_ps_porb,
|
||||
fixed_io_ps_srstb,
|
||||
|
||||
gpio_bd,
|
||||
|
||||
|
|
@ -88,28 +88,28 @@ module system_top (
|
|||
spi_clk,
|
||||
spi_sdio);
|
||||
|
||||
inout [14:0] DDR_addr;
|
||||
inout [ 2:0] DDR_ba;
|
||||
inout DDR_cas_n;
|
||||
inout DDR_ck_n;
|
||||
inout DDR_ck_p;
|
||||
inout DDR_cke;
|
||||
inout DDR_cs_n;
|
||||
inout [ 3:0] DDR_dm;
|
||||
inout [31:0] DDR_dq;
|
||||
inout [ 3:0] DDR_dqs_n;
|
||||
inout [ 3:0] DDR_dqs_p;
|
||||
inout DDR_odt;
|
||||
inout DDR_ras_n;
|
||||
inout DDR_reset_n;
|
||||
inout DDR_we_n;
|
||||
inout [14:0] ddr_addr;
|
||||
inout [ 2:0] ddr_ba;
|
||||
inout ddr_cas_n;
|
||||
inout ddr_ck_n;
|
||||
inout ddr_ck_p;
|
||||
inout ddr_cke;
|
||||
inout ddr_cs_n;
|
||||
inout [ 3:0] ddr_dm;
|
||||
inout [31:0] ddr_dq;
|
||||
inout [ 3:0] ddr_dqs_n;
|
||||
inout [ 3:0] ddr_dqs_p;
|
||||
inout ddr_odt;
|
||||
inout ddr_ras_n;
|
||||
inout ddr_reset_n;
|
||||
inout ddr_we_n;
|
||||
|
||||
inout FIXED_IO_ddr_vrn;
|
||||
inout FIXED_IO_ddr_vrp;
|
||||
inout [53:0] FIXED_IO_mio;
|
||||
inout FIXED_IO_ps_clk;
|
||||
inout FIXED_IO_ps_porb;
|
||||
inout FIXED_IO_ps_srstb;
|
||||
inout fixed_io_ddr_vrn;
|
||||
inout fixed_io_ddr_vrp;
|
||||
inout [53:0] fixed_io_mio;
|
||||
inout fixed_io_ps_clk;
|
||||
inout fixed_io_ps_porb;
|
||||
inout fixed_io_ps_srstb;
|
||||
|
||||
inout [14:0] gpio_bd;
|
||||
|
||||
|
|
@ -144,12 +144,18 @@ module system_top (
|
|||
|
||||
// internal signals
|
||||
|
||||
wire [14:0] gpio_i;
|
||||
wire [14:0] gpio_o;
|
||||
wire [14:0] gpio_t;
|
||||
wire [63:0] gpio_i;
|
||||
wire [63:0] gpio_o;
|
||||
wire [63:0] gpio_t;
|
||||
wire rx_ref_clk;
|
||||
wire spi_miso;
|
||||
wire spi_mosi;
|
||||
wire [ 2:0] spi0_csn;
|
||||
wire spi0_clk;
|
||||
wire spi0_mosi;
|
||||
wire spi0_miso;
|
||||
wire [ 2:0] spi1_csn;
|
||||
wire spi1_clk;
|
||||
wire spi1_mosi;
|
||||
wire spi1_miso;
|
||||
wire adc_clk;
|
||||
wire [127:0] rx_gt_data;
|
||||
wire adc_0_enable_a;
|
||||
|
|
@ -161,7 +167,10 @@ module system_top (
|
|||
wire adc_1_enable_b;
|
||||
wire [31:0] adc_1_data_b;
|
||||
|
||||
wire [15:0] ps_intrs;
|
||||
assign spi_csn = spi0_csn[0];
|
||||
assign spi_clk = spi0_clk;
|
||||
assign spi_mosi = spi0_mosi;
|
||||
assign spi0_miso = spi_miso;
|
||||
|
||||
// pack & unpack here
|
||||
|
||||
|
|
@ -241,9 +250,9 @@ module system_top (
|
|||
.ODIV2 ());
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf (
|
||||
.dt (gpio_t),
|
||||
.di (gpio_o),
|
||||
.do (gpio_i),
|
||||
.dt (gpio_t[14:0]),
|
||||
.di (gpio_o[14:0]),
|
||||
.do (gpio_i[14:0]),
|
||||
.dio (gpio_bd));
|
||||
|
||||
assign spi_adc_clk = spi_clk;
|
||||
|
|
@ -257,30 +266,30 @@ module system_top (
|
|||
.spi_sdio (spi_sdio));
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.DDR_addr (DDR_addr),
|
||||
.DDR_ba (DDR_ba),
|
||||
.DDR_cas_n (DDR_cas_n),
|
||||
.DDR_ck_n (DDR_ck_n),
|
||||
.DDR_ck_p (DDR_ck_p),
|
||||
.DDR_cke (DDR_cke),
|
||||
.DDR_cs_n (DDR_cs_n),
|
||||
.DDR_dm (DDR_dm),
|
||||
.DDR_dq (DDR_dq),
|
||||
.DDR_dqs_n (DDR_dqs_n),
|
||||
.DDR_dqs_p (DDR_dqs_p),
|
||||
.DDR_odt (DDR_odt),
|
||||
.DDR_ras_n (DDR_ras_n),
|
||||
.DDR_reset_n (DDR_reset_n),
|
||||
.DDR_we_n (DDR_we_n),
|
||||
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
|
||||
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
|
||||
.FIXED_IO_mio (FIXED_IO_mio),
|
||||
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
|
||||
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
|
||||
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
|
||||
.GPIO_I (gpio_i),
|
||||
.GPIO_O (gpio_o),
|
||||
.GPIO_T (gpio_t),
|
||||
.ddr_addr (ddr_addr),
|
||||
.ddr_ba (ddr_ba),
|
||||
.ddr_cas_n (ddr_cas_n),
|
||||
.ddr_ck_n (ddr_ck_n),
|
||||
.ddr_ck_p (ddr_ck_p),
|
||||
.ddr_cke (ddr_cke),
|
||||
.ddr_cs_n (ddr_cs_n),
|
||||
.ddr_dm (ddr_dm),
|
||||
.ddr_dq (ddr_dq),
|
||||
.ddr_dqs_n (ddr_dqs_n),
|
||||
.ddr_dqs_p (ddr_dqs_p),
|
||||
.ddr_odt (ddr_odt),
|
||||
.ddr_ras_n (ddr_ras_n),
|
||||
.ddr_reset_n (ddr_reset_n),
|
||||
.ddr_we_n (ddr_we_n),
|
||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
||||
.fixed_io_mio (fixed_io_mio),
|
||||
.fixed_io_ps_clk (fixed_io_ps_clk),
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb),
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
.adc_0_data_a (adc_0_data_a),
|
||||
.adc_0_data_b (adc_0_data_b),
|
||||
.adc_0_enable_a (adc_0_enable_a),
|
||||
|
|
@ -307,22 +316,18 @@ module system_top (
|
|||
.hdmi_vsync (hdmi_vsync),
|
||||
.iic_main_scl_io (iic_scl),
|
||||
.iic_main_sda_io (iic_sda),
|
||||
.ps_intr_0 (ps_intrs[0]),
|
||||
.ps_intr_1 (ps_intrs[1]),
|
||||
.ps_intr_2 (ps_intrs[2]),
|
||||
.ps_intr_3 (ps_intrs[3]),
|
||||
.ps_intr_4 (ps_intrs[4]),
|
||||
.ps_intr_5 (ps_intrs[5]),
|
||||
.ps_intr_6 (ps_intrs[6]),
|
||||
.ps_intr_7 (ps_intrs[7]),
|
||||
.ps_intr_8 (ps_intrs[8]),
|
||||
.ps_intr_9 (ps_intrs[9]),
|
||||
.ps_intr_10 (ps_intrs[10]),
|
||||
.ps_intr_11 (ps_intrs[11]),
|
||||
.ps_intr_12 (ps_intrs[12]),
|
||||
.ps_intr_13 (ps_intrs[13]),
|
||||
.ad9250_0_dma_intr (ps_intrs[13]),
|
||||
.ad9250_1_dma_intr (ps_intrs[12]),
|
||||
.ps_intr_00 (1'b0),
|
||||
.ps_intr_01 (1'b0),
|
||||
.ps_intr_02 (1'b0),
|
||||
.ps_intr_03 (1'b0),
|
||||
.ps_intr_04 (1'b0),
|
||||
.ps_intr_05 (1'b0),
|
||||
.ps_intr_06 (1'b0),
|
||||
.ps_intr_07 (1'b0),
|
||||
.ps_intr_08 (1'b0),
|
||||
.ps_intr_09 (1'b0),
|
||||
.ps_intr_10 (1'b0),
|
||||
.ps_intr_11 (1'b0),
|
||||
.rx_data_n (rx_data_n),
|
||||
.rx_data_p (rx_data_p),
|
||||
.rx_gt_data (rx_gt_data),
|
||||
|
|
@ -332,13 +337,24 @@ module system_top (
|
|||
.rx_sync (rx_sync),
|
||||
.rx_sysref (rx_sysref),
|
||||
.spdif (spdif),
|
||||
.spi_clk_i (1'b0),
|
||||
.spi_clk_o (spi_clk),
|
||||
.spi_csn_i (1'b1),
|
||||
.spi_csn_o (spi_csn),
|
||||
.spi_sdi_i (spi_miso),
|
||||
.spi_sdo_i (1'b0),
|
||||
.spi_sdo_o (spi_mosi));
|
||||
.spi0_clk_i (spi0_clk),
|
||||
.spi0_clk_o (spi0_clk),
|
||||
.spi0_csn_0_o (spi0_csn[0]),
|
||||
.spi0_csn_1_o (spi0_csn[1]),
|
||||
.spi0_csn_2_o (spi0_csn[2]),
|
||||
.spi0_csn_i (1'b1),
|
||||
.spi0_sdi_i (spi0_miso),
|
||||
.spi0_sdo_i (spi0_mosi),
|
||||
.spi0_sdo_o (spi0_mosi),
|
||||
.spi1_clk_i (spi1_clk),
|
||||
.spi1_clk_o (spi1_clk),
|
||||
.spi1_csn_0_o (spi1_csn[0]),
|
||||
.spi1_csn_1_o (spi1_csn[1]),
|
||||
.spi1_csn_2_o (spi1_csn[2]),
|
||||
.spi1_csn_i (1'b1),
|
||||
.spi1_sdi_i (1'b1),
|
||||
.spi1_sdo_i (spi1_mosi),
|
||||
.spi1_sdo_o (spi1_mosi));
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue