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constraints: up_xfer_cntrl and up_xfer_status have its own constraints 

The up_xfer_cntrl and up_xfer_status modules have its own constraints files
in library/xilinx/common. Each IP which has an instance of these
modules, have to use these constraints files.

The following IPs were modified:
  - axi_adc_decimate
  - axi_adc_trigger
  - axi_dac_interpolate
  - axi_logic_analyzer
main
Adrian Costina 2018-02-28 10:05:15 +00:00 committed by István Csomortáni
parent c81254200f
commit d3bfb33871
12 changed files with 21 additions and 58 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
library/axi_adc_decimate/Makefile
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@ -10,8 +10,8 @@ M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += axi_adc_decimate.v
M_DEPS += axi_adc_decimate_constr.xdc
M_DEPS += axi_adc_decimate_filter.v
M_DEPS += axi_adc_decimate_ip.tcl
M_DEPS += axi_adc_decimate_reg.v

7
library/axi_adc_decimate/axi_adc_decimate_constr.xdc
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@ -1,7 +0,0 @@
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_state*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_toggle*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_data* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}]

2
library/axi_adc_decimate/axi_adc_decimate_ip.tcl
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@ -8,7 +8,7 @@ adi_ip_files axi_adc_decimate [list \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/ad_iqcor.v" \
"axi_adc_decimate_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"fir_decim.v" \
"cic_decim.v" \
"axi_adc_decimate_filter.v" \

1
library/axi_adc_trigger/Makefile
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@ -9,6 +9,7 @@ M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += axi_adc_trigger.v
M_DEPS += axi_adc_trigger_constr.xdc
M_DEPS += axi_adc_trigger_ip.tcl

15
library/axi_adc_trigger/axi_adc_trigger_constr.xdc
View File

@ -1,14 +1,11 @@
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_state*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_toggle*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_a_d*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_b_d*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_triggered_d*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_triggered_reset_d*}]
set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_data* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *trigger_a_d1_reg* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *trigger_b_d1_reg* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_d1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_reset_d1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *trigger_a_d1_reg* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *trigger_b_d1_reg* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_d1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_reset_d1* && IS_SEQUENTIAL}]

1
library/axi_adc_trigger/axi_adc_trigger_ip.tcl
View File

@ -7,6 +7,7 @@ adi_ip_create axi_adc_trigger
adi_ip_files axi_adc_trigger [list \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"axi_adc_trigger_constr.xdc" \
"axi_adc_trigger_reg.v" \
"axi_adc_trigger.v" ]

2
library/axi_dac_interpolate/Makefile
View File

@ -11,8 +11,8 @@ M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += ../xilinx/common/ad_mul.v
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += axi_dac_interpolate.v
M_DEPS += axi_dac_interpolate_constr.xdc
M_DEPS += axi_dac_interpolate_filter.v
M_DEPS += axi_dac_interpolate_ip.tcl
M_DEPS += axi_dac_interpolate_reg.v

9
library/axi_dac_interpolate/axi_dac_interpolate_constr.xdc
View File

@ -1,9 +0,0 @@
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_state*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_toggle*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_data* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}]

2
library/axi_dac_interpolate/axi_dac_interpolate_ip.tcl
View File

@ -9,7 +9,7 @@ adi_ip_files axi_dac_interpolate [list \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/ad_iqcor.v" \
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
"axi_dac_interpolate_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"cic_interp.v" \
"fir_interp.v" \
"axi_dac_interpolate_reg.v" \

3
library/axi_logic_analyzer/Makefile
View File

@ -11,6 +11,9 @@ M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += ../xilinx/common/ad_rst_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
M_DEPS += axi_logic_analyzer.v
M_DEPS += axi_logic_analyzer_constr.xdc
M_DEPS += axi_logic_analyzer_ip.tcl

32
library/axi_logic_analyzer/axi_logic_analyzer_constr.xdc
View File

@ -1,33 +1,7 @@
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_state*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_toggle*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_state*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *ad_rst_sync*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_triggered_d*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_triggered_reset_d*}]
set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *up_xfer_toggle_m1_reg* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_data* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *downsampler_counter_* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *data_r_reg* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *dac_read_reg* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_data* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *up_data_status* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *d_xfer_state_m1_reg* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *trigger_m1_reg* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg* && IS_SEQUENTIAL}]
set_false_path -to [get_pins BUFGMUX_CTRL_inst/S*]
set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_d1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_reset_d1* && IS_SEQUENTIAL}]

3
library/axi_logic_analyzer/axi_logic_analyzer_ip.tcl
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@ -9,6 +9,9 @@ adi_ip_files axi_logic_analyzer [list \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
"axi_logic_analyzer_constr.xdc" \
"axi_logic_analyzer_reg.v" \
"axi_logic_analyzer_trigger.v" \