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avl_adxcfg- ip/phy split

main
Rejeesh Kutty 2016-09-12 14:45:03 -04:00
parent 9159e31244
commit d30ffdb7e9
2 changed files with 106 additions and 600 deletions
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639
library/altera/avl_adxcfg/avl_adxcfg.v
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@ -46,593 +46,116 @@ module avl_adxcfg (
input rcfg_in_read_0,
input rcfg_in_write_0,
input [11:0] rcfg_in_address_0,
input [ 9:0] rcfg_in_address_0,
input [31:0] rcfg_in_writedata_0,
output [31:0] rcfg_in_readdata_0,
output rcfg_in_waitrequest_0,
output rcfg_out_read_0,
output rcfg_out_write_0,
output [11:0] rcfg_out_address_0,
output [31:0] rcfg_out_writedata_0,
input [31:0] rcfg_out_readdata_0,
input rcfg_out_waitrequest_0,
input rcfg_in_read_1,
input rcfg_in_write_1,
input [11:0] rcfg_in_address_1,
input [ 9:0] rcfg_in_address_1,
input [31:0] rcfg_in_writedata_1,
output [31:0] rcfg_in_readdata_1,
output rcfg_in_waitrequest_1,
output rcfg_out_read_0,
output rcfg_out_write_0,
output [ 9:0] rcfg_out_address_0,
output [31:0] rcfg_out_writedata_0,
input [31:0] rcfg_out_readdata_0,
input rcfg_out_waitrequest_0,
output rcfg_out_read_1,
output rcfg_out_write_1,
output [11:0] rcfg_out_address_1,
output [ 9:0] rcfg_out_address_1,
output [31:0] rcfg_out_writedata_1,
input [31:0] rcfg_out_readdata_1,
input rcfg_out_waitrequest_1,
input rcfg_in_read_2,
input rcfg_in_write_2,
input [11:0] rcfg_in_address_2,
input [31:0] rcfg_in_writedata_2,
output [31:0] rcfg_in_readdata_2,
output rcfg_in_waitrequest_2,
output rcfg_out_read_2,
output rcfg_out_write_2,
output [11:0] rcfg_out_address_2,
output [31:0] rcfg_out_writedata_2,
input [31:0] rcfg_out_readdata_2,
input rcfg_out_waitrequest_2,
input rcfg_in_read_3,
input rcfg_in_write_3,
input [11:0] rcfg_in_address_3,
input [31:0] rcfg_in_writedata_3,
output [31:0] rcfg_in_readdata_3,
output rcfg_in_waitrequest_3,
output rcfg_out_read_3,
output rcfg_out_write_3,
output [11:0] rcfg_out_address_3,
output [31:0] rcfg_out_writedata_3,
input [31:0] rcfg_out_readdata_3,
input rcfg_out_waitrequest_3,
input rcfg_in_read_4,
input rcfg_in_write_4,
input [11:0] rcfg_in_address_4,
input [31:0] rcfg_in_writedata_4,
output [31:0] rcfg_in_readdata_4,
output rcfg_in_waitrequest_4,
output rcfg_out_read_4,
output rcfg_out_write_4,
output [11:0] rcfg_out_address_4,
output [31:0] rcfg_out_writedata_4,
input [31:0] rcfg_out_readdata_4,
input rcfg_out_waitrequest_4,
input rcfg_in_read_5,
input rcfg_in_write_5,
input [11:0] rcfg_in_address_5,
input [31:0] rcfg_in_writedata_5,
output [31:0] rcfg_in_readdata_5,
output rcfg_in_waitrequest_5,
output rcfg_out_read_5,
output rcfg_out_write_5,
output [11:0] rcfg_out_address_5,
output [31:0] rcfg_out_writedata_5,
input [31:0] rcfg_out_readdata_5,
input rcfg_out_waitrequest_5,
input rcfg_in_read_6,
input rcfg_in_write_6,
input [11:0] rcfg_in_address_6,
input [31:0] rcfg_in_writedata_6,
output [31:0] rcfg_in_readdata_6,
output rcfg_in_waitrequest_6,
output rcfg_out_read_6,
output rcfg_out_write_6,
output [11:0] rcfg_out_address_6,
output [31:0] rcfg_out_writedata_6,
input [31:0] rcfg_out_readdata_6,
input rcfg_out_waitrequest_6,
input rcfg_in_read_7,
input rcfg_in_write_7,
input [11:0] rcfg_in_address_7,
input [31:0] rcfg_in_writedata_7,
output [31:0] rcfg_in_readdata_7,
output rcfg_in_waitrequest_7,
output rcfg_out_read_7,
output rcfg_out_write_7,
output [11:0] rcfg_out_address_7,
output [31:0] rcfg_out_writedata_7,
input [31:0] rcfg_out_readdata_7,
input rcfg_out_waitrequest_7);
input rcfg_out_waitrequest_1);
// internal registers
reg [11:0] rcfg_out_address = 'd0;
reg [31:0] rcfg_out_writedata = 'd0;
reg rcfg_out_iread_0 = 'd0;
reg rcfg_out_iwrite_0 = 'd0;
reg [31:0] rcfg_in_ireaddata_0 = 'd0;
reg rcfg_in_iwaitrequest_0 = 'd0;
reg rcfg_out_iread_1 = 'd0;
reg rcfg_out_iwrite_1 = 'd0;
reg [31:0] rcfg_in_ireaddata_1 = 'd0;
reg rcfg_in_iwaitrequest_1 = 'd0;
reg rcfg_out_iread_2 = 'd0;
reg rcfg_out_iwrite_2 = 'd0;
reg [31:0] rcfg_in_ireaddata_2 = 'd0;
reg rcfg_in_iwaitrequest_2 = 'd0;
reg rcfg_out_iread_3 = 'd0;
reg rcfg_out_iwrite_3 = 'd0;
reg [31:0] rcfg_in_ireaddata_3 = 'd0;
reg rcfg_in_iwaitrequest_3 = 'd0;
reg rcfg_out_iread_4 = 'd0;
reg rcfg_out_iwrite_4 = 'd0;
reg [31:0] rcfg_in_ireaddata_4 = 'd0;
reg rcfg_in_iwaitrequest_4 = 'd0;
reg rcfg_out_iread_5 = 'd0;
reg rcfg_out_iwrite_5 = 'd0;
reg [31:0] rcfg_in_ireaddata_5 = 'd0;
reg rcfg_in_iwaitrequest_5 = 'd0;
reg rcfg_out_iread_6 = 'd0;
reg rcfg_out_iwrite_6 = 'd0;
reg [31:0] rcfg_in_ireaddata_6 = 'd0;
reg rcfg_in_iwaitrequest_6 = 'd0;
reg rcfg_out_iread_7 = 'd0;
reg rcfg_out_iwrite_7 = 'd0;
reg [31:0] rcfg_in_ireaddata_7 = 'd0;
reg rcfg_in_iwaitrequest_7 = 'd0;
reg [ 3:0] rcfg_select = 'd0;
reg [ 1:0] rcfg_select = 'd0;
reg rcfg_read_int = 'd0;
reg rcfg_write_int = 'd0;
reg [ 9:0] rcfg_address_int = 'd0;
reg [31:0] rcfg_writedata_int = 'd0;
reg [31:0] rcfg_readdata_int = 'd0;
reg rcfg_waitrequest_int_0 = 'd0;
reg rcfg_waitrequest_int_1 = 'd0;
// internal signals
wire rcfg_in_req_0_s;
wire rcfg_in_req_1_s;
wire rcfg_in_req_2_s;
wire rcfg_in_req_3_s;
wire rcfg_in_req_4_s;
wire rcfg_in_req_5_s;
wire rcfg_in_req_6_s;
wire rcfg_in_req_7_s;
wire [31:0] rcfg_readdata_s;
wire rcfg_waitrequest_s;
// xcvr sharing requires same bus with ONLY different write/read signals
// xcvr sharing requires same bus (sw must make sure they are mutually exclusive access).
assign rcfg_out_address_0 = rcfg_out_address;
assign rcfg_out_writedata_0 = rcfg_out_writedata;
assign rcfg_out_address_1 = rcfg_out_address;
assign rcfg_out_writedata_1 = rcfg_out_writedata;
assign rcfg_out_address_2 = rcfg_out_address;
assign rcfg_out_writedata_2 = rcfg_out_writedata;
assign rcfg_out_address_3 = rcfg_out_address;
assign rcfg_out_writedata_3 = rcfg_out_writedata;
assign rcfg_out_address_4 = rcfg_out_address;
assign rcfg_out_writedata_4 = rcfg_out_writedata;
assign rcfg_out_address_5 = rcfg_out_address;
assign rcfg_out_writedata_5 = rcfg_out_writedata;
assign rcfg_out_address_6 = rcfg_out_address;
assign rcfg_out_writedata_6 = rcfg_out_writedata;
assign rcfg_out_address_7 = rcfg_out_address;
assign rcfg_out_writedata_7 = rcfg_out_writedata;
assign rcfg_out_read_0 = rcfg_read_int;
assign rcfg_out_write_0 = rcfg_write_int;
assign rcfg_out_address_0 = rcfg_address_int;
assign rcfg_out_writedata_0 = rcfg_writedata_int;
assign rcfg_out_read_1 = rcfg_read_int;
assign rcfg_out_write_1 = rcfg_write_int;
assign rcfg_out_address_1 = rcfg_address_int;
assign rcfg_out_writedata_1 = rcfg_writedata_int;
assign rcfg_in_readdata_0 = rcfg_readdata_int;
assign rcfg_in_readdata_1 = rcfg_readdata_int;
assign rcfg_in_waitrequest_0 = rcfg_waitrequest_int_0;
assign rcfg_in_waitrequest_1 = rcfg_waitrequest_int_1;
assign rcfg_readdata_s = rcfg_out_readdata_1 & rcfg_out_readdata_0;
assign rcfg_waitrequest_s = rcfg_out_waitrequest_1 & rcfg_out_waitrequest_0;
always @(negedge rcfg_reset_n or posedge rcfg_clk) begin
if (rcfg_reset_n == 0) begin
rcfg_out_address <= 12'd0;
rcfg_out_writedata <= 32'd0;
rcfg_select <= 2'd0;
rcfg_read_int <= 1'd0;
rcfg_write_int <= 1'd0;
rcfg_address_int <= 10'd0;
rcfg_writedata_int <= 32'd0;
rcfg_readdata_int = 32'd0;
rcfg_waitrequest_int_0 <= 1'b1;
rcfg_waitrequest_int_1 <= 1'b1;
end else begin
case (rcfg_select)
4'h8: begin
rcfg_out_address <= rcfg_in_address_0;
rcfg_out_writedata <= rcfg_in_writedata_0;
if (rcfg_select[1] == 1'b1) begin
if (rcfg_waitrequest_s == 1'b0) begin
rcfg_select <= 2'd0;
rcfg_read_int <= 1'b0;
rcfg_write_int <= 1'b0;
rcfg_address_int <= 10'd0;
rcfg_writedata_int <= 32'd0;
end
4'h9: begin
rcfg_out_address <= rcfg_in_address_1;
rcfg_out_writedata <= rcfg_in_writedata_1;
end
4'ha: begin
rcfg_out_address <= rcfg_in_address_2;
rcfg_out_writedata <= rcfg_in_writedata_2;
end
4'hb: begin
rcfg_out_address <= rcfg_in_address_3;
rcfg_out_writedata <= rcfg_in_writedata_3;
end
4'hc: begin
rcfg_out_address <= rcfg_in_address_4;
rcfg_out_writedata <= rcfg_in_writedata_4;
end
4'hd: begin
rcfg_out_address <= rcfg_in_address_5;
rcfg_out_writedata <= rcfg_in_writedata_5;
end
4'he: begin
rcfg_out_address <= rcfg_in_address_6;
rcfg_out_writedata <= rcfg_in_writedata_6;
end
4'hf: begin
rcfg_out_address <= rcfg_in_address_7;
rcfg_out_writedata <= rcfg_in_writedata_7;
end
default: begin
rcfg_out_address <= 12'd0;
rcfg_out_writedata <= 32'd0;
end
endcase
end
end
assign rcfg_out_read_0 = rcfg_out_iread_0;
assign rcfg_out_write_0 = rcfg_out_iwrite_0;
assign rcfg_in_readdata_0 = rcfg_in_ireaddata_0;
assign rcfg_in_waitrequest_0 = rcfg_in_iwaitrequest_0;
assign rcfg_out_read_1 = rcfg_out_iread_1;
assign rcfg_out_write_1 = rcfg_out_iwrite_1;
assign rcfg_in_readdata_1 = rcfg_in_ireaddata_1;
assign rcfg_in_waitrequest_1 = rcfg_in_iwaitrequest_1;
assign rcfg_out_read_2 = rcfg_out_iread_2;
assign rcfg_out_write_2 = rcfg_out_iwrite_2;
assign rcfg_in_readdata_2 = rcfg_in_ireaddata_2;
assign rcfg_in_waitrequest_2 = rcfg_in_iwaitrequest_2;
assign rcfg_out_read_3 = rcfg_out_iread_3;
assign rcfg_out_write_3 = rcfg_out_iwrite_3;
assign rcfg_in_readdata_3 = rcfg_in_ireaddata_3;
assign rcfg_in_waitrequest_3 = rcfg_in_iwaitrequest_3;
assign rcfg_out_read_4 = rcfg_out_iread_4;
assign rcfg_out_write_4 = rcfg_out_iwrite_4;
assign rcfg_in_readdata_4 = rcfg_in_ireaddata_4;
assign rcfg_in_waitrequest_4 = rcfg_in_iwaitrequest_4;
assign rcfg_out_read_5 = rcfg_out_iread_5;
assign rcfg_out_write_5 = rcfg_out_iwrite_5;
assign rcfg_in_readdata_5 = rcfg_in_ireaddata_5;
assign rcfg_in_waitrequest_5 = rcfg_in_iwaitrequest_5;
assign rcfg_out_read_6 = rcfg_out_iread_6;
assign rcfg_out_write_6 = rcfg_out_iwrite_6;
assign rcfg_in_readdata_6 = rcfg_in_ireaddata_6;
assign rcfg_in_waitrequest_6 = rcfg_in_iwaitrequest_6;
assign rcfg_out_read_7 = rcfg_out_iread_7;
assign rcfg_out_write_7 = rcfg_out_iwrite_7;
assign rcfg_in_readdata_7 = rcfg_in_ireaddata_7;
assign rcfg_in_waitrequest_7 = rcfg_in_iwaitrequest_7;
always @(negedge rcfg_reset_n or posedge rcfg_clk) begin
if (rcfg_reset_n == 0) begin
rcfg_out_iread_0 <= 1'd0;
rcfg_out_iwrite_0 <= 1'd0;
rcfg_in_ireaddata_0 <= 32'd0;
rcfg_in_iwaitrequest_0 <= 1'd1;
rcfg_out_iread_1 <= 1'd0;
rcfg_out_iwrite_1 <= 1'd0;
rcfg_in_ireaddata_1 <= 32'd0;
rcfg_in_iwaitrequest_1 <= 1'd1;
rcfg_out_iread_2 <= 1'd0;
rcfg_out_iwrite_2 <= 1'd0;
rcfg_in_ireaddata_2 <= 32'd0;
rcfg_in_iwaitrequest_2 <= 1'd1;
rcfg_out_iread_3 <= 1'd0;
rcfg_out_iwrite_3 <= 1'd0;
rcfg_in_ireaddata_3 <= 32'd0;
rcfg_in_iwaitrequest_3 <= 1'd1;
rcfg_out_iread_4 <= 1'd0;
rcfg_out_iwrite_4 <= 1'd0;
rcfg_in_ireaddata_4 <= 32'd0;
rcfg_in_iwaitrequest_4 <= 1'd1;
rcfg_out_iread_5 <= 1'd0;
rcfg_out_iwrite_5 <= 1'd0;
rcfg_in_ireaddata_5 <= 32'd0;
rcfg_in_iwaitrequest_5 <= 1'd1;
rcfg_out_iread_6 <= 1'd0;
rcfg_out_iwrite_6 <= 1'd0;
rcfg_in_ireaddata_6 <= 32'd0;
rcfg_in_iwaitrequest_6 <= 1'd1;
rcfg_out_iread_7 <= 1'd0;
rcfg_out_iwrite_7 <= 1'd0;
rcfg_in_ireaddata_7 <= 32'd0;
rcfg_in_iwaitrequest_7 <= 1'd1;
end else begin
if (rcfg_select == 4'h8) begin
rcfg_out_iread_0 <= rcfg_in_read_0;
rcfg_out_iwrite_0 <= rcfg_in_write_0;
rcfg_in_ireaddata_0 <= rcfg_out_readdata_0;
rcfg_in_iwaitrequest_0 <= rcfg_out_waitrequest_0 | ~rcfg_in_req_0_s;
rcfg_readdata_int = rcfg_readdata_s;
rcfg_waitrequest_int_0 <= rcfg_waitrequest_s | rcfg_select[0];
rcfg_waitrequest_int_1 <= rcfg_waitrequest_s | ~rcfg_select[0];
end else if ((rcfg_in_read_0 == 1'b1) || (rcfg_in_write_0 == 1'b1)) begin
rcfg_select <= 2'b10;
rcfg_read_int <= rcfg_in_read_0;
rcfg_write_int <= rcfg_in_write_0;
rcfg_address_int <= rcfg_in_address_0;
rcfg_writedata_int <= rcfg_in_writedata_0;
rcfg_readdata_int = 32'd0;
rcfg_waitrequest_int_0 <= 1'b1;
rcfg_waitrequest_int_1 <= 1'b1;
end else if ((rcfg_in_read_1 == 1'b1) || (rcfg_in_write_1 == 1'b1)) begin
rcfg_select <= 2'b11;
rcfg_read_int <= rcfg_in_read_1;
rcfg_write_int <= rcfg_in_write_1;
rcfg_address_int <= rcfg_in_address_1;
rcfg_writedata_int <= rcfg_in_writedata_1;
rcfg_readdata_int = 32'd0;
rcfg_waitrequest_int_0 <= 1'b1;
rcfg_waitrequest_int_1 <= 1'b1;
end else begin
rcfg_out_iread_0 <= 1'd0;
rcfg_out_iwrite_0 <= 1'd0;
rcfg_in_ireaddata_0 <= 32'd0;
rcfg_in_iwaitrequest_0 <= 1'd1;
rcfg_select <= 2'd0;
rcfg_read_int <= 1'd0;
rcfg_write_int <= 1'd0;
rcfg_address_int <= 10'd0;
rcfg_writedata_int <= 32'd0;
rcfg_readdata_int = 32'd0;
rcfg_waitrequest_int_0 <= 1'b1;
rcfg_waitrequest_int_1 <= 1'b1;
end
if (rcfg_select == 4'h9) begin
rcfg_out_iread_1 <= rcfg_in_read_1;
rcfg_out_iwrite_1 <= rcfg_in_write_1;
rcfg_in_ireaddata_1 <= rcfg_out_readdata_1;
rcfg_in_iwaitrequest_1 <= rcfg_out_waitrequest_1 | ~rcfg_in_req_1_s;
end else begin
rcfg_out_iread_1 <= 1'd0;
rcfg_out_iwrite_1 <= 1'd0;
rcfg_in_ireaddata_1 <= 32'd0;
rcfg_in_iwaitrequest_1 <= 1'd1;
end
if (rcfg_select == 4'ha) begin
rcfg_out_iread_2 <= rcfg_in_read_2;
rcfg_out_iwrite_2 <= rcfg_in_write_2;
rcfg_in_ireaddata_2 <= rcfg_out_readdata_2;
rcfg_in_iwaitrequest_2 <= rcfg_out_waitrequest_2 | ~rcfg_in_req_2_s;
end else begin
rcfg_out_iread_2 <= 1'd0;
rcfg_out_iwrite_2 <= 1'd0;
rcfg_in_ireaddata_2 <= 32'd0;
rcfg_in_iwaitrequest_2 <= 1'd1;
end
if (rcfg_select == 4'hb) begin
rcfg_out_iread_3 <= rcfg_in_read_3;
rcfg_out_iwrite_3 <= rcfg_in_write_3;
rcfg_in_ireaddata_3 <= rcfg_out_readdata_3;
rcfg_in_iwaitrequest_3 <= rcfg_out_waitrequest_3 | ~rcfg_in_req_3_s;
end else begin
rcfg_out_iread_3 <= 1'd0;
rcfg_out_iwrite_3 <= 1'd0;
rcfg_in_ireaddata_3 <= 32'd0;
rcfg_in_iwaitrequest_3 <= 1'd1;
end
if (rcfg_select == 4'hc) begin
rcfg_out_iread_4 <= rcfg_in_read_4;
rcfg_out_iwrite_4 <= rcfg_in_write_4;
rcfg_in_ireaddata_4 <= rcfg_out_readdata_4;
rcfg_in_iwaitrequest_4 <= rcfg_out_waitrequest_4 | ~rcfg_in_req_4_s;
end else begin
rcfg_out_iread_4 <= 1'd0;
rcfg_out_iwrite_4 <= 1'd0;
rcfg_in_ireaddata_4 <= 32'd0;
rcfg_in_iwaitrequest_4 <= 1'd1;
end
if (rcfg_select == 4'hd) begin
rcfg_out_iread_5 <= rcfg_in_read_5;
rcfg_out_iwrite_5 <= rcfg_in_write_5;
rcfg_in_ireaddata_5 <= rcfg_out_readdata_5;
rcfg_in_iwaitrequest_5 <= rcfg_out_waitrequest_5 | ~rcfg_in_req_5_s;
end else begin
rcfg_out_iread_5 <= 1'd0;
rcfg_out_iwrite_5 <= 1'd0;
rcfg_in_ireaddata_5 <= 32'd0;
rcfg_in_iwaitrequest_5 <= 1'd1;
end
if (rcfg_select == 4'he) begin
rcfg_out_iread_6 <= rcfg_in_read_6;
rcfg_out_iwrite_6 <= rcfg_in_write_6;
rcfg_in_ireaddata_6 <= rcfg_out_readdata_6;
rcfg_in_iwaitrequest_6 <= rcfg_out_waitrequest_6 | ~rcfg_in_req_6_s;
end else begin
rcfg_out_iread_6 <= 1'd0;
rcfg_out_iwrite_6 <= 1'd0;
rcfg_in_ireaddata_6 <= 32'd0;
rcfg_in_iwaitrequest_6 <= 1'd1;
end
if (rcfg_select == 4'hf) begin
rcfg_out_iread_7 <= rcfg_in_read_7;
rcfg_out_iwrite_7 <= rcfg_in_write_7;
rcfg_in_ireaddata_7 <= rcfg_out_readdata_7;
rcfg_in_iwaitrequest_7 <= rcfg_out_waitrequest_7 | ~rcfg_in_req_7_s;
end else begin
rcfg_out_iread_7 <= 1'd0;
rcfg_out_iwrite_7 <= 1'd0;
rcfg_in_ireaddata_7 <= 32'd0;
rcfg_in_iwaitrequest_7 <= 1'd1;
end
end
end
assign rcfg_in_req_0_s = rcfg_in_read_0 | rcfg_in_write_0;
assign rcfg_in_req_1_s = rcfg_in_read_1 | rcfg_in_write_1;
assign rcfg_in_req_2_s = rcfg_in_read_2 | rcfg_in_write_2;
assign rcfg_in_req_3_s = rcfg_in_read_3 | rcfg_in_write_3;
assign rcfg_in_req_4_s = rcfg_in_read_4 | rcfg_in_write_4;
assign rcfg_in_req_5_s = rcfg_in_read_5 | rcfg_in_write_5;
assign rcfg_in_req_6_s = rcfg_in_read_6 | rcfg_in_write_6;
assign rcfg_in_req_7_s = rcfg_in_read_7 | rcfg_in_write_7;
always @(negedge rcfg_reset_n or posedge rcfg_clk) begin
if (rcfg_reset_n == 0) begin
rcfg_select <= 4'h0;
end else begin
case (rcfg_select)
4'h8: begin
if (rcfg_in_req_1_s == 1'b1) begin
rcfg_select <= 4'h9;
end else if (rcfg_in_req_2_s == 1'b1) begin
rcfg_select <= 4'ha;
end else if (rcfg_in_req_3_s == 1'b1) begin
rcfg_select <= 4'hb;
end else if (rcfg_in_req_4_s == 1'b1) begin
rcfg_select <= 4'hc;
end else if (rcfg_in_req_5_s == 1'b1) begin
rcfg_select <= 4'hd;
end else if (rcfg_in_req_6_s == 1'b1) begin
rcfg_select <= 4'he;
end else if (rcfg_in_req_7_s == 1'b1) begin
rcfg_select <= 4'hf;
end else if (rcfg_in_req_0_s == 1'b1) begin
rcfg_select <= 4'h8;
end else begin
rcfg_select <= 4'h0;
end
end
4'h9: begin
if (rcfg_in_req_2_s == 1'b1) begin
rcfg_select <= 4'ha;
end else if (rcfg_in_req_3_s == 1'b1) begin
rcfg_select <= 4'hb;
end else if (rcfg_in_req_4_s == 1'b1) begin
rcfg_select <= 4'hc;
end else if (rcfg_in_req_5_s == 1'b1) begin
rcfg_select <= 4'hd;
end else if (rcfg_in_req_6_s == 1'b1) begin
rcfg_select <= 4'he;
end else if (rcfg_in_req_7_s == 1'b1) begin
rcfg_select <= 4'hf;
end else if (rcfg_in_req_0_s == 1'b1) begin
rcfg_select <= 4'h8;
end else if (rcfg_in_req_1_s == 1'b1) begin
rcfg_select <= 4'h9;
end else begin
rcfg_select <= 4'h0;
end
end
4'ha: begin
if (rcfg_in_req_3_s == 1'b1) begin
rcfg_select <= 4'hb;
end else if (rcfg_in_req_4_s == 1'b1) begin
rcfg_select <= 4'hc;
end else if (rcfg_in_req_5_s == 1'b1) begin
rcfg_select <= 4'hd;
end else if (rcfg_in_req_6_s == 1'b1) begin
rcfg_select <= 4'he;
end else if (rcfg_in_req_7_s == 1'b1) begin
rcfg_select <= 4'hf;
end else if (rcfg_in_req_0_s == 1'b1) begin
rcfg_select <= 4'h8;
end else if (rcfg_in_req_1_s == 1'b1) begin
rcfg_select <= 4'h9;
end else if (rcfg_in_req_2_s == 1'b1) begin
rcfg_select <= 4'ha;
end else begin
rcfg_select <= 4'h0;
end
end
4'hb: begin
if (rcfg_in_req_4_s == 1'b1) begin
rcfg_select <= 4'hc;
end else if (rcfg_in_req_5_s == 1'b1) begin
rcfg_select <= 4'hd;
end else if (rcfg_in_req_6_s == 1'b1) begin
rcfg_select <= 4'he;
end else if (rcfg_in_req_7_s == 1'b1) begin
rcfg_select <= 4'hf;
end else if (rcfg_in_req_0_s == 1'b1) begin
rcfg_select <= 4'h8;
end else if (rcfg_in_req_1_s == 1'b1) begin
rcfg_select <= 4'h9;
end else if (rcfg_in_req_2_s == 1'b1) begin
rcfg_select <= 4'ha;
end else if (rcfg_in_req_3_s == 1'b1) begin
rcfg_select <= 4'hb;
end else begin
rcfg_select <= 4'h0;
end
end
4'hc: begin
if (rcfg_in_req_5_s == 1'b1) begin
rcfg_select <= 4'hd;
end else if (rcfg_in_req_6_s == 1'b1) begin
rcfg_select <= 4'he;
end else if (rcfg_in_req_7_s == 1'b1) begin
rcfg_select <= 4'hf;
end else if (rcfg_in_req_0_s == 1'b1) begin
rcfg_select <= 4'h8;
end else if (rcfg_in_req_1_s == 1'b1) begin
rcfg_select <= 4'h9;
end else if (rcfg_in_req_2_s == 1'b1) begin
rcfg_select <= 4'ha;
end else if (rcfg_in_req_3_s == 1'b1) begin
rcfg_select <= 4'hb;
end else if (rcfg_in_req_4_s == 1'b1) begin
rcfg_select <= 4'hc;
end else begin
rcfg_select <= 4'h0;
end
end
4'hd: begin
if (rcfg_in_req_6_s == 1'b1) begin
rcfg_select <= 4'he;
end else if (rcfg_in_req_7_s == 1'b1) begin
rcfg_select <= 4'hf;
end else if (rcfg_in_req_0_s == 1'b1) begin
rcfg_select <= 4'h8;
end else if (rcfg_in_req_1_s == 1'b1) begin
rcfg_select <= 4'h9;
end else if (rcfg_in_req_2_s == 1'b1) begin
rcfg_select <= 4'ha;
end else if (rcfg_in_req_3_s == 1'b1) begin
rcfg_select <= 4'hb;
end else if (rcfg_in_req_4_s == 1'b1) begin
rcfg_select <= 4'hc;
end else if (rcfg_in_req_5_s == 1'b1) begin
rcfg_select <= 4'hd;
end else begin
rcfg_select <= 4'h0;
end
end
4'he: begin
if (rcfg_in_req_7_s == 1'b1) begin
rcfg_select <= 4'hf;
end else if (rcfg_in_req_0_s == 1'b1) begin
rcfg_select <= 4'h8;
end else if (rcfg_in_req_1_s == 1'b1) begin
rcfg_select <= 4'h9;
end else if (rcfg_in_req_2_s == 1'b1) begin
rcfg_select <= 4'ha;
end else if (rcfg_in_req_3_s == 1'b1) begin
rcfg_select <= 4'hb;
end else if (rcfg_in_req_4_s == 1'b1) begin
rcfg_select <= 4'hc;
end else if (rcfg_in_req_5_s == 1'b1) begin
rcfg_select <= 4'hd;
end else if (rcfg_in_req_6_s == 1'b1) begin
rcfg_select <= 4'he;
end else begin
rcfg_select <= 4'h0;
end
end
4'hf: begin
if (rcfg_in_req_0_s == 1'b1) begin
rcfg_select <= 4'h8;
end else if (rcfg_in_req_1_s == 1'b1) begin
rcfg_select <= 4'h9;
end else if (rcfg_in_req_2_s == 1'b1) begin
rcfg_select <= 4'ha;
end else if (rcfg_in_req_3_s == 1'b1) begin
rcfg_select <= 4'hb;
end else if (rcfg_in_req_4_s == 1'b1) begin
rcfg_select <= 4'hc;
end else if (rcfg_in_req_5_s == 1'b1) begin
rcfg_select <= 4'hd;
end else if (rcfg_in_req_6_s == 1'b1) begin
rcfg_select <= 4'he;
end else if (rcfg_in_req_7_s == 1'b1) begin
rcfg_select <= 4'hf;
end else begin
rcfg_select <= 4'h0;
end
end
default: begin
if (rcfg_in_req_0_s == 1'b1) begin
rcfg_select <= 4'h8;
end else if (rcfg_in_req_1_s == 1'b1) begin
rcfg_select <= 4'h9;
end else if (rcfg_in_req_2_s == 1'b1) begin
rcfg_select <= 4'ha;
end else if (rcfg_in_req_3_s == 1'b1) begin
rcfg_select <= 4'hb;
end else if (rcfg_in_req_4_s == 1'b1) begin
rcfg_select <= 4'hc;
end else if (rcfg_in_req_5_s == 1'b1) begin
rcfg_select <= 4'hd;
end else if (rcfg_in_req_6_s == 1'b1) begin
rcfg_select <= 4'he;
end else if (rcfg_in_req_7_s == 1'b1) begin
rcfg_select <= 4'hf;
end else begin
rcfg_select <= 4'h0;
end
end
endcase
end
end

67
library/altera/avl_adxcfg/avl_adxcfg_hw.tcl
View File

@ -6,7 +6,6 @@ set_module_property DESCRIPTION "Avalon ADXCFG Core"
set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME avl_adxcfg
set_module_property ELABORATION_CALLBACK p_avl_adxcfg
# files
@ -14,14 +13,6 @@ add_fileset quartus_synth QUARTUS_SYNTH "" ""
set_fileset_property quartus_synth TOP_LEVEL avl_adxcfg
add_fileset_file avl_adxcfg.v VERILOG PATH avl_adxcfg.v TOP_LEVEL_FILE
# parameters
add_parameter NUM_OF_CORES INTEGER 0
set_parameter_property NUM_OF_CORES DISPLAY_NAME NUM_OF_CORES
set_parameter_property NUM_OF_CORES TYPE INTEGER
set_parameter_property NUM_OF_CORES UNITS None
set_parameter_property NUM_OF_CORES HDL_PARAMETER false
# reconfiguration interfaces
add_interface rcfg_clk clock sink
@ -31,42 +22,34 @@ add_interface rcfg_reset_n reset end
set_interface_property rcfg_reset_n associatedClock rcfg_clk
add_interface_port rcfg_reset_n rcfg_reset_n reset_n Input 1
proc p_avl_adxcfg {} {
for {set n 0} {$n < 2} {incr n} {
set m_num_of_cores [get_parameter_value NUM_OF_CORES]
add_interface rcfg_s${n} avalon slave
add_interface rcfg_m${n} avalon master
if {$m_num_of_cores > 8} {
set m_num_of_cores 8
}
add_interface_port rcfg_s${n} rcfg_in_read_${n} read Input 1
add_interface_port rcfg_s${n} rcfg_in_write_${n} write Input 1
add_interface_port rcfg_s${n} rcfg_in_address_${n} address Input 10
add_interface_port rcfg_s${n} rcfg_in_writedata_${n} writedata Input 32
add_interface_port rcfg_s${n} rcfg_in_readdata_${n} readdata Output 32
add_interface_port rcfg_s${n} rcfg_in_waitrequest_${n} waitrequest Output 1
add_interface_port rcfg_m${n} rcfg_out_read_${n} read Output 1
add_interface_port rcfg_m${n} rcfg_out_write_${n} write Output 1
add_interface_port rcfg_m${n} rcfg_out_address_${n} address Output 10
add_interface_port rcfg_m${n} rcfg_out_writedata_${n} writedata Output 32
add_interface_port rcfg_m${n} rcfg_out_readdata_${n} readdata Input 32
add_interface_port rcfg_m${n} rcfg_out_waitrequest_${n} waitrequest Input 1
for {set n 0} {$n < $m_num_of_cores} {incr n} {
add_interface rcfg_s${n} avalon slave
add_interface rcfg_m${n} avalon master
add_interface_port rcfg_s${n} rcfg_in_read_${n} read Input 1
add_interface_port rcfg_s${n} rcfg_in_write_${n} write Input 1
add_interface_port rcfg_s${n} rcfg_in_address_${n} address Input 12
add_interface_port rcfg_s${n} rcfg_in_writedata_${n} writedata Input 32
add_interface_port rcfg_s${n} rcfg_in_readdata_${n} readdata Output 32
add_interface_port rcfg_s${n} rcfg_in_waitrequest_${n} waitrequest Output 1
add_interface_port rcfg_m${n} rcfg_out_read_${n} read Output 1
add_interface_port rcfg_m${n} rcfg_out_write_${n} write Output 1
add_interface_port rcfg_m${n} rcfg_out_address_${n} address Output 12
add_interface_port rcfg_m${n} rcfg_out_writedata_${n} writedata Output 32
add_interface_port rcfg_m${n} rcfg_out_readdata_${n} readdata Input 32
add_interface_port rcfg_m${n} rcfg_out_waitrequest_${n} waitrequest Input 1
set_interface_property rcfg_s${n} associatedClock rcfg_clk
set_interface_property rcfg_s${n} associatedReset rcfg_reset_n
set_interface_property rcfg_s${n} addressUnits WORDS
set_interface_property rcfg_s${n} burstCountUnits WORDS
set_interface_property rcfg_s${n} explicitAddressSpan 0
set_interface_property rcfg_m${n} associatedClock rcfg_clk
set_interface_property rcfg_m${n} associatedReset rcfg_reset_n
set_interface_property rcfg_m${n} addressUnits WORDS
set_interface_property rcfg_m${n} burstCountUnits WORDS
}
set_interface_property rcfg_s${n} associatedClock rcfg_clk
set_interface_property rcfg_s${n} associatedReset rcfg_reset_n
set_interface_property rcfg_s${n} addressUnits WORDS
set_interface_property rcfg_s${n} burstCountUnits WORDS
set_interface_property rcfg_s${n} explicitAddressSpan 0
set_interface_property rcfg_m${n} associatedClock rcfg_clk
set_interface_property rcfg_m${n} associatedReset rcfg_reset_n
set_interface_property rcfg_m${n} addressUnits WORDS
set_interface_property rcfg_m${n} burstCountUnits WORDS
}