daq3/a10gx: updates
parent
d10dd78094
commit
d2fc64d130
|
@ -9,14 +9,6 @@
|
|||
categories="System" />
|
||||
<parameter name="bonusData"><![CDATA[bonusData
|
||||
{
|
||||
element $${FILENAME}
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element a10gx_base
|
||||
{
|
||||
datum _sortIndex
|
||||
|
@ -58,7 +50,7 @@
|
|||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "212992";
|
||||
value = "229376";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
@ -74,7 +66,7 @@
|
|||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "196608";
|
||||
value = "212992";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
@ -86,6 +78,54 @@
|
|||
type = "String";
|
||||
}
|
||||
}
|
||||
element daq3.xcvr_core_jesd204_rx_s_avl
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "254976";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element daq3.xcvr_core_jesd204_tx_s_avl
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "253952";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element daq3.xcvr_core_reconfig_s_avl
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "196608";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element daq3.xcvr_rx_pll_reconfig_s_avl
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "251904";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element daq3.xcvr_tx_lane_pll_s_avl
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "245760";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element daq3.xcvr_tx_pll_reconfig_s_avl
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "249856";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element sys_clk
|
||||
{
|
||||
datum _sortIndex
|
||||
|
@ -321,7 +361,7 @@
|
|||
}
|
||||
]]></parameter>
|
||||
<parameter name="clockCrossingAdapter" value="FIFO" />
|
||||
<parameter name="device" value="10AX115S3F45I2SGE2" />
|
||||
<parameter name="device" value="10AX115S3F45E2SGE3" />
|
||||
<parameter name="deviceFamily" value="Arria 10" />
|
||||
<parameter name="deviceSpeedGrade" value="2" />
|
||||
<parameter name="fabricMode" value="QSYS" />
|
||||
|
@ -426,14 +466,14 @@
|
|||
type="reset"
|
||||
dir="end" />
|
||||
<module name="a10gx_base" kind="a10gx_system_bd" version="1.0" enabled="1">
|
||||
<parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
|
||||
<parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
|
||||
<parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
|
||||
<parameter name="AUTO_GENERATION_ID" value="0" />
|
||||
<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="6" />
|
||||
<parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
|
||||
<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="6" />
|
||||
<parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='daq3_axi_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='daq3_axi_ad9680_core.s_axi' start='0x10000' end='0x20000' /><slave name='daq3_axi_ad9152_core.s_axi' start='0x20000' end='0x30000' /><slave name='daq3_axi_ad9680_dma.s_axi' start='0x30000' end='0x34000' /><slave name='daq3_axi_ad9152_dma.s_axi' start='0x34000' end='0x38000' /></address-map>]]></parameter>
|
||||
<parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='daq3_axi_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='daq3_axi_ad9680_core.s_axi' start='0x10000' end='0x20000' /><slave name='daq3_axi_ad9152_core.s_axi' start='0x20000' end='0x30000' /><slave name='daq3_xcvr_core.reconfig_avmm' start='0x30000' end='0x34000' /><slave name='daq3_axi_ad9680_dma.s_axi' start='0x34000' end='0x38000' /><slave name='daq3_axi_ad9152_dma.s_axi' start='0x38000' end='0x3C000' /><slave name='daq3_xcvr_tx_lane_pll.reconfig_avmm0' start='0x3C000' end='0x3D000' /><slave name='daq3_xcvr_tx_pll_reconfig.mgmt_avalon_slave' start='0x3D000' end='0x3D800' /><slave name='daq3_xcvr_rx_pll_reconfig.mgmt_avalon_slave' start='0x3D800' end='0x3E000' /><slave name='daq3_xcvr_core.jesd204_tx_avs' start='0x3E000' end='0x3E400' /><slave name='daq3_xcvr_core.jesd204_rx_avs' start='0x3E400' end='0x3E800' /></address-map>]]></parameter>
|
||||
<parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 18" />
|
||||
<parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_CLOCK_DOMAIN" value="1" />
|
||||
<parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_CLOCK_RATE" value="0" />
|
||||
|
@ -445,15 +485,15 @@
|
|||
<parameter name="AUTO_UNIQUE_ID">$${FILENAME}_a10gx_base</parameter>
|
||||
</module>
|
||||
<module name="daq3" kind="daq3_bd" version="1.0" enabled="1">
|
||||
<parameter name="AUTO_AXI_AD9152_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
|
||||
<parameter name="AUTO_AXI_AD9152_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
|
||||
<parameter
|
||||
name="AUTO_AXI_AD9152_DMA_M_AXI_ADDRESS_WIDTH"
|
||||
value="AddressWidth = 29" />
|
||||
<parameter name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
|
||||
<parameter name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
|
||||
<parameter
|
||||
name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_WIDTH"
|
||||
value="AddressWidth = 29" />
|
||||
<parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
|
||||
<parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
|
||||
<parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
|
||||
<parameter name="AUTO_GENERATION_ID" value="0" />
|
||||
|
@ -471,7 +511,7 @@
|
|||
<parameter name="AUTO_TX_REF_CLK_RESET_DOMAIN" value="5" />
|
||||
<parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_daq3" />
|
||||
</module>
|
||||
<module name="sys_clk" kind="clock_source" version="15.0" enabled="1">
|
||||
<module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
|
||||
<parameter name="clockFrequency" value="100000000" />
|
||||
<parameter name="clockFrequencyKnown" value="true" />
|
||||
<parameter name="inputClockFrequency" value="0" />
|
||||
|
@ -479,7 +519,7 @@
|
|||
</module>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.0"
|
||||
version="15.1"
|
||||
start="daq3.axi_ad9152_dma_m_axi"
|
||||
end="a10gx_base.sys_mem_s_avl">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
|
@ -488,7 +528,7 @@
|
|||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.0"
|
||||
version="15.1"
|
||||
start="daq3.axi_ad9680_dma_m_axi"
|
||||
end="a10gx_base.sys_mem_s_avl">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
|
@ -497,7 +537,7 @@
|
|||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.0"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq3.axi_ad9152_core_s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
|
@ -506,16 +546,16 @@
|
|||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.0"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq3.axi_ad9152_dma_s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00034000" />
|
||||
<parameter name="baseAddress" value="0x00038000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.0"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq3.axi_ad9680_core_s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
|
@ -524,16 +564,16 @@
|
|||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.0"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq3.axi_ad9680_dma_s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00030000" />
|
||||
<parameter name="baseAddress" value="0x00034000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.0"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq3.axi_jesd_xcvr_s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
|
@ -541,43 +581,97 @@
|
|||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.0"
|
||||
start="sys_clk.clk"
|
||||
end="a10gx_base.sys_clk" />
|
||||
<connection kind="clock" version="15.0" start="sys_clk.clk" end="daq3.sys_clk" />
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq3.xcvr_core_jesd204_rx_s_avl">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0003e400" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq3.xcvr_core_jesd204_tx_s_avl">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0003e000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq3.xcvr_core_reconfig_s_avl">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00030000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq3.xcvr_rx_pll_reconfig_s_avl">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0003d800" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq3.xcvr_tx_lane_pll_s_avl">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0003c000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq3.xcvr_tx_pll_reconfig_s_avl">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0003d000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.0"
|
||||
version="15.1"
|
||||
start="sys_clk.clk"
|
||||
end="a10gx_base.sys_clk" />
|
||||
<connection kind="clock" version="15.1" start="sys_clk.clk" end="daq3.sys_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="a10gx_base.mem_clk"
|
||||
end="daq3.mem_clk" />
|
||||
<connection
|
||||
kind="interrupt"
|
||||
version="15.0"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_intr"
|
||||
end="daq3.axi_ad9152_dma_intr">
|
||||
<parameter name="irqNumber" value="1" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="interrupt"
|
||||
version="15.0"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_intr"
|
||||
end="daq3.axi_ad9680_dma_intr">
|
||||
<parameter name="irqNumber" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.0"
|
||||
version="15.1"
|
||||
start="sys_clk.clk_reset"
|
||||
end="a10gx_base.sys_rst" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.0"
|
||||
version="15.1"
|
||||
start="sys_clk.clk_reset"
|
||||
end="daq3.sys_rst" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.0"
|
||||
version="15.1"
|
||||
start="a10gx_base.mem_rst"
|
||||
end="daq3.mem_rst" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
|
||||
|
|
|
@ -14,3 +14,30 @@ set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
|
|||
i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_1 \
|
||||
i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_2}]
|
||||
|
||||
set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
|
||||
i_system_bd|a10gx_base|sys_ddr3_cntrl_core_nios_clk}]
|
||||
|
||||
set_false_path -from [get_clocks {sys_clk_100mhz}]\
|
||||
-through [get_nets *altera_jesd204_tx_csr_inst*]\
|
||||
-to [get_clocks {i_system_bd|daq3|xcvr_tx_pll|outclk0}]
|
||||
|
||||
set_false_path -from [get_clocks {sys_clk_100mhz}]\
|
||||
-through [get_nets *altera_jesd204_tx_ctl_inst*]\
|
||||
-to [get_clocks {i_system_bd|daq3|xcvr_tx_pll|outclk0}]
|
||||
|
||||
set_false_path -from [get_clocks {sys_clk_100mhz}]\
|
||||
-through [get_nets *altera_jesd204_rx_csr_inst*]\
|
||||
-to [get_clocks {i_system_bd|daq3|xcvr_rx_pll|outclk0}]
|
||||
|
||||
set_false_path -from [get_clocks {i_system_bd|daq3|xcvr_tx_pll|outclk0}]\
|
||||
-through [get_nets *altera_jesd204_tx_csr_inst*]\
|
||||
-to [get_clocks {sys_clk_100mhz}]
|
||||
|
||||
set_false_path -from [get_clocks {i_system_bd|daq3|xcvr_tx_pll|outclk0}]\
|
||||
-through [get_nets *altera_jesd204_tx_ctl_inst*]\
|
||||
-to [get_clocks {sys_clk_100mhz}]
|
||||
|
||||
set_false_path -from [get_clocks {i_system_bd|daq3|xcvr_rx_pll|outclk0}]\
|
||||
-through [get_nets *altera_jesd204_rx_csr_inst*]\
|
||||
-to [get_clocks {sys_clk_100mhz}]
|
||||
|
||||
|
|
|
@ -147,8 +147,8 @@ module system_top (
|
|||
|
||||
// board gpio
|
||||
|
||||
inout [ 10:0] gpio_bd_i;
|
||||
inout [ 15:0] gpio_bd_o;
|
||||
input [ 10:0] gpio_bd_i;
|
||||
output [ 15:0] gpio_bd_o;
|
||||
|
||||
// lane interface
|
||||
|
||||
|
@ -209,11 +209,11 @@ module system_top (
|
|||
|
||||
// gpio in & out are separate cores
|
||||
|
||||
assign sysref = gpio_o[36];
|
||||
assign adc_pd = gpio_o[35];
|
||||
assign dac_txen = gpio_o[34];
|
||||
assign sysref = gpio_o[43];
|
||||
assign adc_pd = gpio_o[42];
|
||||
assign dac_txen = gpio_o[41];
|
||||
|
||||
assign gpio_i[63:38] = 26'd0;
|
||||
assign gpio_i[63:38] = gpio_o[63:38];
|
||||
assign gpio_i[37:37] = trig;
|
||||
assign gpio_i[36:36] = adc_fdb;
|
||||
assign gpio_i[35:35] = adc_fda;
|
||||
|
|
|
@ -13,7 +13,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "9";
|
||||
value = "11";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
|
@ -21,7 +21,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "14";
|
||||
value = "16";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
|
@ -37,7 +37,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "12";
|
||||
value = "14";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
|
@ -53,7 +53,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "11";
|
||||
value = "13";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
|
@ -69,7 +69,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "8";
|
||||
value = "10";
|
||||
type = "int";
|
||||
}
|
||||
datum sopceditor_expanded
|
||||
|
@ -90,7 +90,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "15";
|
||||
value = "17";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
|
@ -406,14 +406,6 @@
|
|||
type = "String";
|
||||
}
|
||||
}
|
||||
element daq3_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element mem_clk
|
||||
{
|
||||
datum _sortIndex
|
||||
|
@ -650,7 +642,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "10";
|
||||
value = "12";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
|
@ -658,7 +650,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "13";
|
||||
value = "15";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
|
@ -666,7 +658,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "18";
|
||||
value = "20";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
|
@ -674,7 +666,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "16";
|
||||
value = "18";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
|
@ -682,7 +674,15 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "7";
|
||||
value = "8";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element xcvr_rx_pll_reconfig
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "9";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
|
@ -690,7 +690,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "6";
|
||||
value = "7";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
|
@ -698,7 +698,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "17";
|
||||
value = "19";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
|
@ -710,6 +710,14 @@
|
|||
type = "int";
|
||||
}
|
||||
}
|
||||
element xcvr_tx_pll_reconfig
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "6";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element xcvr_tx_ref_clk
|
||||
{
|
||||
datum _sortIndex
|
||||
|
@ -829,6 +837,36 @@
|
|||
internal="axi_jesd_xcvr.if_tx_ext_sysref_in"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="xcvr_core_jesd204_rx_s_avl"
|
||||
internal="xcvr_core.jesd204_rx_avs"
|
||||
type="avalon"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="xcvr_core_jesd204_tx_s_avl"
|
||||
internal="xcvr_core.jesd204_tx_avs"
|
||||
type="avalon"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="xcvr_core_reconfig_s_avl"
|
||||
internal="xcvr_core.reconfig_avmm"
|
||||
type="avalon"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="xcvr_rx_pll_reconfig_s_avl"
|
||||
internal="xcvr_rx_pll_reconfig.mgmt_avalon_slave"
|
||||
type="avalon"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="xcvr_tx_lane_pll_s_avl"
|
||||
internal="xcvr_tx_lane_pll.reconfig_avmm0"
|
||||
type="avalon"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="xcvr_tx_pll_reconfig_s_avl"
|
||||
internal="xcvr_tx_pll_reconfig.mgmt_avalon_slave"
|
||||
type="avalon"
|
||||
dir="end" />
|
||||
<module name="ad9680_adcfifo" kind="util_adcfifo" version="1.0" enabled="1">
|
||||
<parameter name="ADC_DATA_WIDTH" value="128" />
|
||||
<parameter name="DMA_ADDRESS_WIDTH" value="16" />
|
||||
|
@ -966,12 +1004,12 @@
|
|||
<parameter name="lane_rate" value="10000.0" />
|
||||
<parameter name="part_trait_bd" value="NIGHTFURY5" />
|
||||
<parameter name="part_trait_dp" value="10AX115S3F45E2SGE3" />
|
||||
<parameter name="pll_reconfig_enable" value="false" />
|
||||
<parameter name="pll_reconfig_enable" value="true" />
|
||||
<parameter name="pll_type" value="CMU" />
|
||||
<parameter name="rcfg_jtag_enable" value="false" />
|
||||
<parameter name="sdc_constraint" value="1.0" />
|
||||
<parameter name="set_capability_reg_enable" value="false" />
|
||||
<parameter name="set_csr_soft_logic_enable" value="false" />
|
||||
<parameter name="set_capability_reg_enable" value="true" />
|
||||
<parameter name="set_csr_soft_logic_enable" value="true" />
|
||||
<parameter name="set_prbs_soft_logic_enable" value="false" />
|
||||
<parameter name="set_user_identifier" value="0" />
|
||||
<parameter name="wrapper_opt" value="base_phy" />
|
||||
|
@ -994,10 +1032,10 @@
|
|||
<parameter name="TX_PLL_ENABLE" value="1" />
|
||||
<parameter name="T_PLL_LOCK_HYST" value="0" />
|
||||
<parameter name="T_PLL_POWERDOWN" value="1000" />
|
||||
<parameter name="T_RX_ANALOGRESET" value="40" />
|
||||
<parameter name="T_RX_ANALOGRESET" value="70000" />
|
||||
<parameter name="T_RX_DIGITALRESET" value="4000" />
|
||||
<parameter name="T_TX_ANALOGRESET" value="0" />
|
||||
<parameter name="T_TX_DIGITALRESET" value="20" />
|
||||
<parameter name="T_TX_ANALOGRESET" value="70000" />
|
||||
<parameter name="T_TX_DIGITALRESET" value="70000" />
|
||||
<parameter name="device_family" value="Arria 10" />
|
||||
<parameter name="gui_pll_cal_busy" value="1" />
|
||||
<parameter name="gui_rx_auto_reset" value="0" />
|
||||
|
@ -1181,7 +1219,7 @@
|
|||
<parameter name="gui_en_extclkout_ports" value="false" />
|
||||
<parameter name="gui_en_lvds_ports" value="Disabled" />
|
||||
<parameter name="gui_en_phout_ports" value="false" />
|
||||
<parameter name="gui_en_reconf" value="false" />
|
||||
<parameter name="gui_en_reconf" value="true" />
|
||||
<parameter name="gui_enable_cascade_in" value="false" />
|
||||
<parameter name="gui_enable_cascade_out" value="false" />
|
||||
<parameter name="gui_enable_mif_dps" value="false" />
|
||||
|
@ -1287,6 +1325,16 @@
|
|||
<parameter name="system_info_device_speed_grade" value="2" />
|
||||
<parameter name="system_part_trait_speed_grade" value="2" />
|
||||
</module>
|
||||
<module
|
||||
name="xcvr_rx_pll_reconfig"
|
||||
kind="altera_pll_reconfig"
|
||||
version="15.1"
|
||||
enabled="1">
|
||||
<parameter name="ENABLE_BYTEENABLE" value="false" />
|
||||
<parameter name="ENABLE_MIF" value="false" />
|
||||
<parameter name="MIF_FILE_NAME" value="" />
|
||||
<parameter name="device_family" value="Arria 10" />
|
||||
</module>
|
||||
<module
|
||||
name="xcvr_rx_ref_clk"
|
||||
kind="altera_clock_bridge"
|
||||
|
@ -1309,7 +1357,7 @@
|
|||
<parameter name="enable_8G_path" value="1" />
|
||||
<parameter name="enable_analog_resets" value="0" />
|
||||
<parameter name="enable_atx_to_fpll_cascade_out" value="0" />
|
||||
<parameter name="enable_bonding_clks" value="1" />
|
||||
<parameter name="enable_bonding_clks" value="0" />
|
||||
<parameter name="enable_cascade_out" value="0" />
|
||||
<parameter name="enable_debug_ports_parameters" value="0" />
|
||||
<parameter name="enable_fb_comp_bonding" value="0" />
|
||||
|
@ -1322,7 +1370,7 @@
|
|||
<parameter name="enable_pcie_clk" value="0" />
|
||||
<parameter name="enable_pld_atx_cal_busy_port" value="1" />
|
||||
<parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
|
||||
<parameter name="enable_pll_reconfig" value="0" />
|
||||
<parameter name="enable_pll_reconfig" value="1" />
|
||||
<parameter name="generate_add_hdl_instance_example" value="0" />
|
||||
<parameter name="generate_docs" value="1" />
|
||||
<parameter name="mcgb_aux_clkin_cnt" value="0" />
|
||||
|
@ -1342,7 +1390,7 @@
|
|||
<parameter name="rcfg_param_vals2" value="" />
|
||||
<parameter name="rcfg_profile_cnt" value="2" />
|
||||
<parameter name="rcfg_profile_select" value="1" />
|
||||
<parameter name="rcfg_separate_avmm_busy" value="0" />
|
||||
<parameter name="rcfg_separate_avmm_busy" value="1" />
|
||||
<parameter name="rcfg_sv_file_enable" value="0" />
|
||||
<parameter name="rcfg_txt_file_enable" value="0" />
|
||||
<parameter name="refclk_cnt" value="1" />
|
||||
|
@ -1350,16 +1398,16 @@
|
|||
<parameter name="select_manual_config" value="false" />
|
||||
<parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
|
||||
<parameter name="set_auto_reference_clock_frequency" value="500.0" />
|
||||
<parameter name="set_capability_reg_enable" value="0" />
|
||||
<parameter name="set_csr_soft_logic_enable" value="0" />
|
||||
<parameter name="set_fref_clock_frequency" value="100.0" />
|
||||
<parameter name="set_capability_reg_enable" value="1" />
|
||||
<parameter name="set_csr_soft_logic_enable" value="1" />
|
||||
<parameter name="set_fref_clock_frequency" value="156.25" />
|
||||
<parameter name="set_hip_cal_en" value="0" />
|
||||
<parameter name="set_k_counter" value="1" />
|
||||
<parameter name="set_l_cascade_counter" value="4" />
|
||||
<parameter name="set_k_counter" value="2000000000" />
|
||||
<parameter name="set_l_cascade_counter" value="15" />
|
||||
<parameter name="set_l_cascade_predivider" value="1" />
|
||||
<parameter name="set_l_counter" value="4" />
|
||||
<parameter name="set_m_counter" value="50" />
|
||||
<parameter name="set_manual_reference_clock_frequency" value="100.0" />
|
||||
<parameter name="set_l_counter" value="16" />
|
||||
<parameter name="set_m_counter" value="24" />
|
||||
<parameter name="set_manual_reference_clock_frequency" value="200.0" />
|
||||
<parameter name="set_output_clock_frequency" value="5000.0" />
|
||||
<parameter name="set_ref_clk_div" value="1" />
|
||||
<parameter name="set_user_identifier" value="0" />
|
||||
|
@ -1544,7 +1592,7 @@
|
|||
<parameter name="gui_en_extclkout_ports" value="false" />
|
||||
<parameter name="gui_en_lvds_ports" value="Disabled" />
|
||||
<parameter name="gui_en_phout_ports" value="false" />
|
||||
<parameter name="gui_en_reconf" value="false" />
|
||||
<parameter name="gui_en_reconf" value="true" />
|
||||
<parameter name="gui_enable_cascade_in" value="false" />
|
||||
<parameter name="gui_enable_cascade_out" value="false" />
|
||||
<parameter name="gui_enable_mif_dps" value="false" />
|
||||
|
@ -1650,6 +1698,16 @@
|
|||
<parameter name="system_info_device_speed_grade" value="2" />
|
||||
<parameter name="system_part_trait_speed_grade" value="2" />
|
||||
</module>
|
||||
<module
|
||||
name="xcvr_tx_pll_reconfig"
|
||||
kind="altera_pll_reconfig"
|
||||
version="15.1"
|
||||
enabled="1">
|
||||
<parameter name="ENABLE_BYTEENABLE" value="false" />
|
||||
<parameter name="ENABLE_MIF" value="false" />
|
||||
<parameter name="MIF_FILE_NAME" value="" />
|
||||
<parameter name="device_family" value="Arria 10" />
|
||||
</module>
|
||||
<module
|
||||
name="xcvr_tx_ref_clk"
|
||||
kind="altera_clock_bridge"
|
||||
|
@ -1706,11 +1764,31 @@
|
|||
version="15.1"
|
||||
start="mem_clk.out_clk"
|
||||
end="axi_ad9152_dma.m_src_axi_clock" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="sys_clk.out_clk"
|
||||
end="xcvr_tx_pll_reconfig.mgmt_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="sys_clk.out_clk"
|
||||
end="xcvr_rx_pll_reconfig.mgmt_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="xcvr_tx_ref_clk.out_clk"
|
||||
end="xcvr_tx_lane_pll.pll_refclk0" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="sys_clk.out_clk"
|
||||
end="xcvr_core.reconfig_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="sys_clk.out_clk"
|
||||
end="xcvr_tx_lane_pll.reconfig_clk0" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
|
@ -1804,8 +1882,8 @@
|
|||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="util_cpack_0.adc_ch_0"
|
||||
end="axi_ad9680_core.adc_ch_0">
|
||||
start="axi_ad9680_core.adc_ch_0"
|
||||
end="util_cpack_0.adc_ch_0">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
|
@ -1815,8 +1893,8 @@
|
|||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="util_cpack_0.adc_ch_1"
|
||||
end="axi_ad9680_core.adc_ch_1">
|
||||
start="axi_ad9680_core.adc_ch_1"
|
||||
end="util_cpack_0.adc_ch_1">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
|
@ -1837,8 +1915,8 @@
|
|||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="util_upack_0.dac_ch_0"
|
||||
end="axi_ad9152_core.dac_ch_0">
|
||||
start="axi_ad9152_core.dac_ch_0"
|
||||
end="util_upack_0.dac_ch_0">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
|
@ -1889,17 +1967,6 @@
|
|||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_ad9152_core.if_dac_dunf"
|
||||
end="axi_ad9152_dma.if_fifo_rd_underflow">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
|
@ -1966,6 +2033,17 @@
|
|||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_ad9152_dma.if_fifo_rd_underflow"
|
||||
end="axi_ad9152_core.if_dac_dunf">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
|
@ -2046,19 +2124,8 @@
|
|||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_jesd_xcvr.if_tx_ready"
|
||||
end="xcvr_rst_cntrl.tx_ready">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="xcvr_rst_cntrl.pll_cal_busy"
|
||||
end="xcvr_tx_lane_pll.pll_cal_busy">
|
||||
start="xcvr_tx_lane_pll.pll_cal_busy"
|
||||
end="xcvr_rst_cntrl.pll_cal_busy">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
|
@ -2079,8 +2146,52 @@
|
|||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="xcvr_tx_lane_pll.pll_powerdown"
|
||||
end="xcvr_rst_cntrl.pll_powerdown">
|
||||
start="xcvr_rst_cntrl.pll_powerdown"
|
||||
end="xcvr_tx_lane_pll.pll_powerdown">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="xcvr_tx_pll_reconfig.reconfig_from_pll"
|
||||
end="xcvr_tx_pll.reconfig_from_pll">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="xcvr_rx_pll.reconfig_from_pll"
|
||||
end="xcvr_rx_pll_reconfig.reconfig_from_pll">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="xcvr_tx_pll.reconfig_to_pll"
|
||||
end="xcvr_tx_pll_reconfig.reconfig_to_pll">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="xcvr_rx_pll_reconfig.reconfig_to_pll"
|
||||
end="xcvr_rx_pll.reconfig_to_pll">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
|
@ -2178,8 +2289,19 @@
|
|||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="xcvr_rst_cntrl.tx_digitalreset"
|
||||
end="xcvr_core.tx_digitalreset">
|
||||
start="xcvr_core.tx_digitalreset"
|
||||
end="xcvr_rst_cntrl.tx_digitalreset">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="xcvr_rst_cntrl.tx_ready"
|
||||
end="axi_jesd_xcvr.if_tx_ready">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
|
@ -2275,7 +2397,22 @@
|
|||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="xcvr_rst_cntrl.reset" />
|
||||
end="xcvr_tx_pll_reconfig.mgmt_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="xcvr_rx_pll_reconfig.mgmt_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="xcvr_core.reconfig_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="xcvr_tx_lane_pll.reconfig_reset0" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
|
@ -2286,6 +2423,11 @@
|
|||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="xcvr_rx_pll.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="xcvr_rst_cntrl.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
|
|
Loading…
Reference in New Issue