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axi_ad9144: Updates for ad_dds phase acc wrapper

main
AndreiGrozav 2018-06-06 11:45:04 +03:00 committed by AndreiGrozav
parent 4a73e32941
commit d27ed93594
3 changed files with 10 additions and 0 deletions
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3
library/axi_ad9144/Makefile
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@ -18,7 +18,10 @@ ALTERA_DEPS += ../altera/common/up_xfer_cntrl_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_status_constr.sdc
ALTERA_DEPS += ../common/ad_dds.v
ALTERA_DEPS += ../common/ad_dds_1.v
ALTERA_DEPS += ../common/ad_dds_2.v
ALTERA_DEPS += ../common/ad_dds_cordic_pipe.v
ALTERA_DEPS += ../common/ad_dds_sine.v
ALTERA_DEPS += ../common/ad_dds_sine_cordic.v
ALTERA_DEPS += ../common/ad_rst.v
ALTERA_DEPS += ../common/up_axi.v
ALTERA_DEPS += ../common/up_clock_mon.v

4
library/axi_ad9144/axi_ad9144.v
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@ -41,6 +41,7 @@ module axi_ad9144 #(
parameter QUAD_OR_DUAL_N = 1,
parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
parameter DAC_DATAPATH_DISABLE = 0) (
// jesd interface
@ -131,6 +132,9 @@ module axi_ad9144 #(
.ID (ID),
.NUM_LANES (NUM_CHANNELS * 2),
.NUM_CHANNELS (NUM_CHANNELS),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DAC_DATAPATH_DISABLE (DAC_DATAPATH_DISABLE)
) i_dac_jesd204 (
.link_clk (tx_clk),

3
library/axi_ad9144/axi_ad9144_hw.tcl
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@ -15,7 +15,10 @@ set_module_property ELABORATION_CALLBACK p_axi_ad9144
ad_ip_files axi_ad9144 [list \
$ad_hdl_dir/library/altera/common/ad_mul.v \
$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v \
$ad_hdl_dir/library/common/ad_dds_sine_cordic.v \
$ad_hdl_dir/library/common/ad_dds_sine.v \
$ad_hdl_dir/library/common/ad_dds_2.v \
$ad_hdl_dir/library/common/ad_dds_1.v \
$ad_hdl_dir/library/common/ad_dds.v \
$ad_hdl_dir/library/common/ad_rst.v \