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adi_ip.tcl: Allow to directly specify the vlnv string for adi_add_bus() 

Modify the adi_add_bus() function to take the full vlnv strings instead of just the bus type.

This makes the function more flexible and e.g. allows to handle buses from other vendors.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2015-04-01 12:52:23 +02:00
parent 7da59a435f
commit d17cd22ef1
4 changed files with 43 additions and 33 deletions
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8
library/axi_dmac/axi_dmac_ip.tcl
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@ -38,14 +38,18 @@ adi_ip_constraints axi_dmac [list \
set_property physical_name {s_axi_aclk} [ipx::get_port_map CLK \ set_property physical_name {s_axi_aclk} [ipx::get_port_map CLK \
[ipx::get_bus_interface s_axi_signal_clock [ipx::current_core]]] [ipx::get_bus_interface s_axi_signal_clock [ipx::current_core]]]
adi_add_bus "s_axis" "axis" "slave" \ adi_add_bus "s_axis" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
[list {"s_axis_ready" "TREADY"} \ [list {"s_axis_ready" "TREADY"} \
{"s_axis_valid" "TVALID"} \ {"s_axis_valid" "TVALID"} \
{"s_axis_data" "TDATA"} \ {"s_axis_data" "TDATA"} \
{"s_axis_user" "TUSER"} ] {"s_axis_user" "TUSER"} ]
adi_add_bus_clock "s_axis_aclk" "s_axis" adi_add_bus_clock "s_axis_aclk" "s_axis"
adi_add_bus "m_axis" "axis" "master" \ adi_add_bus "m_axis" "master" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
[list {"m_axis_ready" "TREADY"} \ [list {"m_axis_ready" "TREADY"} \
{"m_axis_valid" "TVALID"} \ {"m_axis_valid" "TVALID"} \
{"m_axis_data" "TDATA"} ] {"m_axis_data" "TDATA"} ]

40
library/axi_i2s_adi/axi_i2s_adi_ip.tcl
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@ -19,27 +19,43 @@ adi_ip_files axi_i2s_adi [list \
adi_ip_properties_lite axi_i2s_adi adi_ip_properties_lite axi_i2s_adi
adi_add_bus "DMA_ACK_RX" "axis" "slave" \ adi_add_bus "DMA_ACK_RX" "slave" \
[list {"DMA_REQ_RX_DAVALID" "TVALID"} \ "xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
{ \
{"DMA_REQ_RX_DAVALID" "TVALID"} \
{"DMA_REQ_RX_DAREADY" "TREADY"} \ {"DMA_REQ_RX_DAREADY" "TREADY"} \
{"DMA_REQ_RX_DATYPE" "TUSER"} ] {"DMA_REQ_RX_DATYPE" "TUSER"} \
adi_add_bus "DMA_REQ_RX" "axis" "master" \ }
[list {"DMA_REQ_RX_DRVALID" "TVALID"} \ adi_add_bus "DMA_REQ_RX" "master" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
{ \
{"DMA_REQ_RX_DRVALID" "TVALID"} \
{"DMA_REQ_RX_DRREADY" "TREADY"} \ {"DMA_REQ_RX_DRREADY" "TREADY"} \
{"DMA_REQ_RX_DRTYPE" "TUSER"} \ {"DMA_REQ_RX_DRTYPE" "TUSER"} \
{"DMA_REQ_RX_DRLAST" "TLAST"} ] {"DMA_REQ_RX_DRLAST" "TLAST"} \
}
# Clock and reset are for both DMA_REQ and DMA_ACK # Clock and reset are for both DMA_REQ and DMA_ACK
adi_add_bus_clock "DMA_REQ_RX_ACLK" "DMA_REQ_RX:DMA_ACK_RX" "DMA_REQ_RX_RSTN" adi_add_bus_clock "DMA_REQ_RX_ACLK" "DMA_REQ_RX:DMA_ACK_RX" "DMA_REQ_RX_RSTN"
adi_add_bus "DMA_ACK_TX" "axis" "slave" \ adi_add_bus "DMA_ACK_TX" "slave" \
[list {"DMA_REQ_TX_DAVALID" "TVALID"} \ "xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
{ \
{"DMA_REQ_TX_DAVALID" "TVALID"} \
{"DMA_REQ_TX_DAREADY" "TREADY"} \ {"DMA_REQ_TX_DAREADY" "TREADY"} \
{"DMA_REQ_TX_DATYPE" "TUSER"} ] {"DMA_REQ_TX_DATYPE" "TUSER"} \
adi_add_bus "DMA_REQ_TX" "axis" "master" \ }
[list {"DMA_REQ_TX_DRVALID" "TVALID"} \ adi_add_bus "DMA_REQ_TX" "master" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
{ \
{"DMA_REQ_TX_DRVALID" "TVALID"} \
{"DMA_REQ_TX_DRREADY" "TREADY"} \ {"DMA_REQ_TX_DRREADY" "TREADY"} \
{"DMA_REQ_TX_DRTYPE" "TUSER"} \ {"DMA_REQ_TX_DRTYPE" "TUSER"} \
{"DMA_REQ_TX_DRLAST" "TLAST"} ] {"DMA_REQ_TX_DRLAST" "TLAST"} \
}
# Clock and reset are for both DMA_REQ and DMA_ACK # Clock and reset are for both DMA_REQ and DMA_ACK
adi_add_bus_clock "DMA_REQ_TX_ACLK" "DMA_REQ_TX:DMA_ACK_TX" "DMA_REQ_TX_RSTN" adi_add_bus_clock "DMA_REQ_TX_ACLK" "DMA_REQ_TX:DMA_ACK_TX" "DMA_REQ_TX_RSTN"

8
library/axi_spdif_tx/axi_spdif_tx_ip.tcl
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@ -22,11 +22,15 @@ ipx::add_file $ip_constr_files $proj_filegroup
set_property type {{xdc}} [ipx::get_file $ip_constr_files $proj_filegroup] set_property type {{xdc}} [ipx::get_file $ip_constr_files $proj_filegroup]
set_property library_name {} [ipx::get_file $ip_constr_files $proj_filegroup] set_property library_name {} [ipx::get_file $ip_constr_files $proj_filegroup]
adi_add_bus "DMA_ACK" "axis" "slave" \ adi_add_bus "DMA_ACK" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
[list {"DMA_REQ_DAVALID" "TVALID"} \ [list {"DMA_REQ_DAVALID" "TVALID"} \
{"DMA_REQ_DAREADY" "TREADY"} \ {"DMA_REQ_DAREADY" "TREADY"} \
{"DMA_REQ_DATYPE" "TUSER"} ] {"DMA_REQ_DATYPE" "TUSER"} ]
adi_add_bus "DMA_REQ" "axis" "master" \ adi_add_bus "DMA_REQ" "master" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
[list {"DMA_REQ_DRVALID" "TVALID"} \ [list {"DMA_REQ_DRVALID" "TVALID"} \
{"DMA_REQ_DRREADY" "TREADY"} \ {"DMA_REQ_DRREADY" "TREADY"} \
{"DMA_REQ_DRTYPE" "TUSER"} \ {"DMA_REQ_DRTYPE" "TUSER"} \

20
library/scripts/adi_ip.tcl
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@ -125,25 +125,11 @@ proc adi_add_port_map {bus phys logic} {
set_property "LOGICAL_NAME" $logic $map set_property "LOGICAL_NAME" $logic $map
} }
proc adi_add_bus {bus_name bus_type mode port_maps} { proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
if { $bus_type == "axis" } {
set abst_type "axis_rtl"
} elseif { $bus_type == "aximm" } {
set abst_type "aximm_rtl"
} else {
set abst_type $bus_type
}
set_property "ABSTRACTION_TYPE_LIBRARY" "interface" $bus set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
set_property "ABSTRACTION_TYPE_NAME" $abst_type $bus set_property "BUS_TYPE_VLNV" $bus_type $bus
set_property "ABSTRACTION_TYPE_VENDOR" "xilinx.com" $bus
set_property "ABSTRACTION_TYPE_VERSION" "1.0" $bus
set_property "BUS_TYPE_LIBRARY" "interface" $bus
set_property "BUS_TYPE_NAME" $bus_type $bus
set_property "BUS_TYPE_VENDOR" "xilinx.com" $bus
set_property "BUS_TYPE_VERSION" "1.0" $bus
set_property "CLASS" "bus_interface" $bus
set_property "INTERFACE_MODE" $mode $bus set_property "INTERFACE_MODE" $mode $bus
foreach port_map $port_maps { foreach port_map $port_maps {