arradio- timing violations fix
parent
36a9ea40b1
commit
d132ed45cd
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@ -93,7 +93,7 @@ module axi_ad9361_lvds_if_c5 (
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// internal registers
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reg pll_rst = 'd0;
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reg pll_rst = 1'd1;
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reg locked_int = 'd0;
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reg tx_core_enable_int = 'd0;
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reg tx_core_txnrx_int = 'd0;
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@ -66,6 +66,11 @@ set_output_delay -add_delay -fall -min 0.2 -clock {v_tx_clk} [get_ports {tx_dat
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set_output_delay -add_delay -fall -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[4]}]
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set_output_delay -add_delay -fall -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[5]}]
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# locked is async- most likely clock won't be running when deasserted
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set_false_path -to [get_registers *axi_ad9361_lvds_if:i_dev_if|up_drp_locked_m1*]
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# frame reader seems to use the wrong reset!
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set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]
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