From d132ed45cdb687dc9ec4dbf0aadb0347ec51d16d Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 20 Jul 2017 15:08:21 -0400 Subject: [PATCH] arradio- timing violations fix --- library/axi_ad9361/altera/axi_ad9361_lvds_if_c5.v | 2 +- projects/arradio/c5soc/system_constr.sdc | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/library/axi_ad9361/altera/axi_ad9361_lvds_if_c5.v b/library/axi_ad9361/altera/axi_ad9361_lvds_if_c5.v index f92fedb0d..7666139ac 100644 --- a/library/axi_ad9361/altera/axi_ad9361_lvds_if_c5.v +++ b/library/axi_ad9361/altera/axi_ad9361_lvds_if_c5.v @@ -93,7 +93,7 @@ module axi_ad9361_lvds_if_c5 ( // internal registers - reg pll_rst = 'd0; + reg pll_rst = 1'd1; reg locked_int = 'd0; reg tx_core_enable_int = 'd0; reg tx_core_txnrx_int = 'd0; diff --git a/projects/arradio/c5soc/system_constr.sdc b/projects/arradio/c5soc/system_constr.sdc index 3d398c96a..2376f8e15 100644 --- a/projects/arradio/c5soc/system_constr.sdc +++ b/projects/arradio/c5soc/system_constr.sdc @@ -66,6 +66,11 @@ set_output_delay -add_delay -fall -min 0.2 -clock {v_tx_clk} [get_ports {tx_dat set_output_delay -add_delay -fall -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[4]}] set_output_delay -add_delay -fall -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[5]}] +# locked is async- most likely clock won't be running when deasserted + +set_false_path -to [get_registers *axi_ad9361_lvds_if:i_dev_if|up_drp_locked_m1*] + # frame reader seems to use the wrong reset! set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*] +