Add util_sync_reset helper module

This helper module can be used to make sure that a reset signal is de-asserted
synchronously to a clock signal. This is e.g. required by the AXI spec.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

library/util_sync_reset/util_sync_reset.v

@@ -0,0 +1,23 @@
+
+
+module util_sync_reset (
+	input async_resetn,
+	input clk,
+	output sync_resetn
+);
+
+// Keep it asserted for three clock cycles
+reg [2:0] reset = 3'b111;
+
+assign sync_resetn = reset[2];
+
+always @(posedge clk or negedge async_resetn) begin
+	if (async_resetn == 1'b0) begin
+		reset <= 3'b111;
+	end else begin
+		reset <= {reset[1:0], 1'b0};
+	end
+
+end
+
+endmodule

library/util_sync_reset/util_sync_reset_ip.tcl

@@ -0,0 +1,13 @@
+# ip
+
+source ../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip.tcl
+
+adi_ip_create util_sync_reset
+adi_ip_files util_sync_reset [list \
+  "util_sync_reset.v" ]
+
+adi_ip_properties_lite util_sync_reset
+
+ipx::save_core [ipx::current_core]
+