diff --git a/projects/adrv9361z7035/common/adrv9361z7035_bd.tcl b/projects/adrv9361z7035/common/adrv9361z7035_bd.tcl index a71c06ccb..0db503a8a 100644 --- a/projects/adrv9361z7035/common/adrv9361z7035_bd.tcl +++ b/projects/adrv9361z7035/common/adrv9361z7035_bd.tcl @@ -125,65 +125,65 @@ ad_ip_parameter sys_logic_inv CONFIG.C_OPERATION not # system reset/clock definitions -ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0 -ad_connect sys_200m_clk sys_ps7/FCLK_CLK1 -ad_connect sys_cpu_reset sys_rstgen/peripheral_reset -ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn -ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk -ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N +ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0 +ad_connect sys_200m_clk sys_ps7/FCLK_CLK1 +ad_connect sys_cpu_reset sys_rstgen/peripheral_reset +ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn +ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk +ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N # interface connections -ad_connect ddr sys_ps7/DDR -ad_connect gpio_i sys_ps7/GPIO_I -ad_connect gpio_o sys_ps7/GPIO_O -ad_connect gpio_t sys_ps7/GPIO_T -ad_connect fixed_io sys_ps7/FIXED_IO -ad_connect iic_main axi_iic_main/iic -ad_connect sys_logic_inv/Res sys_ps7/USB0_VBUS_PWRFAULT -ad_connect sys_logic_inv/Op1 otg_vbusoc +ad_connect ddr sys_ps7/DDR +ad_connect gpio_i sys_ps7/GPIO_I +ad_connect gpio_o sys_ps7/GPIO_O +ad_connect gpio_t sys_ps7/GPIO_T +ad_connect fixed_io sys_ps7/FIXED_IO +ad_connect iic_main axi_iic_main/iic +ad_connect sys_logic_inv/Res sys_ps7/USB0_VBUS_PWRFAULT +ad_connect sys_logic_inv/Op1 otg_vbusoc # spi connections -ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O -ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O -ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O -ad_connect spi0_csn_i sys_ps7/SPI0_SS_I -ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I -ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O -ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I -ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O -ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I +ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O +ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O +ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O +ad_connect spi0_csn_i sys_ps7/SPI0_SS_I +ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I +ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O +ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I +ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O +ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I -ad_connect spi1_csn_2_o sys_ps7/SPI1_SS2_O -ad_connect spi1_csn_1_o sys_ps7/SPI1_SS1_O -ad_connect spi1_csn_0_o sys_ps7/SPI1_SS_O -ad_connect spi1_csn_i sys_ps7/SPI1_SS_I -ad_connect spi1_clk_i sys_ps7/SPI1_SCLK_I -ad_connect spi1_clk_o sys_ps7/SPI1_SCLK_O -ad_connect spi1_sdo_i sys_ps7/SPI1_MOSI_I -ad_connect spi1_sdo_o sys_ps7/SPI1_MOSI_O -ad_connect spi1_sdi_i sys_ps7/SPI1_MISO_I +ad_connect spi1_csn_2_o sys_ps7/SPI1_SS2_O +ad_connect spi1_csn_1_o sys_ps7/SPI1_SS1_O +ad_connect spi1_csn_0_o sys_ps7/SPI1_SS_O +ad_connect spi1_csn_i sys_ps7/SPI1_SS_I +ad_connect spi1_clk_i sys_ps7/SPI1_SCLK_I +ad_connect spi1_clk_o sys_ps7/SPI1_SCLK_O +ad_connect spi1_sdo_i sys_ps7/SPI1_MOSI_I +ad_connect spi1_sdo_o sys_ps7/SPI1_MOSI_O +ad_connect spi1_sdi_i sys_ps7/SPI1_MISO_I # interrupts -ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P -ad_connect sys_concat_intc/In15 ps_intr_15 -ad_connect sys_concat_intc/In14 axi_iic_main/iic2intc_irpt -ad_connect sys_concat_intc/In13 ps_intr_13 -ad_connect sys_concat_intc/In12 ps_intr_12 -ad_connect sys_concat_intc/In11 ps_intr_11 -ad_connect sys_concat_intc/In10 ps_intr_10 -ad_connect sys_concat_intc/In9 ps_intr_09 -ad_connect sys_concat_intc/In8 ps_intr_08 -ad_connect sys_concat_intc/In7 ps_intr_07 -ad_connect sys_concat_intc/In6 ps_intr_06 -ad_connect sys_concat_intc/In5 ps_intr_05 -ad_connect sys_concat_intc/In4 ps_intr_04 -ad_connect sys_concat_intc/In3 ps_intr_03 -ad_connect sys_concat_intc/In2 ps_intr_02 -ad_connect sys_concat_intc/In1 ps_intr_01 -ad_connect sys_concat_intc/In0 ps_intr_00 +ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P +ad_connect sys_concat_intc/In15 ps_intr_15 +ad_connect sys_concat_intc/In14 axi_iic_main/iic2intc_irpt +ad_connect sys_concat_intc/In13 ps_intr_13 +ad_connect sys_concat_intc/In12 ps_intr_12 +ad_connect sys_concat_intc/In11 ps_intr_11 +ad_connect sys_concat_intc/In10 ps_intr_10 +ad_connect sys_concat_intc/In9 ps_intr_09 +ad_connect sys_concat_intc/In8 ps_intr_08 +ad_connect sys_concat_intc/In7 ps_intr_07 +ad_connect sys_concat_intc/In6 ps_intr_06 +ad_connect sys_concat_intc/In5 ps_intr_05 +ad_connect sys_concat_intc/In4 ps_intr_04 +ad_connect sys_concat_intc/In3 ps_intr_03 +ad_connect sys_concat_intc/In2 ps_intr_02 +ad_connect sys_concat_intc/In1 ps_intr_01 +ad_connect sys_concat_intc/In0 ps_intr_00 # interconnects @@ -195,6 +195,7 @@ create_bd_port -dir O enable create_bd_port -dir O txnrx create_bd_port -dir I up_enable create_bd_port -dir I up_txnrx + create_bd_port -dir O tdd_sync_o create_bd_port -dir I tdd_sync_i create_bd_port -dir O tdd_sync_t @@ -205,19 +206,94 @@ create_bd_port -dir I gps_pps ad_ip_instance axi_ad9361 axi_ad9361 ad_ip_parameter axi_ad9361 CONFIG.ID 0 ad_ip_parameter axi_ad9361 CONFIG.DAC_IODELAY_ENABLE 1 +ad_connect sys_200m_clk axi_ad9361/delay_clk +ad_connect axi_ad9361/l_clk axi_ad9361/clk +ad_connect enable axi_ad9361/enable +ad_connect txnrx axi_ad9361/txnrx +ad_connect up_enable axi_ad9361/up_enable +ad_connect up_txnrx axi_ad9361/up_txnrx -ad_ip_instance axi_dmac axi_ad9361_dac_dma -ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_SRC 0 -ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_DEST 2 -ad_ip_parameter axi_ad9361_dac_dma CONFIG.CYCLIC 1 -ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_SRC 0 -ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_DEST 1 -ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_2D_TRANSFER 0 -ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_DATA_WIDTH_DEST 64 +# tdd-sync -ad_ip_instance util_upack util_ad9361_dac_upack -ad_ip_parameter util_ad9361_dac_upack CONFIG.NUM_OF_CHANNELS 4 -ad_ip_parameter util_ad9361_dac_upack CONFIG.CHANNEL_DATA_WIDTH 16 +ad_ip_instance util_tdd_sync util_ad9361_tdd_sync +ad_ip_parameter util_ad9361_tdd_sync CONFIG.TDD_SYNC_PERIOD 10000000 +ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk +ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn +ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync +ad_connect util_ad9361_tdd_sync/sync_mode axi_ad9361/tdd_sync_cntr +ad_connect tdd_sync_t axi_ad9361/tdd_sync_cntr +ad_connect tdd_sync_o util_ad9361_tdd_sync/sync_out +ad_connect tdd_sync_i util_ad9361_tdd_sync/sync_in +ad_connect gps_pps axi_ad9361/gps_pps + +# interface clock divider to generate sampling clock +# interface runs at 4x in 2r2t mode, and 2x in 1r1t mode + +ad_ip_instance xlconcat util_ad9361_divclk_sel_concat +ad_ip_parameter util_ad9361_divclk_sel_concat CONFIG.NUM_PORTS 2 +ad_connect axi_ad9361/adc_r1_mode util_ad9361_divclk_sel_concat/In0 +ad_connect axi_ad9361/dac_r1_mode util_ad9361_divclk_sel_concat/In1 + +ad_ip_instance util_reduced_logic util_ad9361_divclk_sel +ad_ip_parameter util_ad9361_divclk_sel CONFIG.C_SIZE 2 +ad_connect util_ad9361_divclk_sel_concat/dout util_ad9361_divclk_sel/Op1 + +ad_ip_instance util_clkdiv util_ad9361_divclk +ad_connect util_ad9361_divclk_sel/Res util_ad9361_divclk/clk_sel +ad_connect axi_ad9361/l_clk util_ad9361_divclk/clk + +# resets at divided clock + +ad_ip_instance proc_sys_reset util_ad9361_divclk_reset +ad_connect sys_rstgen/peripheral_aresetn util_ad9361_divclk_reset/ext_reset_in +ad_connect util_ad9361_divclk/clk_out util_ad9361_divclk_reset/slowest_sync_clk + +# adc-path wfifo + +ad_ip_instance util_wfifo util_ad9361_adc_fifo +ad_ip_parameter util_ad9361_adc_fifo CONFIG.NUM_OF_CHANNELS 4 +ad_ip_parameter util_ad9361_adc_fifo CONFIG.DIN_ADDRESS_WIDTH 4 +ad_ip_parameter util_ad9361_adc_fifo CONFIG.DIN_DATA_WIDTH 16 +ad_ip_parameter util_ad9361_adc_fifo CONFIG.DOUT_DATA_WIDTH 16 +ad_connect axi_ad9361/l_clk util_ad9361_adc_fifo/din_clk +ad_connect axi_ad9361/rst util_ad9361_adc_fifo/din_rst +ad_connect util_ad9361_divclk/clk_out util_ad9361_adc_fifo/dout_clk +ad_connect util_ad9361_divclk_reset/peripheral_aresetn util_ad9361_adc_fifo/dout_rstn +ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0 +ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0 +ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0 +ad_connect axi_ad9361/adc_enable_q0 util_ad9361_adc_fifo/din_enable_1 +ad_connect axi_ad9361/adc_valid_q0 util_ad9361_adc_fifo/din_valid_1 +ad_connect axi_ad9361/adc_data_q0 util_ad9361_adc_fifo/din_data_1 +ad_connect axi_ad9361/adc_enable_i1 util_ad9361_adc_fifo/din_enable_2 +ad_connect axi_ad9361/adc_valid_i1 util_ad9361_adc_fifo/din_valid_2 +ad_connect axi_ad9361/adc_data_i1 util_ad9361_adc_fifo/din_data_2 +ad_connect axi_ad9361/adc_enable_q1 util_ad9361_adc_fifo/din_enable_3 +ad_connect axi_ad9361/adc_valid_q1 util_ad9361_adc_fifo/din_valid_3 +ad_connect axi_ad9361/adc_data_q1 util_ad9361_adc_fifo/din_data_3 +ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf + +# adc-path channel pack + +ad_ip_instance util_cpack util_ad9361_adc_pack +ad_ip_parameter util_ad9361_adc_pack CONFIG.NUM_OF_CHANNELS 4 +ad_ip_parameter util_ad9361_adc_pack CONFIG.CHANNEL_DATA_WIDTH 16 +ad_connect util_ad9361_divclk/clk_out util_ad9361_adc_pack/adc_clk +ad_connect util_ad9361_divclk_reset/peripheral_reset util_ad9361_adc_pack/adc_rst +ad_connect util_ad9361_adc_fifo/dout_enable_0 util_ad9361_adc_pack/adc_enable_0 +ad_connect util_ad9361_adc_fifo/dout_valid_0 util_ad9361_adc_pack/adc_valid_0 +ad_connect util_ad9361_adc_fifo/dout_data_0 util_ad9361_adc_pack/adc_data_0 +ad_connect util_ad9361_adc_fifo/dout_enable_1 util_ad9361_adc_pack/adc_enable_1 +ad_connect util_ad9361_adc_fifo/dout_valid_1 util_ad9361_adc_pack/adc_valid_1 +ad_connect util_ad9361_adc_fifo/dout_data_1 util_ad9361_adc_pack/adc_data_1 +ad_connect util_ad9361_adc_fifo/dout_enable_2 util_ad9361_adc_pack/adc_enable_2 +ad_connect util_ad9361_adc_fifo/dout_valid_2 util_ad9361_adc_pack/adc_valid_2 +ad_connect util_ad9361_adc_fifo/dout_data_2 util_ad9361_adc_pack/adc_data_2 +ad_connect util_ad9361_adc_fifo/dout_enable_3 util_ad9361_adc_pack/adc_enable_3 +ad_connect util_ad9361_adc_fifo/dout_valid_3 util_ad9361_adc_pack/adc_valid_3 +ad_connect util_ad9361_adc_fifo/dout_data_3 util_ad9361_adc_pack/adc_data_3 + +# adc-path dma ad_ip_instance axi_dmac axi_ad9361_adc_dma ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_TYPE_SRC 2 @@ -228,128 +304,75 @@ ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_SRC 0 ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_DEST 0 ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_DATA_WIDTH_SRC 64 +ad_connect util_ad9361_divclk/clk_out axi_ad9361_adc_dma/fifo_wr_clk +ad_connect util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en +ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync +ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din +ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf +ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn -ad_ip_instance util_cpack util_ad9361_adc_pack -ad_ip_parameter util_ad9361_adc_pack CONFIG.NUM_OF_CHANNELS 4 -ad_ip_parameter util_ad9361_adc_pack CONFIG.CHANNEL_DATA_WIDTH 16 +# dac-path rfifo -ad_ip_instance util_wfifo util_ad9361_adc_fifo -ad_ip_parameter util_ad9361_adc_fifo CONFIG.NUM_OF_CHANNELS 4 -ad_ip_parameter util_ad9361_adc_fifo CONFIG.DIN_ADDRESS_WIDTH 4 -ad_ip_parameter util_ad9361_adc_fifo CONFIG.DIN_DATA_WIDTH 16 -ad_ip_parameter util_ad9361_adc_fifo CONFIG.DOUT_DATA_WIDTH 16 +ad_ip_instance util_rfifo axi_ad9361_dac_fifo +ad_ip_parameter axi_ad9361_dac_fifo CONFIG.DIN_DATA_WIDTH 16 +ad_ip_parameter axi_ad9361_dac_fifo CONFIG.DOUT_DATA_WIDTH 16 +ad_ip_parameter axi_ad9361_dac_fifo CONFIG.DIN_ADDRESS_WIDTH 4 +ad_connect axi_ad9361/l_clk axi_ad9361_dac_fifo/dout_clk +ad_connect axi_ad9361/rst axi_ad9361_dac_fifo/dout_rst +ad_connect util_ad9361_divclk/clk_out axi_ad9361_dac_fifo/din_clk +ad_connect util_ad9361_divclk_reset/peripheral_aresetn axi_ad9361_dac_fifo/din_rstn +ad_connect axi_ad9361_dac_fifo/dout_enable_0 axi_ad9361/dac_enable_i0 +ad_connect axi_ad9361_dac_fifo/dout_valid_0 axi_ad9361/dac_valid_i0 +ad_connect axi_ad9361_dac_fifo/dout_data_0 axi_ad9361/dac_data_i0 +ad_connect axi_ad9361_dac_fifo/dout_enable_1 axi_ad9361/dac_enable_q0 +ad_connect axi_ad9361_dac_fifo/dout_valid_1 axi_ad9361/dac_valid_q0 +ad_connect axi_ad9361_dac_fifo/dout_data_1 axi_ad9361/dac_data_q0 +ad_connect axi_ad9361_dac_fifo/dout_enable_2 axi_ad9361/dac_enable_i1 +ad_connect axi_ad9361_dac_fifo/dout_valid_2 axi_ad9361/dac_valid_i1 +ad_connect axi_ad9361_dac_fifo/dout_data_2 axi_ad9361/dac_data_i1 +ad_connect axi_ad9361_dac_fifo/dout_enable_3 axi_ad9361/dac_enable_q1 +ad_connect axi_ad9361_dac_fifo/dout_valid_3 axi_ad9361/dac_valid_q1 +ad_connect axi_ad9361_dac_fifo/dout_data_3 axi_ad9361/dac_data_q1 +ad_connect axi_ad9361_dac_fifo/dout_unf axi_ad9361/dac_dunf -ad_ip_instance util_tdd_sync util_ad9361_tdd_sync -ad_ip_parameter util_ad9361_tdd_sync CONFIG.TDD_SYNC_PERIOD 10000000 +# dac-path channel unpack -ad_ip_instance util_clkdiv clkdiv +ad_ip_instance util_upack util_ad9361_dac_upack +ad_ip_parameter util_ad9361_dac_upack CONFIG.NUM_OF_CHANNELS 4 +ad_ip_parameter util_ad9361_dac_upack CONFIG.CHANNEL_DATA_WIDTH 16 +ad_connect util_ad9361_divclk/clk_out util_ad9361_dac_upack/dac_clk +ad_connect util_ad9361_dac_upack/dac_enable_0 axi_ad9361_dac_fifo/din_enable_0 +ad_connect util_ad9361_dac_upack/dac_valid_0 axi_ad9361_dac_fifo/din_valid_0 +ad_connect util_ad9361_dac_upack/dac_valid_out_0 axi_ad9361_dac_fifo/din_valid_in_0 +ad_connect util_ad9361_dac_upack/dac_data_0 axi_ad9361_dac_fifo/din_data_0 +ad_connect util_ad9361_dac_upack/dac_enable_1 axi_ad9361_dac_fifo/din_enable_1 +ad_connect util_ad9361_dac_upack/dac_valid_1 axi_ad9361_dac_fifo/din_valid_1 +ad_connect util_ad9361_dac_upack/dac_valid_out_1 axi_ad9361_dac_fifo/din_valid_in_1 +ad_connect util_ad9361_dac_upack/dac_data_1 axi_ad9361_dac_fifo/din_data_1 +ad_connect util_ad9361_dac_upack/dac_enable_2 axi_ad9361_dac_fifo/din_enable_2 +ad_connect util_ad9361_dac_upack/dac_valid_2 axi_ad9361_dac_fifo/din_valid_2 +ad_connect util_ad9361_dac_upack/dac_valid_out_2 axi_ad9361_dac_fifo/din_valid_in_2 +ad_connect util_ad9361_dac_upack/dac_data_2 axi_ad9361_dac_fifo/din_data_2 +ad_connect util_ad9361_dac_upack/dac_enable_3 axi_ad9361_dac_fifo/din_enable_3 +ad_connect util_ad9361_dac_upack/dac_valid_3 axi_ad9361_dac_fifo/din_valid_3 +ad_connect util_ad9361_dac_upack/dac_valid_out_3 axi_ad9361_dac_fifo/din_valid_in_3 +ad_connect util_ad9361_dac_upack/dac_data_3 axi_ad9361_dac_fifo/din_data_3 -ad_ip_instance proc_sys_reset clkdiv_reset +# dac-path dma -ad_ip_instance util_rfifo dac_fifo -ad_ip_parameter dac_fifo CONFIG.DIN_DATA_WIDTH 16 -ad_ip_parameter dac_fifo CONFIG.DOUT_DATA_WIDTH 16 -ad_ip_parameter dac_fifo CONFIG.DIN_ADDRESS_WIDTH 4 - -ad_ip_instance util_reduced_logic clkdiv_sel_logic -ad_ip_parameter clkdiv_sel_logic CONFIG.C_SIZE 2 - -ad_ip_instance xlconcat concat_logic -ad_ip_parameter concat_logic CONFIG.NUM_PORTS 2 - -# connections - -ad_connect sys_200m_clk axi_ad9361/delay_clk -ad_connect axi_ad9361_clk axi_ad9361/l_clk -ad_connect axi_ad9361_clk axi_ad9361/clk -ad_connect enable axi_ad9361/enable -ad_connect txnrx axi_ad9361/txnrx -ad_connect up_enable axi_ad9361/up_enable -ad_connect up_txnrx axi_ad9361/up_txnrx -ad_connect axi_ad9361_clk util_ad9361_adc_fifo/din_clk -ad_connect axi_ad9361/rst util_ad9361_adc_fifo/din_rst -ad_connect axi_ad9361_clk clkdiv/clk -ad_connect clkdiv/clk_out axi_ad9361_adc_dma/fifo_wr_clk -ad_connect clkdiv/clk_out util_ad9361_adc_fifo/dout_clk -ad_connect clkdiv/clk_out util_ad9361_adc_pack/adc_clk -ad_connect clkdiv_reset/ext_reset_in sys_rstgen/peripheral_aresetn -ad_connect clkdiv_reset/slowest_sync_clk clkdiv/clk_out -ad_connect util_ad9361_adc_pack/adc_rst clkdiv_reset/peripheral_reset -ad_connect util_ad9361_adc_fifo/dout_rstn clkdiv_reset/peripheral_aresetn -ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0 -ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0 -ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0 -ad_connect axi_ad9361/adc_enable_q0 util_ad9361_adc_fifo/din_enable_1 -ad_connect axi_ad9361/adc_valid_q0 util_ad9361_adc_fifo/din_valid_1 -ad_connect axi_ad9361/adc_data_q0 util_ad9361_adc_fifo/din_data_1 -ad_connect axi_ad9361/adc_enable_i1 util_ad9361_adc_fifo/din_enable_2 -ad_connect axi_ad9361/adc_valid_i1 util_ad9361_adc_fifo/din_valid_2 -ad_connect axi_ad9361/adc_data_i1 util_ad9361_adc_fifo/din_data_2 -ad_connect axi_ad9361/adc_enable_q1 util_ad9361_adc_fifo/din_enable_3 -ad_connect axi_ad9361/adc_valid_q1 util_ad9361_adc_fifo/din_valid_3 -ad_connect axi_ad9361/adc_data_q1 util_ad9361_adc_fifo/din_data_3 -ad_connect util_ad9361_adc_fifo/dout_enable_0 util_ad9361_adc_pack/adc_enable_0 -ad_connect util_ad9361_adc_fifo/dout_valid_0 util_ad9361_adc_pack/adc_valid_0 -ad_connect util_ad9361_adc_fifo/dout_data_0 util_ad9361_adc_pack/adc_data_0 -ad_connect util_ad9361_adc_fifo/dout_enable_1 util_ad9361_adc_pack/adc_enable_1 -ad_connect util_ad9361_adc_fifo/dout_valid_1 util_ad9361_adc_pack/adc_valid_1 -ad_connect util_ad9361_adc_fifo/dout_data_1 util_ad9361_adc_pack/adc_data_1 -ad_connect util_ad9361_adc_fifo/dout_enable_2 util_ad9361_adc_pack/adc_enable_2 -ad_connect util_ad9361_adc_fifo/dout_valid_2 util_ad9361_adc_pack/adc_valid_2 -ad_connect util_ad9361_adc_fifo/dout_data_2 util_ad9361_adc_pack/adc_data_2 -ad_connect util_ad9361_adc_fifo/dout_enable_3 util_ad9361_adc_pack/adc_enable_3 -ad_connect util_ad9361_adc_fifo/dout_valid_3 util_ad9361_adc_pack/adc_valid_3 -ad_connect util_ad9361_adc_fifo/dout_data_3 util_ad9361_adc_pack/adc_data_3 -ad_connect util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en -ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync -ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din -ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf -ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf -ad_connect axi_ad9361/adc_r1_mode concat_logic/In0 -ad_connect axi_ad9361/dac_r1_mode concat_logic/In1 -ad_connect concat_logic/dout clkdiv_sel_logic/Op1 -ad_connect clkdiv/clk_sel clkdiv_sel_logic/Res -ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en -ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout -ad_connect clkdiv/clk_out axi_ad9361_dac_dma/fifo_rd_clk -ad_connect axi_ad9361/dac_dunf dac_fifo/dout_unf -ad_connect dac_fifo/din_clk clkdiv/clk_out -ad_connect dac_fifo/din_rstn clkdiv_reset/peripheral_aresetn -ad_connect axi_ad9361_clk dac_fifo/dout_clk -ad_connect dac_fifo/dout_rst axi_ad9361/rst -ad_connect util_ad9361_dac_upack/dac_clk clkdiv/clk_out -ad_connect dac_fifo/din_enable_0 util_ad9361_dac_upack/dac_enable_0 -ad_connect dac_fifo/din_valid_0 util_ad9361_dac_upack/dac_valid_0 -ad_connect dac_fifo/din_data_0 util_ad9361_dac_upack/dac_data_0 -ad_connect dac_fifo/din_enable_1 util_ad9361_dac_upack/dac_enable_1 -ad_connect dac_fifo/din_valid_1 util_ad9361_dac_upack/dac_valid_1 -ad_connect dac_fifo/din_data_1 util_ad9361_dac_upack/dac_data_1 -ad_connect dac_fifo/din_enable_2 util_ad9361_dac_upack/dac_enable_2 -ad_connect dac_fifo/din_valid_2 util_ad9361_dac_upack/dac_valid_2 -ad_connect dac_fifo/din_data_2 util_ad9361_dac_upack/dac_data_2 -ad_connect dac_fifo/din_enable_3 util_ad9361_dac_upack/dac_enable_3 -ad_connect dac_fifo/din_valid_3 util_ad9361_dac_upack/dac_valid_3 -ad_connect dac_fifo/din_data_3 util_ad9361_dac_upack/dac_data_3 -ad_connect axi_ad9361/dac_enable_i0 dac_fifo/dout_enable_0 -ad_connect axi_ad9361/dac_valid_i0 dac_fifo/dout_valid_0 -ad_connect axi_ad9361/dac_data_i0 dac_fifo/dout_data_0 -ad_connect axi_ad9361/dac_enable_q0 dac_fifo/dout_enable_1 -ad_connect axi_ad9361/dac_valid_q0 dac_fifo/dout_valid_1 -ad_connect axi_ad9361/dac_data_q0 dac_fifo/dout_data_1 -ad_connect axi_ad9361/dac_enable_i1 dac_fifo/dout_enable_2 -ad_connect axi_ad9361/dac_valid_i1 dac_fifo/dout_valid_2 -ad_connect axi_ad9361/dac_data_i1 dac_fifo/dout_data_2 -ad_connect axi_ad9361/dac_enable_q1 dac_fifo/dout_enable_3 -ad_connect axi_ad9361/dac_valid_q1 dac_fifo/dout_valid_3 -ad_connect axi_ad9361/dac_data_q1 dac_fifo/dout_data_3 -ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk -ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn -ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync -ad_connect util_ad9361_tdd_sync/sync_mode axi_ad9361/tdd_sync_cntr -ad_connect tdd_sync_t axi_ad9361/tdd_sync_cntr -ad_connect tdd_sync_o util_ad9361_tdd_sync/sync_out -ad_connect tdd_sync_i util_ad9361_tdd_sync/sync_in -ad_connect gps_pps axi_ad9361/gps_pps +ad_ip_instance axi_dmac axi_ad9361_dac_dma +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_SRC 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_DEST 2 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.CYCLIC 1 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_DEST 1 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_DATA_WIDTH_DEST 64 +ad_connect util_ad9361_divclk/clk_out axi_ad9361_dac_dma/fifo_rd_clk +ad_connect axi_ad9361_dac_dma/fifo_rd_en util_ad9361_dac_upack/dac_valid +ad_connect axi_ad9361_dac_dma/fifo_rd_dout util_ad9361_dac_upack/dac_data +ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn # interconnects @@ -360,8 +383,6 @@ ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 ad_mem_hp1_interconnect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi -ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn -ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn # interrupts @@ -425,18 +446,18 @@ proc cfg_ad9361_interface {cmos_or_lvds} { create_bd_port -dir O -from 5 -to 0 tx_data_out_p create_bd_port -dir O -from 5 -to 0 tx_data_out_n - ad_connect rx_clk_in_p axi_ad9361/rx_clk_in_p - ad_connect rx_clk_in_n axi_ad9361/rx_clk_in_n - ad_connect rx_frame_in_p axi_ad9361/rx_frame_in_p - ad_connect rx_frame_in_n axi_ad9361/rx_frame_in_n - ad_connect rx_data_in_p axi_ad9361/rx_data_in_p - ad_connect rx_data_in_n axi_ad9361/rx_data_in_n - ad_connect tx_clk_out_p axi_ad9361/tx_clk_out_p - ad_connect tx_clk_out_n axi_ad9361/tx_clk_out_n - ad_connect tx_frame_out_p axi_ad9361/tx_frame_out_p - ad_connect tx_frame_out_n axi_ad9361/tx_frame_out_n - ad_connect tx_data_out_p axi_ad9361/tx_data_out_p - ad_connect tx_data_out_n axi_ad9361/tx_data_out_n + ad_connect rx_clk_in_p axi_ad9361/rx_clk_in_p + ad_connect rx_clk_in_n axi_ad9361/rx_clk_in_n + ad_connect rx_frame_in_p axi_ad9361/rx_frame_in_p + ad_connect rx_frame_in_n axi_ad9361/rx_frame_in_n + ad_connect rx_data_in_p axi_ad9361/rx_data_in_p + ad_connect rx_data_in_n axi_ad9361/rx_data_in_n + ad_connect tx_clk_out_p axi_ad9361/tx_clk_out_p + ad_connect tx_clk_out_n axi_ad9361/tx_clk_out_n + ad_connect tx_frame_out_p axi_ad9361/tx_frame_out_p + ad_connect tx_frame_out_n axi_ad9361/tx_frame_out_n + ad_connect tx_data_out_p axi_ad9361/tx_data_out_p + ad_connect tx_data_out_n axi_ad9361/tx_data_out_n return } @@ -452,12 +473,12 @@ proc cfg_ad9361_interface {cmos_or_lvds} { create_bd_port -dir O tx_frame_out create_bd_port -dir O -from 11 -to 0 tx_data_out - ad_connect rx_clk_in axi_ad9361/rx_clk_in - ad_connect rx_frame_in axi_ad9361/rx_frame_in - ad_connect rx_data_in axi_ad9361/rx_data_in - ad_connect tx_clk_out axi_ad9361/tx_clk_out - ad_connect tx_frame_out axi_ad9361/tx_frame_out - ad_connect tx_data_out axi_ad9361/tx_data_out + ad_connect rx_clk_in axi_ad9361/rx_clk_in + ad_connect rx_frame_in axi_ad9361/rx_frame_in + ad_connect rx_data_in axi_ad9361/rx_data_in + ad_connect tx_clk_out axi_ad9361/tx_clk_out + ad_connect tx_frame_out axi_ad9361/tx_frame_out + ad_connect tx_data_out axi_ad9361/tx_data_out return } diff --git a/projects/adrv9364z7020/common/adrv9364z7020_bd.tcl b/projects/adrv9364z7020/common/adrv9364z7020_bd.tcl index e5c303ea1..c5bb3aaeb 100644 --- a/projects/adrv9364z7020/common/adrv9364z7020_bd.tcl +++ b/projects/adrv9364z7020/common/adrv9364z7020_bd.tcl @@ -125,65 +125,65 @@ ad_ip_parameter sys_logic_inv CONFIG.C_OPERATION not # system reset/clock definitions -ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0 -ad_connect sys_200m_clk sys_ps7/FCLK_CLK1 -ad_connect sys_cpu_reset sys_rstgen/peripheral_reset -ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn -ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk -ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N +ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0 +ad_connect sys_200m_clk sys_ps7/FCLK_CLK1 +ad_connect sys_cpu_reset sys_rstgen/peripheral_reset +ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn +ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk +ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N # interface connections -ad_connect ddr sys_ps7/DDR -ad_connect gpio_i sys_ps7/GPIO_I -ad_connect gpio_o sys_ps7/GPIO_O -ad_connect gpio_t sys_ps7/GPIO_T -ad_connect fixed_io sys_ps7/FIXED_IO -ad_connect iic_main axi_iic_main/iic -ad_connect sys_logic_inv/Res sys_ps7/USB0_VBUS_PWRFAULT -ad_connect sys_logic_inv/Op1 otg_vbusoc +ad_connect ddr sys_ps7/DDR +ad_connect gpio_i sys_ps7/GPIO_I +ad_connect gpio_o sys_ps7/GPIO_O +ad_connect gpio_t sys_ps7/GPIO_T +ad_connect fixed_io sys_ps7/FIXED_IO +ad_connect iic_main axi_iic_main/iic +ad_connect sys_logic_inv/Res sys_ps7/USB0_VBUS_PWRFAULT +ad_connect sys_logic_inv/Op1 otg_vbusoc # spi connections -ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O -ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O -ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O -ad_connect spi0_csn_i sys_ps7/SPI0_SS_I -ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I -ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O -ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I -ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O -ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I +ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O +ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O +ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O +ad_connect spi0_csn_i sys_ps7/SPI0_SS_I +ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I +ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O +ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I +ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O +ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I -ad_connect spi1_csn_2_o sys_ps7/SPI1_SS2_O -ad_connect spi1_csn_1_o sys_ps7/SPI1_SS1_O -ad_connect spi1_csn_0_o sys_ps7/SPI1_SS_O -ad_connect spi1_csn_i sys_ps7/SPI1_SS_I -ad_connect spi1_clk_i sys_ps7/SPI1_SCLK_I -ad_connect spi1_clk_o sys_ps7/SPI1_SCLK_O -ad_connect spi1_sdo_i sys_ps7/SPI1_MOSI_I -ad_connect spi1_sdo_o sys_ps7/SPI1_MOSI_O -ad_connect spi1_sdi_i sys_ps7/SPI1_MISO_I +ad_connect spi1_csn_2_o sys_ps7/SPI1_SS2_O +ad_connect spi1_csn_1_o sys_ps7/SPI1_SS1_O +ad_connect spi1_csn_0_o sys_ps7/SPI1_SS_O +ad_connect spi1_csn_i sys_ps7/SPI1_SS_I +ad_connect spi1_clk_i sys_ps7/SPI1_SCLK_I +ad_connect spi1_clk_o sys_ps7/SPI1_SCLK_O +ad_connect spi1_sdo_i sys_ps7/SPI1_MOSI_I +ad_connect spi1_sdo_o sys_ps7/SPI1_MOSI_O +ad_connect spi1_sdi_i sys_ps7/SPI1_MISO_I # interrupts -ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P -ad_connect sys_concat_intc/In15 ps_intr_15 -ad_connect sys_concat_intc/In14 axi_iic_main/iic2intc_irpt -ad_connect sys_concat_intc/In13 ps_intr_13 -ad_connect sys_concat_intc/In12 ps_intr_12 -ad_connect sys_concat_intc/In11 ps_intr_11 -ad_connect sys_concat_intc/In10 ps_intr_10 -ad_connect sys_concat_intc/In9 ps_intr_09 -ad_connect sys_concat_intc/In8 ps_intr_08 -ad_connect sys_concat_intc/In7 ps_intr_07 -ad_connect sys_concat_intc/In6 ps_intr_06 -ad_connect sys_concat_intc/In5 ps_intr_05 -ad_connect sys_concat_intc/In4 ps_intr_04 -ad_connect sys_concat_intc/In3 ps_intr_03 -ad_connect sys_concat_intc/In2 ps_intr_02 -ad_connect sys_concat_intc/In1 ps_intr_01 -ad_connect sys_concat_intc/In0 ps_intr_00 +ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P +ad_connect sys_concat_intc/In15 ps_intr_15 +ad_connect sys_concat_intc/In14 axi_iic_main/iic2intc_irpt +ad_connect sys_concat_intc/In13 ps_intr_13 +ad_connect sys_concat_intc/In12 ps_intr_12 +ad_connect sys_concat_intc/In11 ps_intr_11 +ad_connect sys_concat_intc/In10 ps_intr_10 +ad_connect sys_concat_intc/In9 ps_intr_09 +ad_connect sys_concat_intc/In8 ps_intr_08 +ad_connect sys_concat_intc/In7 ps_intr_07 +ad_connect sys_concat_intc/In6 ps_intr_06 +ad_connect sys_concat_intc/In5 ps_intr_05 +ad_connect sys_concat_intc/In4 ps_intr_04 +ad_connect sys_concat_intc/In3 ps_intr_03 +ad_connect sys_concat_intc/In2 ps_intr_02 +ad_connect sys_concat_intc/In1 ps_intr_01 +ad_connect sys_concat_intc/In0 ps_intr_00 # interconnects @@ -195,6 +195,7 @@ create_bd_port -dir O enable create_bd_port -dir O txnrx create_bd_port -dir I up_enable create_bd_port -dir I up_txnrx + create_bd_port -dir O tdd_sync_o create_bd_port -dir I tdd_sync_i create_bd_port -dir O tdd_sync_t @@ -205,19 +206,94 @@ create_bd_port -dir I gps_pps ad_ip_instance axi_ad9361 axi_ad9361 ad_ip_parameter axi_ad9361 CONFIG.ID 0 ad_ip_parameter axi_ad9361 CONFIG.DAC_IODELAY_ENABLE 0 +ad_connect sys_200m_clk axi_ad9361/delay_clk +ad_connect axi_ad9361/l_clk axi_ad9361/clk +ad_connect enable axi_ad9361/enable +ad_connect txnrx axi_ad9361/txnrx +ad_connect up_enable axi_ad9361/up_enable +ad_connect up_txnrx axi_ad9361/up_txnrx -ad_ip_instance axi_dmac axi_ad9361_dac_dma -ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_SRC 0 -ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_DEST 2 -ad_ip_parameter axi_ad9361_dac_dma CONFIG.CYCLIC 1 -ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_SRC 0 -ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_DEST 1 -ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_2D_TRANSFER 0 -ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_DATA_WIDTH_DEST 64 +# tdd-sync -ad_ip_instance util_upack util_ad9361_dac_upack -ad_ip_parameter util_ad9361_dac_upack CONFIG.NUM_OF_CHANNELS 4 -ad_ip_parameter util_ad9361_dac_upack CONFIG.CHANNEL_DATA_WIDTH 16 +ad_ip_instance util_tdd_sync util_ad9361_tdd_sync +ad_ip_parameter util_ad9361_tdd_sync CONFIG.TDD_SYNC_PERIOD 10000000 +ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk +ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn +ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync +ad_connect util_ad9361_tdd_sync/sync_mode axi_ad9361/tdd_sync_cntr +ad_connect tdd_sync_t axi_ad9361/tdd_sync_cntr +ad_connect tdd_sync_o util_ad9361_tdd_sync/sync_out +ad_connect tdd_sync_i util_ad9361_tdd_sync/sync_in +ad_connect gps_pps axi_ad9361/gps_pps + +# interface clock divider to generate sampling clock +# interface runs at 4x in 2r2t mode, and 2x in 1r1t mode + +ad_ip_instance xlconcat util_ad9361_divclk_sel_concat +ad_ip_parameter util_ad9361_divclk_sel_concat CONFIG.NUM_PORTS 2 +ad_connect axi_ad9361/adc_r1_mode util_ad9361_divclk_sel_concat/In0 +ad_connect axi_ad9361/dac_r1_mode util_ad9361_divclk_sel_concat/In1 + +ad_ip_instance util_reduced_logic util_ad9361_divclk_sel +ad_ip_parameter util_ad9361_divclk_sel CONFIG.C_SIZE 2 +ad_connect util_ad9361_divclk_sel_concat/dout util_ad9361_divclk_sel/Op1 + +ad_ip_instance util_clkdiv util_ad9361_divclk +ad_connect util_ad9361_divclk_sel/Res util_ad9361_divclk/clk_sel +ad_connect axi_ad9361/l_clk util_ad9361_divclk/clk + +# resets at divided clock + +ad_ip_instance proc_sys_reset util_ad9361_divclk_reset +ad_connect sys_rstgen/peripheral_aresetn util_ad9361_divclk_reset/ext_reset_in +ad_connect util_ad9361_divclk/clk_out util_ad9361_divclk_reset/slowest_sync_clk + +# adc-path wfifo + +ad_ip_instance util_wfifo util_ad9361_adc_fifo +ad_ip_parameter util_ad9361_adc_fifo CONFIG.NUM_OF_CHANNELS 4 +ad_ip_parameter util_ad9361_adc_fifo CONFIG.DIN_ADDRESS_WIDTH 4 +ad_ip_parameter util_ad9361_adc_fifo CONFIG.DIN_DATA_WIDTH 16 +ad_ip_parameter util_ad9361_adc_fifo CONFIG.DOUT_DATA_WIDTH 16 +ad_connect axi_ad9361/l_clk util_ad9361_adc_fifo/din_clk +ad_connect axi_ad9361/rst util_ad9361_adc_fifo/din_rst +ad_connect util_ad9361_divclk/clk_out util_ad9361_adc_fifo/dout_clk +ad_connect util_ad9361_divclk_reset/peripheral_aresetn util_ad9361_adc_fifo/dout_rstn +ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0 +ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0 +ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0 +ad_connect axi_ad9361/adc_enable_q0 util_ad9361_adc_fifo/din_enable_1 +ad_connect axi_ad9361/adc_valid_q0 util_ad9361_adc_fifo/din_valid_1 +ad_connect axi_ad9361/adc_data_q0 util_ad9361_adc_fifo/din_data_1 +ad_connect axi_ad9361/adc_enable_i1 util_ad9361_adc_fifo/din_enable_2 +ad_connect axi_ad9361/adc_valid_i1 util_ad9361_adc_fifo/din_valid_2 +ad_connect axi_ad9361/adc_data_i1 util_ad9361_adc_fifo/din_data_2 +ad_connect axi_ad9361/adc_enable_q1 util_ad9361_adc_fifo/din_enable_3 +ad_connect axi_ad9361/adc_valid_q1 util_ad9361_adc_fifo/din_valid_3 +ad_connect axi_ad9361/adc_data_q1 util_ad9361_adc_fifo/din_data_3 +ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf + +# adc-path channel pack + +ad_ip_instance util_cpack util_ad9361_adc_pack +ad_ip_parameter util_ad9361_adc_pack CONFIG.NUM_OF_CHANNELS 4 +ad_ip_parameter util_ad9361_adc_pack CONFIG.CHANNEL_DATA_WIDTH 16 +ad_connect util_ad9361_divclk/clk_out util_ad9361_adc_pack/adc_clk +ad_connect util_ad9361_divclk_reset/peripheral_reset util_ad9361_adc_pack/adc_rst +ad_connect util_ad9361_adc_fifo/dout_enable_0 util_ad9361_adc_pack/adc_enable_0 +ad_connect util_ad9361_adc_fifo/dout_valid_0 util_ad9361_adc_pack/adc_valid_0 +ad_connect util_ad9361_adc_fifo/dout_data_0 util_ad9361_adc_pack/adc_data_0 +ad_connect util_ad9361_adc_fifo/dout_enable_1 util_ad9361_adc_pack/adc_enable_1 +ad_connect util_ad9361_adc_fifo/dout_valid_1 util_ad9361_adc_pack/adc_valid_1 +ad_connect util_ad9361_adc_fifo/dout_data_1 util_ad9361_adc_pack/adc_data_1 +ad_connect util_ad9361_adc_fifo/dout_enable_2 util_ad9361_adc_pack/adc_enable_2 +ad_connect util_ad9361_adc_fifo/dout_valid_2 util_ad9361_adc_pack/adc_valid_2 +ad_connect util_ad9361_adc_fifo/dout_data_2 util_ad9361_adc_pack/adc_data_2 +ad_connect util_ad9361_adc_fifo/dout_enable_3 util_ad9361_adc_pack/adc_enable_3 +ad_connect util_ad9361_adc_fifo/dout_valid_3 util_ad9361_adc_pack/adc_valid_3 +ad_connect util_ad9361_adc_fifo/dout_data_3 util_ad9361_adc_pack/adc_data_3 + +# adc-path dma ad_ip_instance axi_dmac axi_ad9361_adc_dma ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_TYPE_SRC 2 @@ -228,128 +304,75 @@ ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_SRC 0 ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_DEST 0 ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_DATA_WIDTH_SRC 64 +ad_connect util_ad9361_divclk/clk_out axi_ad9361_adc_dma/fifo_wr_clk +ad_connect util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en +ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync +ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din +ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf +ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn -ad_ip_instance util_cpack util_ad9361_adc_pack -ad_ip_parameter util_ad9361_adc_pack CONFIG.NUM_OF_CHANNELS 4 -ad_ip_parameter util_ad9361_adc_pack CONFIG.CHANNEL_DATA_WIDTH 16 +# dac-path rfifo -ad_ip_instance util_wfifo util_ad9361_adc_fifo -ad_ip_parameter util_ad9361_adc_fifo CONFIG.NUM_OF_CHANNELS 4 -ad_ip_parameter util_ad9361_adc_fifo CONFIG.DIN_ADDRESS_WIDTH 4 -ad_ip_parameter util_ad9361_adc_fifo CONFIG.DIN_DATA_WIDTH 16 -ad_ip_parameter util_ad9361_adc_fifo CONFIG.DOUT_DATA_WIDTH 16 +ad_ip_instance util_rfifo axi_ad9361_dac_fifo +ad_ip_parameter axi_ad9361_dac_fifo CONFIG.DIN_DATA_WIDTH 16 +ad_ip_parameter axi_ad9361_dac_fifo CONFIG.DOUT_DATA_WIDTH 16 +ad_ip_parameter axi_ad9361_dac_fifo CONFIG.DIN_ADDRESS_WIDTH 4 +ad_connect axi_ad9361/l_clk axi_ad9361_dac_fifo/dout_clk +ad_connect axi_ad9361/rst axi_ad9361_dac_fifo/dout_rst +ad_connect util_ad9361_divclk/clk_out axi_ad9361_dac_fifo/din_clk +ad_connect util_ad9361_divclk_reset/peripheral_aresetn axi_ad9361_dac_fifo/din_rstn +ad_connect axi_ad9361_dac_fifo/dout_enable_0 axi_ad9361/dac_enable_i0 +ad_connect axi_ad9361_dac_fifo/dout_valid_0 axi_ad9361/dac_valid_i0 +ad_connect axi_ad9361_dac_fifo/dout_data_0 axi_ad9361/dac_data_i0 +ad_connect axi_ad9361_dac_fifo/dout_enable_1 axi_ad9361/dac_enable_q0 +ad_connect axi_ad9361_dac_fifo/dout_valid_1 axi_ad9361/dac_valid_q0 +ad_connect axi_ad9361_dac_fifo/dout_data_1 axi_ad9361/dac_data_q0 +ad_connect axi_ad9361_dac_fifo/dout_enable_2 axi_ad9361/dac_enable_i1 +ad_connect axi_ad9361_dac_fifo/dout_valid_2 axi_ad9361/dac_valid_i1 +ad_connect axi_ad9361_dac_fifo/dout_data_2 axi_ad9361/dac_data_i1 +ad_connect axi_ad9361_dac_fifo/dout_enable_3 axi_ad9361/dac_enable_q1 +ad_connect axi_ad9361_dac_fifo/dout_valid_3 axi_ad9361/dac_valid_q1 +ad_connect axi_ad9361_dac_fifo/dout_data_3 axi_ad9361/dac_data_q1 +ad_connect axi_ad9361_dac_fifo/dout_unf axi_ad9361/dac_dunf -ad_ip_instance util_tdd_sync util_ad9361_tdd_sync -ad_ip_parameter util_ad9361_tdd_sync CONFIG.TDD_SYNC_PERIOD 10000000 +# dac-path channel unpack -ad_ip_instance util_clkdiv clkdiv +ad_ip_instance util_upack util_ad9361_dac_upack +ad_ip_parameter util_ad9361_dac_upack CONFIG.NUM_OF_CHANNELS 4 +ad_ip_parameter util_ad9361_dac_upack CONFIG.CHANNEL_DATA_WIDTH 16 +ad_connect util_ad9361_divclk/clk_out util_ad9361_dac_upack/dac_clk +ad_connect util_ad9361_dac_upack/dac_enable_0 axi_ad9361_dac_fifo/din_enable_0 +ad_connect util_ad9361_dac_upack/dac_valid_0 axi_ad9361_dac_fifo/din_valid_0 +ad_connect util_ad9361_dac_upack/dac_valid_out_0 axi_ad9361_dac_fifo/din_valid_in_0 +ad_connect util_ad9361_dac_upack/dac_data_0 axi_ad9361_dac_fifo/din_data_0 +ad_connect util_ad9361_dac_upack/dac_enable_1 axi_ad9361_dac_fifo/din_enable_1 +ad_connect util_ad9361_dac_upack/dac_valid_1 axi_ad9361_dac_fifo/din_valid_1 +ad_connect util_ad9361_dac_upack/dac_valid_out_1 axi_ad9361_dac_fifo/din_valid_in_1 +ad_connect util_ad9361_dac_upack/dac_data_1 axi_ad9361_dac_fifo/din_data_1 +ad_connect util_ad9361_dac_upack/dac_enable_2 axi_ad9361_dac_fifo/din_enable_2 +ad_connect util_ad9361_dac_upack/dac_valid_2 axi_ad9361_dac_fifo/din_valid_2 +ad_connect util_ad9361_dac_upack/dac_valid_out_2 axi_ad9361_dac_fifo/din_valid_in_2 +ad_connect util_ad9361_dac_upack/dac_data_2 axi_ad9361_dac_fifo/din_data_2 +ad_connect util_ad9361_dac_upack/dac_enable_3 axi_ad9361_dac_fifo/din_enable_3 +ad_connect util_ad9361_dac_upack/dac_valid_3 axi_ad9361_dac_fifo/din_valid_3 +ad_connect util_ad9361_dac_upack/dac_valid_out_3 axi_ad9361_dac_fifo/din_valid_in_3 +ad_connect util_ad9361_dac_upack/dac_data_3 axi_ad9361_dac_fifo/din_data_3 -ad_ip_instance proc_sys_reset clkdiv_reset +# dac-path dma -ad_ip_instance util_rfifo dac_fifo -ad_ip_parameter dac_fifo CONFIG.DIN_DATA_WIDTH 16 -ad_ip_parameter dac_fifo CONFIG.DOUT_DATA_WIDTH 16 -ad_ip_parameter dac_fifo CONFIG.DIN_ADDRESS_WIDTH 4 - -ad_ip_instance util_reduced_logic clkdiv_sel_logic -ad_ip_parameter clkdiv_sel_logic CONFIG.C_SIZE 2 - -ad_ip_instance xlconcat concat_logic -ad_ip_parameter concat_logic CONFIG.NUM_PORTS 2 - -# connections - -ad_connect sys_200m_clk axi_ad9361/delay_clk -ad_connect axi_ad9361_clk axi_ad9361/l_clk -ad_connect axi_ad9361_clk axi_ad9361/clk -ad_connect enable axi_ad9361/enable -ad_connect txnrx axi_ad9361/txnrx -ad_connect up_enable axi_ad9361/up_enable -ad_connect up_txnrx axi_ad9361/up_txnrx -ad_connect axi_ad9361_clk util_ad9361_adc_fifo/din_clk -ad_connect axi_ad9361/rst util_ad9361_adc_fifo/din_rst -ad_connect axi_ad9361_clk clkdiv/clk -ad_connect clkdiv/clk_out axi_ad9361_adc_dma/fifo_wr_clk -ad_connect clkdiv/clk_out util_ad9361_adc_fifo/dout_clk -ad_connect clkdiv/clk_out util_ad9361_adc_pack/adc_clk -ad_connect clkdiv_reset/ext_reset_in sys_rstgen/peripheral_aresetn -ad_connect clkdiv_reset/slowest_sync_clk clkdiv/clk_out -ad_connect util_ad9361_adc_pack/adc_rst clkdiv_reset/peripheral_reset -ad_connect util_ad9361_adc_fifo/dout_rstn clkdiv_reset/peripheral_aresetn -ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0 -ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0 -ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0 -ad_connect axi_ad9361/adc_enable_q0 util_ad9361_adc_fifo/din_enable_1 -ad_connect axi_ad9361/adc_valid_q0 util_ad9361_adc_fifo/din_valid_1 -ad_connect axi_ad9361/adc_data_q0 util_ad9361_adc_fifo/din_data_1 -ad_connect axi_ad9361/adc_enable_i1 util_ad9361_adc_fifo/din_enable_2 -ad_connect axi_ad9361/adc_valid_i1 util_ad9361_adc_fifo/din_valid_2 -ad_connect axi_ad9361/adc_data_i1 util_ad9361_adc_fifo/din_data_2 -ad_connect axi_ad9361/adc_enable_q1 util_ad9361_adc_fifo/din_enable_3 -ad_connect axi_ad9361/adc_valid_q1 util_ad9361_adc_fifo/din_valid_3 -ad_connect axi_ad9361/adc_data_q1 util_ad9361_adc_fifo/din_data_3 -ad_connect util_ad9361_adc_fifo/dout_enable_0 util_ad9361_adc_pack/adc_enable_0 -ad_connect util_ad9361_adc_fifo/dout_valid_0 util_ad9361_adc_pack/adc_valid_0 -ad_connect util_ad9361_adc_fifo/dout_data_0 util_ad9361_adc_pack/adc_data_0 -ad_connect util_ad9361_adc_fifo/dout_enable_1 util_ad9361_adc_pack/adc_enable_1 -ad_connect util_ad9361_adc_fifo/dout_valid_1 util_ad9361_adc_pack/adc_valid_1 -ad_connect util_ad9361_adc_fifo/dout_data_1 util_ad9361_adc_pack/adc_data_1 -ad_connect util_ad9361_adc_fifo/dout_enable_2 util_ad9361_adc_pack/adc_enable_2 -ad_connect util_ad9361_adc_fifo/dout_valid_2 util_ad9361_adc_pack/adc_valid_2 -ad_connect util_ad9361_adc_fifo/dout_data_2 util_ad9361_adc_pack/adc_data_2 -ad_connect util_ad9361_adc_fifo/dout_enable_3 util_ad9361_adc_pack/adc_enable_3 -ad_connect util_ad9361_adc_fifo/dout_valid_3 util_ad9361_adc_pack/adc_valid_3 -ad_connect util_ad9361_adc_fifo/dout_data_3 util_ad9361_adc_pack/adc_data_3 -ad_connect util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en -ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync -ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din -ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf -ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf -ad_connect axi_ad9361/adc_r1_mode concat_logic/In0 -ad_connect axi_ad9361/dac_r1_mode concat_logic/In1 -ad_connect concat_logic/dout clkdiv_sel_logic/Op1 -ad_connect clkdiv/clk_sel clkdiv_sel_logic/Res -ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en -ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout -ad_connect clkdiv/clk_out axi_ad9361_dac_dma/fifo_rd_clk -ad_connect axi_ad9361/dac_dunf dac_fifo/dout_unf -ad_connect dac_fifo/din_clk clkdiv/clk_out -ad_connect dac_fifo/din_rstn clkdiv_reset/peripheral_aresetn -ad_connect axi_ad9361_clk dac_fifo/dout_clk -ad_connect dac_fifo/dout_rst axi_ad9361/rst -ad_connect util_ad9361_dac_upack/dac_clk clkdiv/clk_out -ad_connect dac_fifo/din_enable_0 util_ad9361_dac_upack/dac_enable_0 -ad_connect dac_fifo/din_valid_0 util_ad9361_dac_upack/dac_valid_0 -ad_connect dac_fifo/din_data_0 util_ad9361_dac_upack/dac_data_0 -ad_connect dac_fifo/din_enable_1 util_ad9361_dac_upack/dac_enable_1 -ad_connect dac_fifo/din_valid_1 util_ad9361_dac_upack/dac_valid_1 -ad_connect dac_fifo/din_data_1 util_ad9361_dac_upack/dac_data_1 -ad_connect dac_fifo/din_enable_2 util_ad9361_dac_upack/dac_enable_2 -ad_connect dac_fifo/din_valid_2 util_ad9361_dac_upack/dac_valid_2 -ad_connect dac_fifo/din_data_2 util_ad9361_dac_upack/dac_data_2 -ad_connect dac_fifo/din_enable_3 util_ad9361_dac_upack/dac_enable_3 -ad_connect dac_fifo/din_valid_3 util_ad9361_dac_upack/dac_valid_3 -ad_connect dac_fifo/din_data_3 util_ad9361_dac_upack/dac_data_3 -ad_connect axi_ad9361/dac_enable_i0 dac_fifo/dout_enable_0 -ad_connect axi_ad9361/dac_valid_i0 dac_fifo/dout_valid_0 -ad_connect axi_ad9361/dac_data_i0 dac_fifo/dout_data_0 -ad_connect axi_ad9361/dac_enable_q0 dac_fifo/dout_enable_1 -ad_connect axi_ad9361/dac_valid_q0 dac_fifo/dout_valid_1 -ad_connect axi_ad9361/dac_data_q0 dac_fifo/dout_data_1 -ad_connect axi_ad9361/dac_enable_i1 dac_fifo/dout_enable_2 -ad_connect axi_ad9361/dac_valid_i1 dac_fifo/dout_valid_2 -ad_connect axi_ad9361/dac_data_i1 dac_fifo/dout_data_2 -ad_connect axi_ad9361/dac_enable_q1 dac_fifo/dout_enable_3 -ad_connect axi_ad9361/dac_valid_q1 dac_fifo/dout_valid_3 -ad_connect axi_ad9361/dac_data_q1 dac_fifo/dout_data_3 -ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk -ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn -ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync -ad_connect util_ad9361_tdd_sync/sync_mode axi_ad9361/tdd_sync_cntr -ad_connect tdd_sync_t axi_ad9361/tdd_sync_cntr -ad_connect tdd_sync_o util_ad9361_tdd_sync/sync_out -ad_connect tdd_sync_i util_ad9361_tdd_sync/sync_in -ad_connect gps_pps axi_ad9361/gps_pps +ad_ip_instance axi_dmac axi_ad9361_dac_dma +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_SRC 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_DEST 2 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.CYCLIC 1 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_DEST 1 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_DATA_WIDTH_DEST 64 +ad_connect util_ad9361_divclk/clk_out axi_ad9361_dac_dma/fifo_rd_clk +ad_connect axi_ad9361_dac_dma/fifo_rd_en util_ad9361_dac_upack/dac_valid +ad_connect axi_ad9361_dac_dma/fifo_rd_dout util_ad9361_dac_upack/dac_data +ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn # interconnects @@ -360,8 +383,6 @@ ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 ad_mem_hp1_interconnect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi -ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn -ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn # interrupts @@ -425,18 +446,18 @@ proc cfg_ad9361_interface {cmos_or_lvds} { create_bd_port -dir O -from 5 -to 0 tx_data_out_p create_bd_port -dir O -from 5 -to 0 tx_data_out_n - ad_connect rx_clk_in_p axi_ad9361/rx_clk_in_p - ad_connect rx_clk_in_n axi_ad9361/rx_clk_in_n - ad_connect rx_frame_in_p axi_ad9361/rx_frame_in_p - ad_connect rx_frame_in_n axi_ad9361/rx_frame_in_n - ad_connect rx_data_in_p axi_ad9361/rx_data_in_p - ad_connect rx_data_in_n axi_ad9361/rx_data_in_n - ad_connect tx_clk_out_p axi_ad9361/tx_clk_out_p - ad_connect tx_clk_out_n axi_ad9361/tx_clk_out_n - ad_connect tx_frame_out_p axi_ad9361/tx_frame_out_p - ad_connect tx_frame_out_n axi_ad9361/tx_frame_out_n - ad_connect tx_data_out_p axi_ad9361/tx_data_out_p - ad_connect tx_data_out_n axi_ad9361/tx_data_out_n + ad_connect rx_clk_in_p axi_ad9361/rx_clk_in_p + ad_connect rx_clk_in_n axi_ad9361/rx_clk_in_n + ad_connect rx_frame_in_p axi_ad9361/rx_frame_in_p + ad_connect rx_frame_in_n axi_ad9361/rx_frame_in_n + ad_connect rx_data_in_p axi_ad9361/rx_data_in_p + ad_connect rx_data_in_n axi_ad9361/rx_data_in_n + ad_connect tx_clk_out_p axi_ad9361/tx_clk_out_p + ad_connect tx_clk_out_n axi_ad9361/tx_clk_out_n + ad_connect tx_frame_out_p axi_ad9361/tx_frame_out_p + ad_connect tx_frame_out_n axi_ad9361/tx_frame_out_n + ad_connect tx_data_out_p axi_ad9361/tx_data_out_p + ad_connect tx_data_out_n axi_ad9361/tx_data_out_n return } @@ -452,12 +473,12 @@ proc cfg_ad9361_interface {cmos_or_lvds} { create_bd_port -dir O tx_frame_out create_bd_port -dir O -from 11 -to 0 tx_data_out - ad_connect rx_clk_in axi_ad9361/rx_clk_in - ad_connect rx_frame_in axi_ad9361/rx_frame_in - ad_connect rx_data_in axi_ad9361/rx_data_in - ad_connect tx_clk_out axi_ad9361/tx_clk_out - ad_connect tx_frame_out axi_ad9361/tx_frame_out - ad_connect tx_data_out axi_ad9361/tx_data_out + ad_connect rx_clk_in axi_ad9361/rx_clk_in + ad_connect rx_frame_in axi_ad9361/rx_frame_in + ad_connect rx_data_in axi_ad9361/rx_data_in + ad_connect tx_clk_out axi_ad9361/tx_clk_out + ad_connect tx_frame_out axi_ad9361/tx_frame_out + ad_connect tx_data_out axi_ad9361/tx_data_out return }