From d04a545a41ef7ffce895a741896a7eb41b6ab6ce Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Mon, 27 Oct 2014 19:27:36 +0200 Subject: [PATCH] fmcomms2: updated zc706 project with new constraint style --- projects/fmcomms2/common/fmcomms2_bd.tcl | 6 +----- projects/fmcomms2/zc706/system_constr.xdc | 4 ---- 2 files changed, 1 insertion(+), 9 deletions(-) diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl index ce30eac92..a70d73041 100644 --- a/projects/fmcomms2/common/fmcomms2_bd.tcl +++ b/projects/fmcomms2/common/fmcomms2_bd.tcl @@ -68,11 +68,6 @@ if {$sys_zynq == 1} { set util_dac_unpack [create_bd_cell -type ip -vlnv analog.com:user:util_dac_unpack:1.0 util_dac_unpack] set_property -dict [list CONFIG.CHANNELS {4}] $util_dac_unpack - # constant 0 - - set constant_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant_0] - set_property -dict [list CONFIG.CONST_VAL {0}] $constant_0 - if {$sys_zynq == 1} { set_property -dict [list CONFIG.C_DMA_AXI_PROTOCOL_SRC {1}] $axi_ad9361_dac_dma } @@ -323,6 +318,7 @@ if {$sys_zynq == 0} { # ila (adc) set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_adc] + set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc set_property -dict [list CONFIG.C_NUM_OF_PROBES {8}] $ila_adc set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_adc diff --git a/projects/fmcomms2/zc706/system_constr.xdc b/projects/fmcomms2/zc706/system_constr.xdc index 452f6bbec..d24e70ce1 100644 --- a/projects/fmcomms2/zc706/system_constr.xdc +++ b/projects/fmcomms2/zc706/system_constr.xdc @@ -69,7 +69,3 @@ set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS25} [get_ports sp create_clock -name rx_clk -period 4.00 [get_ports rx_clk_in_p] create_clock -name ad9361_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9361/clk] - -set_clock_groups -asynchronous -group {ad9361_clk} -set_clock_groups -asynchronous -group {rx_clk} -