From cfff70d358ccc53715e3331e5116d79736178cd9 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 1 Feb 2017 14:27:11 +0200 Subject: [PATCH] M2K: Update standalone project - configured PS7 similar to pluto. Added specific constraints instead of default PS7 - moved ad9963_resetn and en_power_analog to gpio[0] and gpio[1] --- projects/m2k/standalone/system_bd.tcl | 35 +++--- projects/m2k/standalone/system_constr.xdc | 130 +++++++++++++++++++++ projects/m2k/standalone/system_project.tcl | 1 + projects/m2k/standalone/system_top.v | 18 ++- 4 files changed, 164 insertions(+), 20 deletions(-) diff --git a/projects/m2k/standalone/system_bd.tcl b/projects/m2k/standalone/system_bd.tcl index fdeab709f..ae11b6a2c 100644 --- a/projects/m2k/standalone/system_bd.tcl +++ b/projects/m2k/standalone/system_bd.tcl @@ -16,9 +16,9 @@ create_bd_port -dir I spi0_sdo_i create_bd_port -dir O spi0_sdo_o create_bd_port -dir I spi0_sdi_i -create_bd_port -dir I -from 63 -to 0 gpio_i -create_bd_port -dir O -from 63 -to 0 gpio_o -create_bd_port -dir O -from 63 -to 0 gpio_t +create_bd_port -dir I -from 17 -to 0 gpio_i +create_bd_port -dir O -from 17 -to 0 gpio_o +create_bd_port -dir O -from 17 -to 0 gpio_t # interrupts @@ -42,8 +42,8 @@ create_bd_port -dir I -type intr ps_intr_15 set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7] -set_property -dict [list CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V}] $sys_ps7 -set_property -dict [list CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 3.3V}] $sys_ps7 +set_property -dict [list CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V}] $sys_ps7 +set_property -dict [list CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V}] $sys_ps7 set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7 set_property -dict [list CONFIG.PCW_PACKAGE_NAME {clg225}] $sys_ps7 set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7 @@ -52,20 +52,27 @@ set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7 set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 -set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7 -set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7 -set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7 -set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7 -set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7 -set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {17}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0}] $sys_ps7 set_property -dict [list CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_UART1_UART1_IO {MIO 12 .. 13}] $sys_ps7 -set_property -dict [list CONFIG.PCW_USB0_RESET_IO {MIO 52}] $sys_ps7 -set_property -dict [list CONFIG.PCW_USB0_RESET_ENABLE {1}] $sys_ps7 -set_property -dict [list CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0}] $sys_ps7 set_property -dict [list CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SD0_PERIPHERAL_ENABLE {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7 +set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USB0_RESET_IO {MIO 52}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USB0_RESET_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7 # DDR MT41K256M16 HA-125 (32M, 16bit, 8banks) diff --git a/projects/m2k/standalone/system_constr.xdc b/projects/m2k/standalone/system_constr.xdc index f0d01adc1..09d3fd5a9 100644 --- a/projects/m2k/standalone/system_constr.xdc +++ b/projects/m2k/standalone/system_constr.xdc @@ -64,3 +64,133 @@ set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS33} [get_ports txd[11]] create_clock -period 10.000 -name rx_clk [get_ports rx_clk] create_clock -period 12.500 -name trigger_clk [get_ports {trigger_bd[0]}] create_clock -period 12.500 -name data_clk [get_ports {data_bd[0]}] + +set_input_jitter clk_fpga_0 0.3 +set_input_jitter clk_fpga_1 0.15 + +set_property IOSTANDARD LVCMOS18 [get_ports *fixed_io_mio*] +set_property SLEW SLOW [get_ports *fixed_io_mio*] +set_property DRIVE 8 [get_ports *fixed_io_mio*] +set_property -dict {PACKAGE_PIN D8 PULLTYPE PULLUP} [get_ports fixed_io_mio[ 0]] +set_property -dict {PACKAGE_PIN A5 PULLTYPE PULLUP} [get_ports fixed_io_mio[ 1]] +set_property -dict {PACKAGE_PIN A8 } [get_ports fixed_io_mio[ 2]] +set_property -dict {PACKAGE_PIN A7 } [get_ports fixed_io_mio[ 3]] +set_property -dict {PACKAGE_PIN C8 } [get_ports fixed_io_mio[ 4]] +set_property -dict {PACKAGE_PIN A9 } [get_ports fixed_io_mio[ 5]] +set_property -dict {PACKAGE_PIN A10 } [get_ports fixed_io_mio[ 6]] +set_property -dict {PACKAGE_PIN D9 } [get_ports fixed_io_mio[ 7]] +set_property -dict {PACKAGE_PIN B6 } [get_ports fixed_io_mio[ 8]] +set_property -dict {PACKAGE_PIN B5 PULLTYPE PULLUP} [get_ports fixed_io_mio[ 9]] +set_property -dict {PACKAGE_PIN D6 PULLTYPE PULLUP} [get_ports fixed_io_mio[10]] +set_property -dict {PACKAGE_PIN B10 PULLTYPE PULLUP} [get_ports fixed_io_mio[11]] +set_property -dict {PACKAGE_PIN B7 PULLTYPE PULLUP} [get_ports fixed_io_mio[12]] +set_property -dict {PACKAGE_PIN C6 PULLTYPE PULLUP} [get_ports fixed_io_mio[13]] +set_property -dict {PACKAGE_PIN B9 PULLTYPE PULLUP} [get_ports fixed_io_mio[14]] +set_property -dict {PACKAGE_PIN D10 PULLTYPE PULLUP} [get_ports fixed_io_mio[15]] +set_property -dict {PACKAGE_PIN A15 PULLTYPE PULLUP} [get_ports fixed_io_mio[16]] +set_property -dict {PACKAGE_PIN D11 PULLTYPE PULLUP} [get_ports fixed_io_mio[17]] +set_property -dict {PACKAGE_PIN B15 PULLTYPE PULLUP} [get_ports fixed_io_mio[18]] +set_property -dict {PACKAGE_PIN C12 PULLTYPE PULLUP} [get_ports fixed_io_mio[19]] +set_property -dict {PACKAGE_PIN E15 PULLTYPE PULLUP} [get_ports fixed_io_mio[20]] +set_property -dict {PACKAGE_PIN C11 PULLTYPE PULLUP} [get_ports fixed_io_mio[21]] +set_property -dict {PACKAGE_PIN D15 PULLTYPE PULLUP} [get_ports fixed_io_mio[22]] +set_property -dict {PACKAGE_PIN A14 PULLTYPE PULLUP} [get_ports fixed_io_mio[23]] +set_property -dict {PACKAGE_PIN B14 PULLTYPE PULLUP} [get_ports fixed_io_mio[24]] +set_property -dict {PACKAGE_PIN C14 PULLTYPE PULLUP} [get_ports fixed_io_mio[25]] +set_property -dict {PACKAGE_PIN A13 PULLTYPE PULLUP} [get_ports fixed_io_mio[26]] +set_property -dict {PACKAGE_PIN D14 PULLTYPE PULLUP} [get_ports fixed_io_mio[27]] +set_property -dict {PACKAGE_PIN B12 PULLTYPE PULLUP} [get_ports fixed_io_mio[28]] +set_property -dict {PACKAGE_PIN D13 PULLTYPE PULLUP} [get_ports fixed_io_mio[29]] +set_property -dict {PACKAGE_PIN A12 PULLTYPE PULLUP} [get_ports fixed_io_mio[30]] +set_property -dict {PACKAGE_PIN C13 PULLTYPE PULLUP} [get_ports fixed_io_mio[31]] + +set_property IOSTANDARD LVCMOS18 [get_ports *fixed_io_ps*] +set_property SLEW SLOW [get_ports *fixed_io_ps*] +set_property DRIVE 8 [get_ports *fixed_io_ps*] +set_property PACKAGE_PIN C7 [get_ports fixed_io_ps_clk] +set_property PACKAGE_PIN C9 [get_ports fixed_io_ps_porb] + +set_property IOSTANDARD SSTL15_T_DCI [get_ports *fixed_io_ddr_vr*] +set_property SLEW FAST [get_ports *fixed_io_ddr_vr*] +set_property PACKAGE_PIN H3 [get_ports fixed_io_ddr_vrp] +set_property PACKAGE_PIN J3 [get_ports fixed_io_ddr_vrn] + +set_property IOSTANDARD DIFF_SSTL15 [get_ports *ddr_ck*] +set_property SLEW FAST [get_ports *ddr_ck*] +set_property PACKAGE_PIN N3 [get_ports ddr_ck_p] +set_property PACKAGE_PIN N2 [get_ports ddr_ck_n] + +set_property IOSTANDARD SSTL15 [get_ports *ddr_addr*] +set_property SLEW SLOW [get_ports *ddr_addr*] +set_property PACKAGE_PIN P1 [get_ports ddr_addr[0]] +set_property PACKAGE_PIN N1 [get_ports ddr_addr[1]] +set_property PACKAGE_PIN M1 [get_ports ddr_addr[2]] +set_property PACKAGE_PIN M4 [get_ports ddr_addr[3]] +set_property PACKAGE_PIN P3 [get_ports ddr_addr[4]] +set_property PACKAGE_PIN P4 [get_ports ddr_addr[5]] +set_property PACKAGE_PIN P5 [get_ports ddr_addr[6]] +set_property PACKAGE_PIN M5 [get_ports ddr_addr[7]] +set_property PACKAGE_PIN P6 [get_ports ddr_addr[8]] +set_property PACKAGE_PIN N4 [get_ports ddr_addr[9]] +set_property PACKAGE_PIN J1 [get_ports ddr_addr[10]] +set_property PACKAGE_PIN L2 [get_ports ddr_addr[11]] +set_property PACKAGE_PIN M2 [get_ports ddr_addr[12]] +set_property PACKAGE_PIN K2 [get_ports ddr_addr[13]] +set_property PACKAGE_PIN K1 [get_ports ddr_addr[14]] + +set_property IOSTANDARD SSTL15 [get_ports *ddr_ba*] +set_property SLEW SLOW [get_ports *ddr_ba*] +set_property PACKAGE_PIN M6 [get_ports ddr_ba[0]] +set_property PACKAGE_PIN R1 [get_ports ddr_ba[1]] +set_property PACKAGE_PIN N6 [get_ports ddr_ba[2]] + +set_property IOSTANDARD SSTL15 [get_ports ddr_reset_n] +set_property SLEW FAST [get_ports ddr_reset_n] +set_property PACKAGE_PIN L4 [get_ports ddr_reset_n] +set_property IOSTANDARD SSTL15 [get_ports ddr_cs_n] +set_property SLEW SLOW [get_ports ddr_cs_n] +set_property PACKAGE_PIN R2 [get_ports ddr_cs_n] +set_property IOSTANDARD SSTL15 [get_ports ddr_ras_n] +set_property SLEW SLOW [get_ports ddr_ras_n] +set_property PACKAGE_PIN R6 [get_ports ddr_ras_n] +set_property IOSTANDARD SSTL15 [get_ports ddr_cas_n] +set_property SLEW SLOW [get_ports ddr_cas_n] +set_property PACKAGE_PIN R5 [get_ports ddr_cas_n] +set_property IOSTANDARD SSTL15 [get_ports ddr_we_n] +set_property SLEW SLOW [get_ports ddr_we_n] +set_property PACKAGE_PIN R3 [get_ports ddr_we_n] +set_property IOSTANDARD SSTL15 [get_ports ddr_cke] +set_property SLEW SLOW [get_ports ddr_cke] +set_property PACKAGE_PIN L3 [get_ports ddr_cke] +set_property IOSTANDARD SSTL15 [get_ports ddr_odt] +set_property SLEW SLOW [get_ports ddr_odt] +set_property PACKAGE_PIN K3 [get_ports ddr_odt] + +set_property IOSTANDARD SSTL15_T_DCI [get_ports *ddr_dq[*]] +set_property SLEW FAST [get_ports *ddr_dq[*]] +set_property PACKAGE_PIN D4 [get_ports ddr_dq[0]] +set_property PACKAGE_PIN A2 [get_ports ddr_dq[1]] +set_property PACKAGE_PIN C4 [get_ports ddr_dq[2]] +set_property PACKAGE_PIN C1 [get_ports ddr_dq[3]] +set_property PACKAGE_PIN B4 [get_ports ddr_dq[4]] +set_property PACKAGE_PIN A4 [get_ports ddr_dq[5]] +set_property PACKAGE_PIN C3 [get_ports ddr_dq[6]] +set_property PACKAGE_PIN A3 [get_ports ddr_dq[7]] +set_property PACKAGE_PIN E1 [get_ports ddr_dq[8]] +set_property PACKAGE_PIN D1 [get_ports ddr_dq[9]] +set_property PACKAGE_PIN E2 [get_ports ddr_dq[10]] +set_property PACKAGE_PIN E3 [get_ports ddr_dq[11]] +set_property PACKAGE_PIN F3 [get_ports ddr_dq[12]] +set_property PACKAGE_PIN G1 [get_ports ddr_dq[13]] +set_property PACKAGE_PIN H1 [get_ports ddr_dq[14]] +set_property PACKAGE_PIN H2 [get_ports ddr_dq[15]] +set_property IOSTANDARD SSTL15_T_DCI [get_ports *ddr_dm[*]] +set_property SLEW FAST [get_ports *ddr_dm[*]] +set_property PACKAGE_PIN B1 [get_ports ddr_dm[0]] +set_property PACKAGE_PIN D3 [get_ports ddr_dm[1]] +set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports *ddr_dqs*] +set_property SLEW FAST [get_ports *ddr_dqs*] +set_property PACKAGE_PIN C2 [get_ports ddr_dqs_p[0]] +set_property PACKAGE_PIN B2 [get_ports ddr_dqs_n[0]] +set_property PACKAGE_PIN G2 [get_ports ddr_dqs_p[1]] +set_property PACKAGE_PIN F2 [get_ports ddr_dqs_n[1]] diff --git a/projects/m2k/standalone/system_project.tcl b/projects/m2k/standalone/system_project.tcl index 38d329e96..6e349259a 100644 --- a/projects/m2k/standalone/system_project.tcl +++ b/projects/m2k/standalone/system_project.tcl @@ -12,5 +12,6 @@ adi_project_files m2k [list \ "system_constr.xdc" \ "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] +set_property is_enabled false [get_files *system_sys_ps7_0.xdc] adi_project_run m2k diff --git a/projects/m2k/standalone/system_top.v b/projects/m2k/standalone/system_top.v index 97153f6df..166c06e95 100644 --- a/projects/m2k/standalone/system_top.v +++ b/projects/m2k/standalone/system_top.v @@ -85,7 +85,9 @@ module system_top ( // internal signals - wire [63:0] gpio_o; + wire [16:0] gpio_i; + wire [16:0] gpio_o; + wire [16:0] gpio_t; wire [15:0] data_i; wire [15:0] data_o; @@ -100,9 +102,6 @@ module system_top ( wire spi0_mosi; wire spi0_miso; - assign ad9963_resetn = gpio_o[32]; - assign en_power_analog = gpio_o[33]; - assign ad9963_csn = spi0_csn[0]; assign adf4360_cs = spi0_csn[1]; assign spi_clk = spi0_clk; @@ -111,6 +110,13 @@ module system_top ( // instantiations + ad_iobuf #(.DATA_WIDTH(2)) i_iobuf ( + .dio_t (gpio_t[ 1:0]), + .dio_i (gpio_o[ 1:0]), + .dio_o (gpio_i[ 1:0]), + .dio_p ({ en_power_analog, + ad9963_resetn})); + ad_iobuf #( .DATA_WIDTH(16) ) i_data_bd ( @@ -157,9 +163,9 @@ module system_top ( .fixed_io_ps_clk (fixed_io_ps_clk), .fixed_io_ps_porb (fixed_io_ps_porb), .fixed_io_ps_srstb (fixed_io_ps_srstb), - .gpio_i (64'h0), + .gpio_i (gpio_i), .gpio_o (gpio_o), - .gpio_t (), + .gpio_t (gpio_t), .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), .data_i(data_i),